推荐-组合逻辑电路的VHDL设计 精品

VHDL 数字逻辑电路设计19例第1章组合逻辑电路8例1. 2-4译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq24 ISPORT (EN,A,B:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(3 downto 0 ));END ENTITY ymq24 ;ARCHITECTURE rt1 OF ymq24 ISSIGNAL T:STD_LOGIC_vector(1 downto 0 );BEGINT<=A & B;process(EN,T)beginIF EN='1' THEN YN<="1111";ELSIF T="00" THEN YN<="1110";ELSIF T="01" THEN YN<="1101";ELSIF T="10" THEN YN<="1011";ELSE YN<="0111";END IF;End process;END ARCHITECTURE rt1;2. 3-8译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq38 ISPORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END ENTITY ymq38 ;ARCHITECTURE rt1 OF ymq38 ISSIGNAL T1,T2:STD_LOGIC_vector(2 downto 0 );BEGINT1<=A & B & C;T2<=G1 & G2N & G3N;process(G1,G2N,G3N,T1,T2)beginIF T2/="100" THEN YN<="11111111";ELSIF T1="000" THEN YN<="11111110";ELSIF T1="001" THEN YN<="11111101";ELSIF T1="010" THEN YN<="11111011";ELSIF T1="011" THEN YN<="11110111";ELSIF T1="100" THEN YN<="11101111";ELSIF T1="101" THEN YN<="11011111";ELSIF T1="110" THEN YN<="10111111";ELSE YN<="01111111";END IF;End process;END ARCHITECTURE rt1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq41 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq41;ARCHITECTURE rt1 OF xzq41 ISsignal s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS<= a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "00"=> Y<=d(0);WHEN "01"=> Y<=d(1);WHEN "10"=> Y<=d(2);WHEN "11"=> Y<=d(3);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq81 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq81;ARCHITECTURE rt1 OF xzq81 ISsignal s: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINS<= a2 & a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "000"=> Y<=d(0);WHEN "001"=> Y<=d(1);WHEN "010"=> Y<=d(2);WHEN "011"=> Y<=d(3);WHEN "100"=> Y<=d(4);WHEN "101"=> Y<=d(5);WHEN "110"=> Y<=d(6);WHEN "111"=> Y<=d(7);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l75 ISPORT (A,B,C:IN STD_LOGIC;d,g : OUT STD_LOGIC);END ENTITY l75 ;ARCHITECTURE rt1 OF l75 ISCOMPONENT ymq38PORT (G1, G2N, G3N, A, B, C: IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END COMPONENT ;signal ynt : STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1','0','0',a,b,c,YNt(7 DOWNTO 0));d<=not(ynt(1) and ynt(2) and ynt(4) and ynt(7));g<=not(ynt(1) and ynt(2) and ynt(3) and ynt(7));END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l76 ISPORT (A,B,C,D:IN STD_LOGIC;F : OUT STD_LOGIC);END ENTITY l76 ;ARCHITECTURE rt1 OF l76 ISCOMPONENT ymq38PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 ));END COMPONENT ;signal yn1t:STD_LOGIC_vector(7 downto 0 );signal yn2t:STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1',A,'0',B,C,D,YN1t(7 DOWNTO 0));U2 :ymq38 PORT MAP (A,'0','0',B,C,D,YN2t(7 DOWNTO 0));F<=not( yn1t(2) and yn1t(4) and yn1t(6) and yn2t(0) and yn2t(2) and yn2t(4) and yn2t(6)); END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq81PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;BEGINU1 :xzq81 PORT MAP ('0',"01101100",c,b,a,f);END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq41PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;signal t:STD_LOGIC;signal dt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINt<= not c;dt<=t & c & '1' & '0';U1 :xzq41 PORT MAP ('0',dt,b,a,f);【作业】以下所有题目必须用VHDL代码实现。

实验二 组合逻辑电路的VHDL 设计一、实验目的与要求 1、目的（1）熟悉VHDL 语言的基本结构（2）掌握用VHDL 语言实现组合逻辑功能器件的逻辑功能的一般方法。

2、要求（1）调试程序要记录调试过程中出现的问题及解决办法； （2）给出每个问题的算法或画出流程图；（3）编写程序要规范、正确，上机调试过程和结果要有记录，并注意调试程序集成环境的掌握及应用，不断积累编程及调试经验； （4）做完实验后给出本实验的实验报告。

二、实验设备、环境PII 以上计算机，装有QuartusII 软件 三、方法与步骤（一）教师简单回顾所需知识并演示较一个简单功能的实现过程。

1、 简单回顾组合逻辑电路的特点及常用逻辑功能器件的功能 2、 回顾QuartusII 的VHDL 操作步骤3、 以4选1数据选择器为例，重点演示该组合逻辑单元的VHDL 设计过程。

（1）4选1数据选择器的真值表与电路符号（2）4选1数据选择器的参考VHDL 程序LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 ISPORT(S ：IN STD_LOGIC_VECTOR (1 DOWNTO 0); A,B,C,D ： IN STD_LOGIC; Y ：OUT STD_LOGIC );地址输入输出S0 S1 0 0 A 0 1 B 1 0 C 11DS[1..0]A B C DYMULTI_4VA B C DS[1..0]YEND mux41;ARCHITECTURE a OF mux41 ISBEGINPROCESS (s,A,B,C,D)BEGINIF (S="00") THENY <= A;ELSIF (S="01") THENY <= B;ELSIF (S="10") THENY <= C;ELSIF (S="11") THENY <= D;END IF;END PROCESS;END a;四、实验过程、内容、数据处理及分析按照设计选题编写简单程序1、可供选择进行设计的组合逻辑电路如下，要求规定课时内至少完成3种逻辑电路的设计。

VHDL 数字逻辑电路设计19例第1章组合逻辑电路8例1. 2-4译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq24 ISPORT (EN,A,B:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(3 downto 0 ));END ENTITY ymq24 ;ARCHITECTURE rt1 OF ymq24 ISSIGNAL T:STD_LOGIC_vector(1 downto 0 );BEGINT<=A & B;process(EN,T)beginIF EN='1' THEN YN<="1111";ELSIF T="00" THEN YN<="1110";ELSIF T="01" THEN YN<="1101";ELSIF T="10" THEN YN<="1011";ELSE YN<="0111";END IF;End process;END ARCHITECTURE rt1;2. 3-8译码器USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq38 ISPORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END ENTITY ymq38 ;ARCHITECTURE rt1 OF ymq38 ISSIGNAL T1,T2:STD_LOGIC_vector(2 downto 0 );BEGINT1<=A & B & C;T2<=G1 & G2N & G3N;process(G1,G2N,G3N,T1,T2)beginIF T2/="100" THEN YN<="11111111";ELSIF T1="000" THEN YN<="11111110";ELSIF T1="001" THEN YN<="11111101";ELSIF T1="010" THEN YN<="11111011";ELSIF T1="011" THEN YN<="11110111";ELSIF T1="100" THEN YN<="11101111";ELSIF T1="101" THEN YN<="11011111";ELSIF T1="110" THEN YN<="10111111";ELSE YN<="01111111";END IF;End process;END ARCHITECTURE rt1;3. 4选1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq41 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq41;ARCHITECTURE rt1 OF xzq41 ISsignal s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS<= a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;4. 8选1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq81 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq81;ARCHITECTURE rt1 OF xzq81 ISsignal s: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINS<= a2 & a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "000"=> Y<=d(0);WHEN "001"=> Y<=d(1);WHEN "110"=> Y<=d(6);WHEN "111"=> Y<=d(7);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;5. 例75LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l75 ISPORT (A,B,C:IN STD_LOGIC;d,g : OUT STD_LOGIC);END ENTITY l75 ;ARCHITECTURE rt1 OF l75 ISCOMPONENT ymq38PORT (G1, G2N, G3N, A, B, C: IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END COMPONENT ;signal ynt : STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1','0','0',a,b,c,YNt(7 DOWNTO 0));d<=not(ynt(1) and ynt(2) and ynt(4) and ynt(7));g<=not(ynt(1) and ynt(2) and ynt(3) and ynt(7));END ARCHITECTURE rt1;6. 例76LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l76 ISPORT (A,B,C,D:IN STD_LOGIC;F : OUT STD_LOGIC);END ENTITY l76 ;ARCHITECTURE rt1 OF l76 ISCOMPONENT ymq38PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 ));END COMPONENT ;signal yn1t:STD_LOGIC_vector(7 downto 0 );signal yn2t:STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1',A,'0',B,C,D,YN1t(7 DOWNTO 0));U2 :ymq38 PORT MAP (A,'0','0',B,C,D,YN2t(7 DOWNTO 0));F<=not( yn1t(2) and yn1t(4) and yn1t(6) and yn2t(0) and yn2t(2) and yn2t(4) and yn2t(6)); END ARCHITECTURE rt1;7. 例78-1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq81PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;BEGINU1 :xzq81 PORT MAP ('0',"01101100",c,b,a,f);END ARCHITECTURE rt1;8. 例78-2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq41PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;signal t:STD_LOGIC;signal dt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINt<= not c;dt<=t & c & '1' & '0';U1 :xzq41 PORT MAP ('0',dt,b,a,f);【作业】以下所有题目必须用VHDL代码实现。

实验一组合逻辑电路的VHDL设计实验报告(1) 实验目的：熟悉QuartusⅡ的VHDL文本设计流程全过程，学习简单组合电路的设计、多层次电路设计、仿真和硬件测试。

(2) 实验内容1：用VHDL语言设计2选1多路选择器。

提示：参考例3-1。

要求：首先利用QuartusⅡ完成2选1多路选择器的文本编辑输入和编译、仿真测试等步骤，给出时序仿真波形。

选择目标器件EP1C3，建议选实验电路模式5，如附图1所示。

用键1(PIO0，引脚号为1)控制s；a和b分别接clock0(引脚号为93)和clock2(引脚号为17)；输出信号y接扬声器speaker(引脚号为129)。

通过短路帽选择clock0接256Hz信号，clock2接8Hz信号。

引脚锁定后进行编译、下载和硬件测试实验，通过键1控制s，可使扬声器输出不同音调。

(3) 实验内容2：将此二选一多路选择器看成是一个元件mux21a，利用元件例化语句描述图2所示电路，并将此文件放在同一目录中。

图2 双2选1多路选择器要求：首先利用QuartusⅡ完成2选1多路选择器的文本编辑输入和编译、仿真测试等步骤，给出时序仿真波形。

然后进行引脚锁定以及硬件下载测试。

选择目标器件EP1C3，建议选实验电路模式5（附图1），用键1(PIO0，引脚号为1)控制s0；用键2(PIO1，引脚号为2)控制s1；a3、a2和a1分别接clock5(引脚号为16)、clock0(引脚号为93)和clock2(引脚号为17)；输出信号outy仍接扬声器spker(引脚号为129)。

通过短路帽选择clock0接256Hz信号，clock5接1024Hz，clock2接8Hz信号。

通过选择键1、键2，控制s0、s1，可使扬声器输出不同音调。

(4)程序设计程序1：LIBRARY IEEE;use ieee.std_logic_1164.all;entity mux21a isport(a,b,s:in std_logic;y:out std_logic);end entity mux21a;architecture one of mux21a isbeginPROCESS(s,a,b)BEGINCASE S ISWHEN '0' => y <= a;WHEN '1' => y <= b;WHEN OTHERS =>NULL ;END CASE;END PROCESS;end architecture one;程序2：library ieee;use ieee.std_logic_1164.all;entity muxk isport(a1,a2,a3,s0,s1:in std_logic; outy: out std_logic);end entity muxk;architecture one of muxk issignal tmp: std_logic;component mux21aport(a,b,s: in std_logic;y:out std_logic);end component;beginu1: mux21a port map(a=>a2,b=>a3,s=>s0,y=>tmp);u2: mux21a port map(a=>a1,b=>tmp,s=>s1,y=>outy);end architecture one;(5)实验过程打开软件，点击新建建立一个VHDL FILE,将编写好的程序拷进去点击保存根据提示新建一个以实体名为名的工程并选择芯片，程序名也与实体名一致。