`timescale 1ns/10ps
module top_bench;
reg clk;
reg rst_n;
reg [2:0] addr;
reg scl;
reg sda_in;
reg [12:0]vsamp;
reg clk_hb3_out;
//output
wire evnt;
wire sdaout;
wire sda_en;
wire [7:0] dat_from_slave;
wire [7:0] dat_to_slave;
wire swp;
wire shutdn;
wire spd_pt_rdy;
wire spd_data_rdy;
wire [12:0]tout;
wire rd_cns;
integer i;
DCORE_top top_0 (.clk_m(clk),
.rst_n(rst_n),
.addr(addr[2:0]),
.scl(scl),
.sdain(sda_in),
.vsamp(vsamp[12:0]),
.clk_hb3_out(clk_hb3_out),
//output
.evnt(evnt),
.sdaout(sdaout),
.sda_en(sda_en),
.dat_from_slave(dat_from_slave[7:0]),
.dat_to_slave(dat_to_slave[7:0]),
.swp(swp),
.shutdn(shutdn),
.proccessing(proccessing),
.spd_pt_rdy(spd_pt_rdy),
.spd_data_rdy(spd_data_rdy),
.tout(tout[12:0]),
.rd_cns(rd_cns));
initial
begin
scl=1;
clk=0;
sda_in=1;
addr[2:0]=3'h0;
vsamp[12:0]=0;
clk_hb3_out=1'b0;
end
//
always
begin
#937.5 scl = 1; //400k
#1562.5 scl = 0; //400k
end
always #156.25 clk = ~clk; //3.2M
//always #2500 scl = ~scl; //200k
//always #5000 scl = ~scl; //100k
//always #10000 scl = ~scl; //50k
//always #12500 scl = ~scl; //40k
//always #50000 scl = ~scl; //10k
//always #156.25 clk = ~clk; //3.2M
//always #312.5 clk = ~clk; //1.6M
//always #6250 clk = ~clk; //80k
initial
begin
rst_n=1;
addr[2:0]=3'h0;
#30
rst_n=0;
#500
rst_n=1;
#200
#100000000
//******************
// test SPD
//******************
/*
start;
i2c_instruction(8'h62);//write swp
ptr(8'h10);
data_in(8'h10);
stop;
#10000000
start;
i2c_instruction(8'h60);//write pswp
ptr(8'h10);
data_in(8'h10);
stop;
#150000000
start;
i2c_instruction(8'h62);//write swp
ptr(8'h10);
data_in(8'h10);
stop;
#10000000
rst_n=0;
#400
rst_n=1;
#4000000
*/
start;
i2c_instruction(8'ha0);
ptr(8'h01);
data_in(8'h55);
data_in(8'h4f);
data_in(8'h03);
stop;
#150000000
start;
i2c_instruction(8'ha0);
ptr(8'h01);
start;
i2c_instruction(8'ha1);
wt_rpt1;
wt_rpt1;
wt_rpt1;
stop;
#10000000
/*
start;
i2c_instruction(8'h66);//clear swp
ptr(8'h10);
data_in(8'h10);
stop;
#150000000
start;
i2c_instruction(8'h18);//clear pswp
ptr(8'h10);
data_in(8'h10);
stop;
#150000000
*/
start;
i2c_instruction(8'ha0);
ptr(8'h00);
data_in(8'h70);
data_in(8'hdd);
data_in(8'h32);
stop;
#150000000
start;
i2c_instruction(8'ha0);
ptr(8'h00);
start;
i2c_instruction(8'ha1);
wt_rpt1;
wt_rpt1;
wt_rpt1;
stop;
#10000000
start;
i2c_instruction(8'ha0);//write mode squences
ptr(8'h09);
data_in(8'h54);
data_in(8'h10);
data_in(8'h00);
data_in(8'h5c);
data_in(8'h00);
data_in(8'h30);
stop;
#2500000
start;
i2c_instruction(8'ha0);//read mode squences
ptr(8'h09);
start;
i2c_instruction(8'ha1);
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
stop;
#1000000
start;
i2c_instruction(8'ha0);//write spd one byte
ptr(8'h01);
data_in(8'h34);
stop;
#2500000
start;
i2c_instruction(8'ha0);//read spd one byte
ptr(8'h01);
start;
i2c_instruction(8'ha1);
wt_rpt1;
stop;
#50000
/*
start;
i2c_instruction(8'h66);//clear swp
ptr(8'h10);
data_in(8'h10);
stop;
#10000000
*/
/*
start;
i2c_instruction(8'h60);//write pswp
ptr(8'h10);
data_in(8'h10);
stop;
#50000
*/
start;
i2c_instruction(8'ha0);//write spd one byte
ptr(8'h82);
data_in(8'h10);
stop;
#2500000
start;
i2c_instruction(8'ha0);//read spd one byte
ptr(8'h82);
start;
i2c_instruction(8'ha1);
wt_rpt1;
stop;
#50000
start;
i2c_instruction(8'ha0);//write mode squences
ptr(8'h90);
data_in(8'h04);
data_in(8'h10);
data_in(8'h40);
data_in(8'h60);
data_in(8'h20);
data_in(8'h90);
stop;
#2500000
start;
i2c_instruction(8'ha0);//read mode squences
ptr(8'h90);
start;
i2c_instruction(8'ha1);
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
stop;
#1000000
start;
i2c_instruction(8'ha0);
ptr(8'h00);
data_in(8'h04);//write cns_flag
data_in(8'h10);//write cp[15:8]
data_in(8'h00);//write cp[7:0],cp=0.25
data_in(8'h5c);//write mm[15:8]
data_in(8'h00);//write mm[7:0],mm=92
data_in(8'h30);//write pe[15:0]
data_in(8'h00);//write pe[7:0],pe=3
data_in(8'h00);
stop;
#2500000
start;
i2c_instruction(8'ha0);//read constants
ptr(8'h00);
start;
i2c_instruction(8'ha1);
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
wt_rpt1;
stop;
#300000
//*****************
// RST
//*****************
rst_n=0;
#400
rst_n=1;
#40000000
//******************
// test system read
//******************
#10000
start;
i2c_instruction(8'ha0);//clear cns_flag
ptr(8'h00);
data_in(8'h00);
stop;
#2500000
start;
i2c_instruction(8'ha0);
ptr(8'h00);//read eeprom address 00
start;
i2c_instruction(8'ha1);
wt_rpt1;
stop;
#10000000
//*****************
// RST
//*****************
rst_n=0;
#400
rst_n=1;
#40000000
//******************
// test TS
//******************
start;
i2c_instruction(8'h30); //write high limit reg
ptr(8'h02);
data_in(8'h02);//hlr=16'h0228=34.5C
data_in(8'h28);
stop;
start;
i2c_instruction(8'h30); //read high limit reg
ptr(8'h02);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem~= 35C
#1000
start;
i2c_instruction(8'h30); //write low limit reg
ptr(8
'h03);
data_in(8'h1e);//llr=-27C
data_in(8'h30);
stop;
#1000
vsamp_in(13'h1808);//vsamp ~= -0.9922,tsamp ~= -56.606, Tem > -55C
#1000
start;
i2c_instruction(8'h30); //read low limit reg
ptr(8'h03);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
start;
i2c_instruction(8'h30); //write critical limit reg
ptr(8'h04);
data_in(8'h06);//clr=100C
data_in(8'h40);
stop;
start;
i2c_instruction(8'h30); //read critical limit reg
ptr(8'h04);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
start;
i2c_instruction(8'h30); //write high limit reg
ptr(8'h02);
data_in(8'h04);//hlr=16'h0428=66.5C
data_in(8'h28);
stop;
start;
i2c_instruction(8'h30);//write configration reg
ptr(8'h01);
data_in(8'h00);
data_in(8'hc8);//lock clr, hlr and llr ,unmask evnt pin,comparator mode
stop;
#1000000
start;
i2c_instruction(8'h30); //write high limit reg
ptr(8'h02);
data_in(8'h05);
data_in(8'h36);
stop;
start;
i2c_instruction(8'h30); //read high limit reg
ptr(8'h02);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
start;
i2c_instruction(8'h30); //write low limit reg
ptr(8'h03);
data_in(8'h1f);
data_in(8'h50);
stop;
#1000
start;
i2c_instruction(8'h30); //read low limit reg
ptr(8'h03);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
start;
i2c_instruction(8'h30); //write critical limit reg
ptr(8'h04);
data_in(8'h05);
data_in(8'h30);
stop;
start;
i2c_instruction(8'h30); //read critical limit reg
ptr(8'h04);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
//*****************
// comparator mode
//*****************
vsamp_in(13'h0720);//vsamp=0.890625 ,tsamp ~= 116.9,Tem ~= 116.69C
#10000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem~= 35C
#10000
vsamp_in(13'h1999); //vsamp ~= -0.796875 ,tsamp ~= -38.607, Tem~= -38.78C.
#10000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem~= 35C
#10000
//*****************
// RST
//*****************
rst_n=0;
#400
rst_n=1;
#40000000
start;
i2c_instruction(8'h30); //write low limit reg
ptr(8'h03);
data_in(8'h1e);//llr=-27C
data_in(8'h30);
stop;
#1000
start;
i2c_instruction(8'h30); //write critical limit reg
ptr(8'h04);
data_in(8'h06);//clr=100C
data_in(8'h40);
stop;
start;
i2c_instruction(8'h30); //write high limit reg
ptr(8'h02);
data_in(8'h04);//hlr=16'h0428=66.5C
data_in(8'h28);
stop;
//*****************
// interrupt mode
//*****************
start;
i2c_instruction(8'h30);//write configration reg
ptr(8'h01);
data_in(8'h00);
data_in(8'h09);//interrupt mode
stop;
#200
start;
i2c_instruction(8'h30); //read configration reg
ptr(8'h01);
start;
i2c_instruction(8'h31);
wt_rpt1;
wt_rpt1;
stop;
#1000
vsamp_in(13'h0720);//vsamp=0.890625 ,tsamp ~= 116.9,Tem ~= 116.69C
#10000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem
~= 35C
#10000
start;
i2c_instruction(8'h30);//write configration reg
ptr(8'h01);
data_in(8'h02);
data_in(8'h29);//clear bit
stop;
#200000
vsamp_in(13'h0720);//vsamp=0.890625 ,tsamp ~= 116.9,Tem ~= 116.69C
#10000
vsamp_in(13'h1999); //vsamp ~= -0.796875 ,tsamp ~= -38.607, Tem~= -38.78C.
#10000
start;
i2c_instruction(8'h30);//write configration reg
ptr(8'h01);
data_in(8'h02);
data_in(8'h29);//clear bit
stop;
#2000
vsamp_in(13'h1b20); //vsamp ~= -0.6003 ,tsamp ~= -20C
#10000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem~= 35C
#10000
start;
i2c_instruction(8'h30);//write configration reg
ptr(8'h01);
data_in(8'h02);
data_in(8'h29);//clear bit
stop;
#200
//*********************
// critical only mode
//*********************
start;
i2c_instruction(8'h30);
ptr(8'h01);
data_in(8'h02);
data_in(8'h0c);
stop;
#10000
vsamp_in(13'h0720);//vsamp=0.890625 ,tsamp ~= 116.9,Tem ~= 116.69C
#10000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem~= 35C
#10000
vsamp_in(13'h1999); //vsamp ~= -0.796875 ,tsamp ~= -38.607, Tem~= -38.78C.
#10000
vsamp_in(13'h0720);//vsamp=0.890625 ,tsamp ~= 116.9,Tem ~= 116.69C
#10000
vsamp_in(13'h0040);//vsamp=0.03125 ,tsamp ~=37.71, Tem~= 35C
#10000000
/*
start;
i2c_instruction(8'h18);//clear pswp
ptr(8'h10);
data_in(8'h10);
stop;
#1000000000
*/
$finish;
end
task start;
begin
@(negedge scl)
sda_in = 1;
@(posedge scl)
#100 sda_in = 0;
end
endtask
task stop;
begin
@(negedge scl)
#300
sda_in=1'b0;
@(posedge scl)
#300
sda_in = 1'b1;
end
endtask
task i2c_instruction;
input [7:0]reg_w;
begin
@(negedge scl)
sda_in = reg_w[7];
@(negedge scl)
sda_in = reg_w[6];
@(negedge scl)
sda_in = reg_w[5];
@(negedge scl)
sda_in = reg_w[4];
@(negedge scl)
sda_in = reg_w[3];
@(negedge scl)
sda_in = reg_w[2];
@(negedge scl)
sda_in = reg_w[1];
@(negedge scl)
sda_in = reg_w[0];
@(negedge scl)
i=100;
end
endtask
task ptr;
input [7:0]pt;
begin
@(negedge scl)
sda_in = pt[7];
@(negedge scl)
sda_in = pt[6];
@(negedge scl)
sda_in = pt[5];
@(negedge scl)
sda_in = pt[4];
@(negedge scl)
sda_in = pt[3];
@(negedge scl)
sda_in = pt[2];
@(negedge scl)
sda_in = pt[1];
@(negedge scl)
sda_in = pt[0];
@(negedge scl)
i=100;
end
endtask
task data_in;
input [7:0]data;
begin
@(negedge scl)
sda_in = data[7];
@(negedge scl)
sda_in = data[6];
@(negedge scl)
sda_in = data[5];
@(negedge scl)
sda_in = data[4];
@(negedge scl)
sda_in = data[3];
@(negedge scl)
sda_in = data[2];
@(negedge scl)
sda_in = data[1];
@(negedge scl)
sda_in = data[0];
@(negedge scl)
i=100;
end
endtask
task wt_rpt;
begin
repeat(17)
begin
@(negedge scl)
i=100;
end
end
endtask
task wt_rpt1;
begin
repeat(9)
begin
@(negedge scl)
i=100;
end
end
endtask
tas
k vsamp_in;
input [12:0]samp_data;
begin
@(negedge clk)
begin
clk_hb3_out =1;
vsamp[12:0]=samp_data[12:0];
end
@(negedge clk)
clk_hb3_out =0;
end
endtask
initial
begin
$sdf_annotate("dig_pr2.sdf",DCORE_top,,,"TYPICAL",,);
end
`ifdef DUMP_FSDB
initial
begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars;
end
`endif
endmodule