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Multi-Valued Simulation with Binary Decision Diagrams

Multi-Valued Simulation with Binary Decision Diagrams
Multi-Valued Simulation with Binary Decision Diagrams

MULTI-VALUED SIMULATION

WITH BINARY DECISION DIAGRAMS

Raimund UBAR, Jaan RAIK

Technical University of Tallinn,

Ehitajate tee 5, EE0026, Tallinn, ESTONIA

Fax: (+372) 620 2226, E-mail: raiub@pld.ttu.ee

Abstract. The paper presents a new method for multivalued simulation of digital circuits based on calculation of Boolean derivatives on BDDs (or structural alternative graphs). A procedure for calculation of maximums of Boolean derivatives as the basis of multivalued simulation is given. The method is applicable for component level representations of digital circuits where as components arbitrary subcircuits (macros) instead of gates are considered. No dedicated model library for multivalued simulation is needed. Instead of dedicated multi-valued models, generic ones in the form of BDDs are used. Implementation areas of multivalued simulation for delay fault testing and hazard analysis are discussed. Advantages of the new approach compared to the traditional gate-level multi-valued simulation are shown. Experimental data for ISCAS benchmarks to demonstrate these advantages are also included.

1. INTRODUCTION

Test pattern generation and fault simulation procedures for digital circuits, because of the need for high computational speed are usually based on simplified two-valued simulation. This results in the following consequences:

- transitions between patterns in the test sequence can have transient pulses caused by hazards, which may result in the loss of credibility of test sequences in detecting faults of asynchronous circuits;

- it is not possible to generate test patterns for faults in functionally redundant parts of the design;

- it is not possible to generate or analyse the quality of test sequences for delay faults.

The shortages of test design methods listed above can be overcome by using dynamic analysis methods based on multi-valued simulation.

Multivalued simulation has been used for: detecting hazards in digital circuits [1], delay fault analysis and test synthesis [2], fault cover analysis and test synthesis for the case of dynamic testing [3] etc. In this approach, to each value from the given alphabet of signal values a special stylized waveform corresponds. The number of values (waveform types) can be different. Three-, five-, six-, eigth-, nine-valued simulation alphabets are common.

The drawbacks of traditional multi-valued simulation methods are the following:

- traditionally gate-level descriptions are used, which increases the complexity of the model and reduces the computational speed;

- representing of circuits under test by two-input gates is mandatory;

- when introducing macroblocks into the use, each macroblock should have its own computational model.

In this paper for removing the listed drawbacks, a novel method for multivalued simulation is discussed, which lays on using Boolean differential calculus and alternative graphs.

2. MULTI-VALUED SIMULATION IN GATE-LEVEL CIRCUITS

For the purpose of delay fault detection, the line waveforms can be considered to be members of the waveform-type set S = {0, 1, ε, h, 0*, 1*, ε*, h*, x}. The members of S are described as follows: 0 (1) represents a type of waveform having a stable logic value 0 (1); ε (h) represents a waveform having a step-up transition from 0 to a final value of 1 (step-down transition from 1 to a final value of 0); 0* (1*) represents a waveform having a final value 0 (1) with a static hazard occuring over the transition period; ε* (h*) represents a waveform having a step-up transition from 0 to 1 (step-down transition from 1 to 0) with a dynamic hazard occuring over the transition period, and x represents unknown waveform. Modifications of the set S3 are: S = {0, 1, x} for 3-valued simulation, S5 = {0, 1, ε, h, x}for 5-valued simulation, S6 = {0, 1, ε, h, 0*, 1*}for 6-valued simulation etc.

Due to physical behaviors and the existence of delays of logic components, every line in the circuit can have one of the mentioned waveform-types of S. Correspondingly, the dynamic behavior of the circuit during one single transition period will be represented also by waveforms of S on the outputs of the circuit. Every gate in the circuit network can be regarded as an operator which computes the output value of the gate if the values on the inputs are given. The operators for OR, AND and NOT gates in the case of five-valued simulation are depicted in Table 1.

Table 1

O R 0 1 ε h x A

N

D

0 1 ε h

x

N

O

T

0 0 1 ε h x 0 0 0 0 0

0 1

1 1 1 1 1 1 1 0 1 ε h

x

1 0

εε 1 ε x x ε 0

εε x

x

εh

h h 1 x h x h 0 h x h

x

h ε

x x 1 x x x x 0 x x x

x

x x

From Table 1 and its transitivity we can compute the logic value of any line in the circuit which is represented as a network of two-input logic gates OR, AND or NOT. Similar tables can be easily derived for other alphabets S6, S8 etc.

3. MULTI-VALUED SIMULATION AND BOOLEAN DERIVATIVES

Let us represent a digital circuit by equivalent parenthesis form (EPF) synthesized by superposition procedure directly from the circuit. For synthesizing the EPF for a given circuit, numbers are first assigned to the gates and letters to the nets. Then, starting at an output and working back toward primary inputs, EPF replaces individual literals by products of literals or sums of literals. When an AND gate is encountered during backtracing, a product term is created in which the literals are the names of nets connected to the inputs of the AND gate. Encountering an OR gate causes a sum of literals to be formed, while encountering an inverter causes a literal to be complemented.

As an example the procedure is illustrated by transforming the circuit in Fig.1 to its equivalent parenthesis form:

Y = (a1 b1) = (c12 + d12)(m13 + e13) =

(g124 h124 + f125 k125)(m13 + ?k136) =

=

(g124 h124 + ?h1257 k125)(m13 + ?k136).

= Array

Fig.1. Digital circuit for creating the equivalent parenthesis form

When creating an equation by the superposition procedure described above, the identity of every signal path from the inputs to the outputs of the given circuit will be retained. Each literal in an EPF consists of a subscripted input variable or its complement, which identifies a path from the variable to the output. From the manner in which the EPF is constructed, it can be seen that there will be at least one subscripted literal for every path from each input variable to the output. It is also easy to see that the complemented literals correspond to paths, which contain an odd number of inversions.

Let us have an EPF y = f(x1, x2, ... x i, ... x n) where x i are literals, which describes the behavior of a digital circuit. If a transition occurs on the input and affects the path denoted by x i, then the transition will propagate up to the output y if ?y/?x i = 1, where ?y/?x i is called partial Boolean derivative. In general case, if transitions occur on several inputs or a transition has a fan-out and propagates along several reconvergent paths, then the derivative ?y/?x i may have a dynamic value d∈V D. As ?y/?x i = d is the case, we are not allowed to exclude the possibility that during the transition a short period may exist where d = 1 happens. Hence, the statement made above can be generalized as follows: if a transition occurs on the input x i, then the transition from x i will propagate up to the output y if max{?y/?x i} = 1 is valid over the transition period. Now, the following two theorems can be easily proved.

Theorem 1.

The value of the EPF y = f(X) = f(x1, x2, ... x i, ... x n) for the given digital circuit in multivalued alphabet will be static if

?x i∈X: max{?y/?x i} = 0,

x j∈X D

where X D? X is the set of literals whose values are dynamic.

Theorem 2.

If X D ∩{x i? max{?y/?x i} = 1}≠? then the value of y can be calculated as the function of AND (or OR) of values of x i for x i∈ X D ∩{x i? max{?y/?x i} = 1}.

Proof. If the transition occurs on a single input x i with max{?y/?x i} = 1 then y = x i, i.e. the same transition (or its complement if x i is inverted) occurs on the output. Otherwise, if several transitions on inputs x i for x i∈X D ∩{x i? max{?y/?x i} = 1}are propagating through the circuit, these paths can reconverge only on inputs of either AND or OR gates.

From Theorems 1 and 2 an algorithm can be developed for multivalued simulation of digital circuits

based on calculating Boolean derivatives of equivalent parenthesis forms representing the circuit.

Unfortunately, this algorithm obviously will be more complex compared to the traditional gate-level simulation based on multi-valued algebras. However, when using alternative graphs it will be possible to create an efficient algorithm to implement the idea of calculating Boolean derivatives.

4. BINARY DECISION DIAGRAMS AND EQUIVALENT PARENTHESIS FORMS As a general case of decision diagrams alternative graphs (AG) [4] were proposed for representing digital systems. Binary decision diagrams (BDD) [5] can be regarded as a special class of AGs. Unlike the traditional BDDs, structural alternative graphs (SAG) reported in [4] are able to support structural representation of gate-level networks in terms of signal paths.

An AG that represents a Boolean function is a directed noncyclic graph with a single root node, where all nonterminal nodes are labelled by (inverted or non-inverted) Boolean variables (arguments of the function) and always have exactly two successor-nodes whereas terminal nodes are labelled by constants 0 or 1. For all nonterminal nodes, an one-to-one correspondence exists between values of the node variable and successors of the node. This correspondence is determined by the Boolean function represented by the graph.

Denote the variable which labels the node m by x(m). We say that a value of the node variable activates the node output branch. According to the value of x(m), one of two output branches of m will be activated. A path in an AG is called activated if all the branches that form this path are activated. The AG is called activated to the value 0 (or 1) if there exists an activated path that includes both the root node and the terminal node labelled by the constant 0 (or 1). Alternative graph G y with nodes labelled by variables x1, x2, ..., x n, represents the Boolean function y = f(X) = f(x1, x2, ..., x n), if for each pattern of X, the AG will be activated to the value which is equal to y. We can consider a digital circuit as a network of tree-like subcircuits, each of them represented by a Boolean function. Consequently, a digital circuit can be represented by a system of AGs. For the gate-level AG-description, the number of AGs is equal to the number of gates in the circuit.

Fig.2. Combinational circuit and his structural alternative graph

Similar to superposition of functions described in the previous section, superposition of AGs can be defined [4]: if the label x(m) of a node m in an AG G is a Boolean function which is represented by another AG G x(m) then the node m in G can be substituted by G x(m). Generation of an AG-model for a given gate-level digital circuit is based on the superposition of AGs. AGs for logical gates are assumed to be given as a source library. Starting from the gate-level AG-description and using iteratively the superposition procedure, we produce a more concise representation of the circuit (by each substitution of a node with an AG, we reduce the model by one node and by one AG). As a result of the superposition procedure, we create so-called structural AGs, which have the following property [4]: each node in a structural AG represents a related signal path in the corresponding gate-level circuit. To avoid repetitive occurrence of same subgraphs in the model, it is recommended to create separate AGs

for tree-like subcircuits. In this case, the number of all nodes in the set of AGs will be equal to the number of paths in all tree-like subnetworks of the circuit. Hence, using the concept of AGs, it is possible to ascend from the gate-level descriptions of digital devices to higher level structural descriptions without loosing accuracy of representing gate-level signal paths.

As an example, Fig.2. shows a representation of a combinational circuit represented by equivalent parenthesis form

y = (x1 x21 + ?x22 x31) (x32 x51 + ?x4 x61) + x52?x62

also by the corresponding structural alternative graph. For simplicity, values of variables on branches are omitted (by convention, the right-hand branch corresponds to 1 and the lower-hand branch to 0). Also, terminal nodes with constants 0 and 1 are omitted (leaving the AG to the right corresponds to y = 1, and down - to y = 0). The graph contains 10 nodes whereas each of them represents a signal path in a circuit and a literal in the EPF. The literals in EPF and the related node variables in AG correspond to input branches of the circuit shown in Fig.2.

5. MULTI-VALUED SIMULATION WITH ALTERNATIVE GRAPHS

Two-valued test pattern simulation on AGs is equivalent to path tracing procedure on graphs according to the values of variables at a given test pattern. As a result of path tracing in G y, the value of y will be calculated which will be equal to the value of the label variable at the terminal node reached by path tracing. For explaining the calculation of Boolean derivatives, introduce the following notations: l(m) - activated path in the AG from the root node up to a node m; l(m,#1) (or l(m,#0)) - activated path from a node m up to the terminal node labelled by constant #1 (or #0); m1 (or m0) - successor of the node m for the value x(m)=1 (or x(m)=0). Denote l(m)=1 (or l(m,#e)=1) if there exists a path l(m) (or l(m,#e)), where e ∈{0,1}; in other case, l(m)=0 (or l(m,#e)=0).

In the case of AGs, dy/dx(m)=1 is equivalent to one of the two conditions:

∧ l(m1,#1) ∧ l(m0,#0) = 1, (1) l(m)

∧ l(m1,#0) ∧ l(m0,#1) = 1, (2)

l(m)

in other words, dy/dx(m)=1 is equivalent to the existence of simultaneously activated three paths: l(m), l(m1,#1) (or l(m1,#0)) and l(m0,#0) (or l(m0,#1)).

For example, for the input pattern X = 110011 for Fig.2, we have for the SAG: dy/?dx4=1, since the following three paths are activated: l(?x4)=(x1, x21, x32, ?x4), l(x51,#1)=(x51,#1), l(x52,#0)=(x52,?x62, #0) and the condition (1) is fulfilled.

For calculating the maximum of a Boolean derivative and proving that max{dy/dx(m)} = 1, all dynamic values when tracing the path l(m1,#1) should be replaced by 1 and when tracing the path l(m1,#1) by 0; when tracing the path l(m) all dynamic values should be replaced either by 1 or by 0 properly so that the node m can be reached. In fact, instead of sequentially calculating the maximum derivatives separately step by step for all the nodes m where x(m)∈X D, we can travers all the paths from all these nodes in both directions by a a single procedure based on backtracking (by nested calculation of all the derivatives).

Examples of the procedure are demonstrated in Fig.3. In Fig.3a, we have dy/dx32 = dy/dx31 = 0, hence y = 0, because the traversing in all directions ends in the terminal node #0. In Fig.3b, we have dy/dx32 = dy/dx31 = 1, hence y = x32 x32 = εε = ε. In Fig.3c, we have dy/dx32 = dy/dx31 = 0, hence y = 1, because the traversing in all directions ends in the terminal node #1.

Fig.3. Multi-valued simulation by tracing the alternative graph

6. MULTI-VALUED SIMULATION ALGORITHM

In the five-valued alphabet, 0 and 1 are referred to as static values while ε, h and x are called dynamic values. Respectively, nodes labelled by variables containing static values are referred to as static nodes and nodes labelled by variables containing dynamic values are referred to as dynamic nodes.

In the following, few definitions used in describing the multi-valued simulation algorithm on alternative graphs (AGs) are given.

Definition 1. The value of the node m i

m i = x(m i )?β(m i ) ∨ ?x(m i )β(m i ) ,

where x(m i ) is the value of the variable labelling node m i , and β(m i ) is a constant which can be equal to either 0 or 1. Constant β(m i ) can be interpreted as an inversion flag for the node m i .

As it was mentioned in section 5, m 0 denotes the successor node of the node m which will be chosen when m=0. Accordingly, m 1 will denote the successor node that will be chosen when m=1.

Definition 2. Let us denote the operation of selecting the successor node to a node m while moving rightwards by m → and the operation of selecting the successor node while moving downwards by m ↓, respectively. In order to calculate the operations, the following rules are applied:

a) b) c) ???≠=→=0,0,1

0m m m m m ???≠=↓=1

,1,0

1m m m m m (1) (2)

An iterative process, which starts from node v, selects the successor node corresponding to rule (1) to be the new starting node and repeats until the graph has been exited is called moving rightwards from node m . In similar way we can define the process of downward movement from node m .

According to above definitions, a multi-valued simulation algorithm for AGs is presented. It includes two stacks, A and B for saving dynamic nodes while traversing the graph, and flags flag1 and flag2 for each node to keep track of which nodes have been traversed and to what direction. Initially all the flags are reset and all the stacks are empty.

The algorithm starts with the rightward movement from the root node. During the process, each traversed dynamic node will be pushed to stack A and the flag flag1of these nodes will be set. (The flag shows that the node was traversed while moving rightwards). If the value of the last traversed node was zero then the simulation will end and the value of the graph will be zero. Otherwise, a process of traversing the graph and calculating Boolean derivations for the dynamic nodes using the two stacks (A and B ) starts.

The process will end when both of the stacks are empty or Boolean derivation for a node containing value x is one. Nodes are popped from stack A for the subsequent downward movement. However, the dynamic nodes traversed during the downward movement are pushed to stack B . During the rightward movement, nodes are popped from stack B and pushed to stack A, respectively. The process of handling the node stacks is shown in Figure 4.

Fig. 4 Managing the Node Stacks

Let us consider in detail the process of handling stack A. (It is similar to the management of stack B with the exception that the moving direction and flag1 and flag2 are changed to their respective counterparts). When we pop a dynamic node from stack A , we will have to save the value of the stack pointer of stack B . This is necessary in order to restore the value of the pointer when the Boolean derivation of the popped node appears to be 0. Subsequently, the process of downward movement begins. If we reach a dynamic node that was previously traversed while moving rightwards (marked by flag1) then the Boolean derivation of the popped node will be equal to zero. If we reach a dynamic node that has not been traversed we will push it to stack B . Finally, if the graph is exited to the rightward direction, the Boolean derivation of the popped node is considered to be zero. Accordingly, if the graph is exited downwards then the corresponding derivation will be equal to one.

If the Boolean derivation of the node is zero, then we will pop the next node from stack A , otherwise we will continue with handling stack B . As mentioned above, the simulation process will end when both of the stacks are empty or Boolean derivation for a node containing value x is found to be one. The value of the graph is x also in the case when there exists at least one node equal to ε and one node equal to h whose Boolean derivations are ones. If there exist at least one node equal to ε and no nodes equal to h whose Boolean derivations are one then the value of the graph will be ε. In similar way, if we find Boolean derivation to be one for at least one node equal to h but not for any node containing ε then the value of the graph will be h. Finally, if Boolean derivations for all the nodes are found to be zeros then the value of the graph will be equal to one.

6. EXPERIMENTAL RESULTS

Dynamic test analysis has the goal to estimate the quality of test patterns by considering not only static levels of signals but also transitions between patterns in test sequences. The dynamic analysis package of the Turbo-Tester (TT) software [6] developed at the Tallinn Technical University is based on a multi-valued simulation on AGs. TT contains tools for multi-valued simulation, delay fault coverage analysis and dynamic fault analysis (especially oriented for detecting statically redundant faults). Experimental results on the multi-valued simulation of well-known ISCAS’85 benchmark circuits are given in Table 2. Time ratio 1 shows the efficiency of macro-level simulation for the case when only a single signal transition at inputs is allowed, and Time ratio 2 corresponds to the case of multiple random transitions at inputs.

Note that in Turbo Tester for the first time a macro-level multi-valued simulation method is implemented. As a result the complexity of the model can be significally reduced compared with known methods which always need as a model a network of two-input logical gates. The fault ratio in Table 3 shows differences in model complexities. From Table 2 it follows that the speed of macro-level simulation based on the proposed method increases up to 2,36 times for given benchmark circuits compared to the gate-level simulation.

Table 2

880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 Benchmark circuit c432 c499 c

(G) 974 2194 1550 21942788 4150 55688638 9728 11590

faults

Gate-level

faults

(M) 616 1202 994 16181732 2626 32965424 7744 7104 Macro

(M/G) 1,58 1,83 1,56 1,361,61 1,58 1,691,59 1,26 1,63 ratio

Fault

1

(M/G) 2,07 3,04 2,07 1,712,62 2,18 3,292,54 1,50 2,19 ratio

Time

2

(M/G) 2,37 2,77 2,22 1,732,35 2,39 2,572,14 1,62 2,63 ratio

Time

We discovered that the efficiency of simulation is highly dependent on the number of levels and on the number of gates in tree-like subcircuits represented by graphs. Experimental results for 5 different subcircuits represented by one graph with numbers of levels from 3 to 7 (and with numbers of gates from 7 to 127) are represented in Fig.5 and Table 3. As an example, note that the tree-like subcircuit with maximum size in the ISCAS’85 benchmark circuit c7552 contains 64 gates. Simulation time in Fig.5 is given for 100000 random patterns in seconds on SUN SPARC 20 workstation.

Fig.5. Comparison of Gate-level and Macro-level simulation

Table 3

Levels Gates Macro Gate

3 70.57 1.3

4 1

5 1.3 2.8

5 31 1.3 4.7

6 63 1.49.1

7 127 1.717

7. CONCLUSIONS

A new efficient multi-valued simulation approach for combinational or scan-based circuits for delay fault analysis, hazard detection or dynamic test analysis is presented. Its basic idea is substituting the traditional gate-level waveform calculation by nested Boolean differential calculus on alternative graphs. Introducing of AGs allows to reduce the complexity of the model by replacing low-level two-input-gate networks with higher macro-level representations. In fact, the multi-valued calculus on gate-level networks is transformed to a path traversing procedure on alternative graphs. It is not needed to create for each new macro-block a separate dedicated multi-valued model. Instead, from the gate-level description automatically an AG-representation will be created, where a single general procedure for all types of macros will be used. Experimental benchmark results have substantiated the efficiency of the new approach compared to the traditional gate-level simulation approaches.

References

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of 16th Int. Symposium on Multiple Valued Logic. Blacksburg, 1986, pp. 273-280.

2. W. Mao, M.D. Ciletti. A variable observation method for testing delay faults. Proc. Of 27th

ACM/TEEE Design Automation Conference. 1990, pp. 728-731.

3. S. Si. Dynamic testing of redundant logic networks. IEEE Trans. on Computers, 1978, Vol. C-27,

No 9, pp. 828-832.

4. R. Ubar. Test Synthesis with Alternative Graphs. IEEE Design & Test of Computers. Spring 1996,

pp. 48-59.

5. S. Akers. Binary Decision Diagrams. IEEE Trans. Computers, Vol. 27, No. 6, July 1978, pp. 509-

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