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The NuMesh A modular, scalable communications substrate

The NuMesh A modular, scalable communications substrate
The NuMesh A modular, scalable communications substrate

The NuMesh:

A Modular,Scalable Communications Substrate

Steve Ward,

Karim Abdalla,Rajeev Dujari,Michael Fetterman,

Frank Honor′e,Ricardo Jenez,Philippe Laffont,Ken Mackenzie,Chris Metcalf, Milan Minsky,John Nguyen,John Pezaris,Gill Pratt,Russell Tessier

MIT Laboratory for Computer Science

Cambridge,MA02139

(617)253-6036

numesh@https://www.doczj.com/doc/6216033721.html,

Many standardized hardware communication interfaces offer run-time?exibility and con?gurability at the cost of ef?ciency.An alternate approach is the use of a highly-ef?cient,minimal commu-nication element,with as much communication decision-making as possible done at compile time.NuMesh is a packaging and inter-connect technology supporting high-bandwidth systolic communi-cations on a3D nearest-neighbor lattice;our goal is to combine Lego-like modularity with supercomputer performance.To date, the primary focus of the project has been the class of applications whose static communication patterns can be precompiled into inde-pendent and carefully choreographed?nite state machines running on each node.Several extensions of the NuMesh to more general communication paradigms have been implemented,and the issues involved are under active exploration.

This paper presents an overview of our approach,as well as an introduction to our current-generation prototype.We also discuss our software environment and simulation technology,and enumer-ate some of the applications and programming models we have developed to make full use of the capabilities of the NuMesh. Keywords:systolic array,multiprocessor,interconnect,network, recon?gurable architectures.

Over the past two decades,the backplane bus has dominated com-puter architectures as the mechanism for intermodule communi-cations.The reasons for this dominance are simple and remain compelling:a well-designed bus provides a simple,extensible communications substrate that allows modules performing a va-riety of computational tasks to be assembled into coherent systems. It induces a Tinkertoy modularity at the system con?guration level, allowing system designers to construct systems without redesign-ing every component.However,despite the wide acceptance of buses,their technical limitations are well known and restrict their applicability in high-performance systems.Since they serialize all system-level communications,buses constitute a non-scalable com-munication bottleneck.Moreover,the achievable bus bandwidth is constrained both by the electrical length of the bus and by arbitration and other overheads.

The approach to this problem that we are exploring is a com-munications substrate that affords both modularity and high-per-formance communication.Our approach involves standardizing the mechanical,electrical,and logical interconnect among modules that are arranged in a three-dimensional mesh whose lowest-level communications follow largely precompiled systolic patterns.The attractiveness of this scheme derives from the separation of commu-nication and processing components,and the standardization of the interface between them.By making the communications hardware as streamlined and minimal as possible,and requiring the com-piler to do almost all the work for routing data within the mesh, we can maintain high-bandwidth,low-latency communications be-tween the processing nodes distributed throughout the NuMesh.

Dependence on compile-time decisions regarding routing,dead-lock avoidance,and resource allocation distinguishes the NuMesh communication substrate from more general dynamic networks such as those of Seitz[8,25]or Dally[7].One potential advantage of precompiled communication patterns is hardware simplicity,as-suming run-time routing decisions can be eliminated altogether or handled infrequently with little dedicated hardware.More signif-icant,however,is the amenability of such patterns to very high bandwidths because of their predictability.Every decision based on run-time data(such as port availability or message destination) constrains the minimum time of a?it through a network node. Elimination of such dependencies enables control circuitry to be

pipelined to arbitrary depth,allowing the data paths of the network to be switched at their maximal speed.Further,run-time collisions can be avoided by precompiling message schedules,allowing a higher level of communications traf?c before saturation,as shown by Shukla and Agrawal[26].

Our goal is to develop hardware modules and supporting soft-ware that allow high-performance,special-purpose multiprocessors to be con?gured for particular applications by simply plugging together the appropriate NuMesh-based modules.Such modules replace the individually tuned communication paths of contempo-rary supercomputers by a regular mesh of replicated near-neighbor links whose mechanical and electrical characteristics are rigidly constrained and highly optimized.These constraints allow per-formance parameters for non-local communications that compete favorably with those of a specialized interconnect.

The interdependence of communication and computation func-tions in most modern parallel architectures both limits the evolu-tion of each technology and discourages communication coherence within heterogeneousnetworks.We view the coupling of communi-cation substrates with processor hardware to be roughly analogous to the processor-speci?c backplane buses that proliferated prior to the late1970s,when the conceptual unbundling of communication from processing resources was evidenced by the emergence and ac-ceptance of processor-independent buses.The NuMesh is a step in a similar revolution,providing a generic communication interface physically and logically separate from the processing elements it connects.Independent manufacturers could,for example,package and bond chips directly into an industry-standard preconstructed NuMesh package.

In the following sections we present our work:Section2gives our idealized system model,and our current prototype is explained in Section3.The NuMesh software tools are discussed in Sec-tion4,and applications and programming models are discussed in Section5.Finally,Section6provides an overview of some related work.

The major thrust of the NuMesh project is to de?ne a highly-ef?cient,generalized communication and interconnect substrate for modules of arbitrarily complex digital systems.Abstractly, a NuMesh consists of modules,or nodes,that may be connected to-gether to populate a three-dimensional mesh.For example,Figure1 shows a simpli?ed view of a small mesh of our current prototype nodes.This?gure depicts each module as a unit whose peripheral connectors provide signal and power contacts to four immediate neighbors.

Each node in the mesh constitutes a digital subsystem that com-municates directly with each of its neighbors through dedicated signal lines.During each period of the globally-synchronousclock, one datum may be transferred between each pair of adjacent mod-ules.Currently,our prototype runs at just over1.2Gbits/second per port;next-generation modules will be clockedfaster,and we believe that our minimal hardware design will make it possible to achieve extremely high clock rates in future revisions of the hardware.

Although the NuMesh model features a rigid partition of

3-

Figure1:Simpli?ed View of a Small NuMesh

space into?xed-sized cells,it accommodates a number of varia-tions within this discipline.A given mesh may be partially popu-lated;one and two-dimensional con?gurations are speci?cally an-ticipated.Many node types may be deployed within a system, including nodes whose principal function is to provide power and cooling conduits while maintaining communication and structural integrity.Nodesmay also occupyseveral adjacentcells;while inter-nal communications within such nodes may follow formats foreign to NuMesh standards,NuMesh conventions are expected at their external boundaries.

An idealized NuMesh module is a roughly rectangular solid with edge dimension on the order of two inches.A node is logically partitioned into two parts:a local processor that implements the node’s particular functionality,and a communications?nite state machine(CFSM),replicated in each node,that controls low-level communications and interface functions.A node’s local processor may consist of a CPU,I/O interface,memory system,or any of the other subsystems out of which traditionally-architected systems are constructed.A node’s CFSM consists of a?nite state machine, data paths for inter-node communication,and an internal interface to the local processor.A typical module is depicted schematically in Figure

2.

The core of the CFSM control path is a programmable?nite state machine.The transition table,held in RAM,is programmed to control all aspects of routing data to other nodes and interfacing with the local processor.A small amount of additional hardware reduces the required number of states by providing special-purpose functionality such as looping counters.

The CFSM data path consists of a number of ports connected through a switching network allowing data from one port to be routed to another.Most of the ports are for communication to other CFSMs;however,one port supports CFSM-local processor transfers and allows the CFSM to move data between the processor and the mesh.This port may be wider than the network ports,and provide out-of-band signals in addition to the ordinary data path. Optimally,any combination of ports may be read or written on each clock cycle,but this?exibility may be constrained in a given implementation.

Each CFSM also contains an oscillator to generate the node’s clock(the local processor has the option of an independent clock), and circuitry to control the phase of the oscillator.The clocks can be kept globally synchronized by any of a number of methods (see Section3.1).The clock cycle time is constrained by the time necessary to transfer a data word between adjacent nodes,which can be made quite short because of the prescribed limited distances between nodes,the point-to-point nature of the links,and the use of synchronous communications.

The transition table of the CFSM is typically programmed to read inputs from various neighbors or the local processor into port regis-ters and send outputs from various port registers to other neighbors or the local processor on each clock cycle.It may be thought of as a programmable pipelined switch.We consider a range of pro-gramming styles that support different communication models in Section5.

The CFSMs in a mesh,operating synchronously at the fre-quency of the communication clock,follow a compiler-generated preprogrammed,systolic communication pattern.Eventually,we plan on extending our compiler technology to suggest selection, function,and mesh positions of the modules themselves.The ag-gregate CFSM circuitry constitutes a distributed switching network that is customized for each application;its programmability allows this customization to be highly optimized.

In applications amenable to rigidly systolic communication pat-terns,each CFSM follows a periodic sequence of transactions with its immediate neighbors.For example,for module to transfer a word to its neighbor on cycle of each period,’s CFSM is programmed to drive its lines to on that cycle,while is pro-grammed to load data from.By appropriate design of transition tables,arbitrary systolic communication patterns may be imple-mented.In some cases,words loaded by a module are destined to be read by that node’s local processor.In other situations,they are routed(typically on the next cycle)to a neighboring node without local processor

involvement.

Figure3:Communications Snapshot

Figure3shows a snapshot of communications within a two-dimensional NuMesh at a typical clock cycle.Heavy arrows depict local communications that complete during the current cycle;gray lines represent nonlocal transfers,formed by a sequence of local communication steps,that complete after some number of cycles. Although this pattern is static in the sense that it is compile-time determined,it is dynamic in that entirely different communication patterns may be used in each clock cycle,limited only by the amount of state memory available to each CFSM.

Certain algorithms may bene?t from?ow control,data-depen-dent CFSM execution,and other synchronization measures in their underlying communications.These may be superimposed on the data-independent primitives by software convention,allowing cer-tain data words to contain control information.Additionally,full–empty status bits may be provided in each direction at each port (as is done in our current prototype);this allows a limited range of communication dynamics by indicating whether a word is avail-able to be read or written during that cycle.The possible range of programming models can be seen as a continuum from fully static to fully dynamic;?ow-control information allows us to use a more general regular-expression model to control the CFSM state.

It is widely believed that ef?cient support for general models of computation(as opposed to the restricted class of systolic algo-rithms)requires the ability to route traf?c dynamically.While we view the extent of this requirement to be an open research question,1 we accept the value of some provision for dynamic routing if the NuMesh is to support general computation.However,we approach this need with a high-level bias toward replacing hardware func-tionality with compile-time analysis whenever possible.

Rather than a fully general dynamic routing mechanism capa-ble of directing each communication to an arbitrary destination,we

optimize for a communication mix in which destinations are largely compile-time predictable and whose unpredictable aspects(requir-

ing run-time routing decisions)have low branching factors or occur infrequently.Our goal for the NuMesh communication architec-ture is to augment the static communication substrate with simple data-dependent branching that allows certain routing decisions to be based on run-time data.This will allow us to optimize applica-tions with limited dynamic communications for the common case of packets whose path can be predicted at compile-time,using extra mechanism for dynamic routing only when necessary.A CFSM can be programmed,for example,to expect the header word for a dynamically-routed message to appear at its North port during clock number;its value dictates the output port for the message, the body of which appears on subsequent clocks.

Interesting approaches to the support of such limited commu-nication dynamics(1)compromise neither the simplicity nor the ef?ciency of static communications,(2)assume the number of bits of run-time decision per node to be small,and(3)avoid taking a po-sition on issues that constitute controversial policy.Our approach is to resolve the majority of communication decisions—such as routing,arbitration,and deadlock avoidance—at compile time,and provide minimal run-time hooks to support those few cases that remain.Dynamic routing support will be provided off the critical path and only accessed explicitly by the CFSM,so that there is no slowdown for the static routing case.

Integrating dynamic routing and static routing is a dif?cult issue that is being studied actively by the group.A na¨?ve way to combine the two is to allocate dynamic routing phases that are a?xed number of cycles in length,for which we can guarantee that packets injected at the beginning of the phase will reach their destination by the end. Such phases can then be intermixed as necessary with static rout-ing.One way to implement such general dynamic communications is to have the local processor parse a header word associated with a message,returning to the CFSM the desired output port for the message(and optionally a new header word).The returned values would then be cached within the CFSM itself,allowing future mes-sages with the same header to be routed without the intervention of the local processor.This would allow arbitrarily powerful dynamic routing models,particularly since the header words need only be recognizable by CFSMs along its path,not by every CFSM in the mesh.

Mixing static and dynamic routing in the same cycle is a harder problem.A simple initial solution is for the compiler to pre-allocate static timeslots per-link in which dynamic routing can occur.This has the obvious disadvantage of wasted bandwidth on slots that are idle on a given cycle,but more sophisticated compiler technology may be able to reclaim that bandwidth,at least partially.One simple method of producing such data-dependent routing is to pass a CFSM state pointer in the data stream,which the CFSM will be programmed to expect,and which it will use to vector to a new state that handles routing the following message.Thus a message destined for one of two possible destinations might be routed purely statically up to the node where the paths to the destinations diverge; that node would then examine the header word to determine which way to send the message.Although a six-neighbor Cartesian mesh is intuitively appealing, other topologies may provide equivalent performance at lower cost. In the interest of post-manufacture scalability we restrict our atten-tion to regular communication meshes whose per-node hardware requirements(i.e.,number of ports)are constant.One particularly interesting topology is the four-neighbor diamond lattice.Figure1 showed a partially populated three-dimensional mesh whose con-nectivity is isomorphic to the structure of the diamond lattice.

The diamond interconnect has a number of useful properties, including low switch complexity,good latency and throughput per-formance,isotropy,and excellent mechanical and thermal proper-ties.The number of links crossing the bisection of the diamond is less than for the equivalent Cartesian mesh;however,if we assume that nodes are pin-limited,the bisection bandwidth of the diamond is as good or better than the Cartesian mesh as a result of the50% wider links made possible by the reduced number of ports.Further details on the diamond interconnect will be available shortly[24]. Early NuMesh prototypes with conservative performance param-eters have been constructed using off-the-shelf TTL and CMOS chips.They plug together in a two-dimensional four-neighbor Cartesian mesh using standard96-pin DIN connectors,or,with different placement of the connectors,in a three-dimensional four-neighbor diamond lattice.The nodes feature either40MHz SPARC processing elements or40MHz DSPs(Texas Instruments TMS320-C30).These prototypes are designed as an early exploration of the NuMesh communication scheme and as a development platform for prototype software.Their internal architecture compromises the goals described earlier(see Section2.1.1)in a variety of ways; many of these compromises are lifted in next-generation prototypes currently under development.

East Port

North Port

West Port

South Port

Processor

Figure4:Prototype CFSM data paths

Data paths for the prototype CFSMs consist of bidirectional reg-istered transceivers that serve to isolate local buses of adjacent nodes[20].The CFSM at each node contains North-South and East-West bus segments as shown in Figure4,the two segments being linked by an interbus transceiver(called the X transceiver). Each node has a transceiver at the North and East ends of its respec-tive bus segments;the opposite end of each segment connects to a similar transceiver of an adjacent node.Transitions between CFSM states are labeled with control bits that specify the actions taken by the components that make up the CFSM.The current state pointer (effectively the instruction pointer)may itself be loaded from a dedi-cated register on the East-West bus;additionally,the node can drive its state,augmented with its node ID and with a user-speci?able constant value,onto the North-South bus.The connection between data paths and CFSM state provides means for limited dynamic routing,as discussed in Section2.3.

The CFSM data paths aggregate as shown in Figure5,which depicts a5-by-3con?guration.The asymmetric placement of transceivers with respect to node boundaries allows data paths of adjacent CFSMs to be separated by a single registered transceiver and hence a single clock delay.2Data propagates along either or-thogonal axis at a maximum rate of one node per CFSM clock cycle.

A change in direction,e.g.routing a datum from the North port of a node to its East port,suffers an additional1-clock latency due to the delay through the X transceiver.

Communication between a prototype CFSM and its local pro-cessor is through a pair of asynchronous FIFOs arranged so that CFSM-to-local processor data is sent from the North-South bus, and local processor-to-CFSM data is received onto the East-West bus.The attraction of FIFOs stems primarily from their inherent synchronization barrier,which allows the CFSMs and their node-speci?c logic to be clocked at independent frequencies.The current prototypes use processors clocked at40MHz and CFSMs clocked at38MHz.The FIFOs also make possible some simpli?cations in the compiler,since,for example,data does not have to be consumed on the exact cycle it is produced.

A scalable clock-synchronization technique,using only local communication between nodes,is used in the current prototypes. This synchronization technique has been proven to work for net-work connected as two-dimensional grids;extensive simulation has veri?ed this result and suggests its effectiveness for grids of higher dimensions.For more information,see[23].

A prototype NuMesh can connect either to a SPARCstation,via an SBus card connected to a prototype node’s FIFO,or to a Mac-intosh,via a DMA NuBus card connected to a node’s NuMesh port.The two interfaces support bidirectional transfers at back-plane bus speeds—considerably slower than NuMesh communi-cation bandwidths—and allow diagnosis,program loading,and application-dependent communication between the NuMesh and host.

Figure5:Aggregate prototype data paths,with one node highlighted.

gramming models that can be speci?ed as real-time tasks;candi-dates include LaRCS[19],Gabriel[5,17],and CONSORT[27]. For many static NuMesh applications,block diagrams,which are essentially hierarchical communication graphs,are an appropriate model;by augmenting diagrams with latency constraints the com-piler can be made aware of hard real-time performance criteria that must be met by the resulting NuMesh implementation.

Our general-purpose FSM-based routing simulator uses a simple register-transfer language to describe the routing actions taken in each state,and either a simple generic assembly code or compiled C code to describe the local processor programming.If compiled C code is used,it is linked with the simulator binary;this allows much faster execution for compute-bound simulations,but requires some user effort to specify delays explicitly in the time-critical sections of the code so the simulator can produce realistic results.We are currently working on adding a cycle-by-cycle SPARC simulator to the existing CFSM simulator so as to be able to generate precise simulations for our SPARC nodes.

The simulator environment allows us to experiment with differ-ent topologies,ranging from the basic Cartesian2D and3D meshes, to the diamond lattice con?gurations described in Section2.4,to other experimental https://www.doczj.com/doc/6216033721.html,ing the simulator also allows ex-perimentation with different CFSM architectures:for example,we can compare the code generated under the assumption that a full permutation of input data to output ports can be performed every cycle,as opposed to the current hardware where two internal buses drive the output ports.It can also be convenient to simulate much larger networks than we can currently build:for example,a multi-grid[21]computation was tested on the simulator for sizes of over 16,000nodes with2,000states in each CFSM;the processing code was written both in C and in generic assembler,and the CFSM code was generated by a dedicated“multigrid routing compiler.”

The simulator has also proven useful when writing complex parallel code.When running native C code,the user’s program, linked with the simulator,can be run under dbx or any other native debugger.The user can alternate between setting breakpoints or performing other C-language debugging actions and checking node states or watching data movement at the simulator’s interactive debugging prompt.Furthermore,extensive task trace information is available from the simulator.For example,we can derive a parallelism pro?le showing when processors are active and when they are blocked waiting for I/O;Figure7shows one run of the multigrid code.As can be seen,the amount of parallel execution drops signi?cantly during the coarser relaxation steps when fewer tasks are available to the nodes.

The simulator has been carefully written to maximize its speed; on a SPARCstation2,for example,the multigrid application runs at about53kHz per simulated processor(in units of routing cy-cles).The simulator itself has also been parallelized for two sep-arate environments.On an eight-processor Encore Multimax the same multigrid application runs at around73kHz per simulated processor.Additionally,System V compatible multiprocessors can take advantage of an implementation using semaphores and shared memory.

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Figure 7:Multigrid parallelism pro?le

In order to develop insights into the static communication methodol-ogy,we have implemented applications using several programming models.These range from a rigid C-language interface for programs with purely static communication patterns to task-schedulingmech-anisms that accommodateapplications with more dynamic features.We present several different points along this spectrum.

The most primitive programming model relies on a purely static,systolic communication scheme that uses no control-?ow infor-mation.The complex scheduling issues that arise from such an approach demand either very dedicated programmers or a complete scheduling compiler such as that sketched by Lam [16].One of our example programs uses a purely static communication scheme in implementing the multigrid algorithm for solving partial differential equations.

In the static multigrid implementation,the communication over-head is relatively low since,when possible,data is routed from source processors to their destinations before it is requested.Addi-tionally,static NuMesh routing is very fast:to cross an 8-by-8grid made up of our relatively slow prototype nodes takes less than 0.5s from source processorwrite to destination processorread.For all data to be routed purely statically,the code execution time must be derived by examining loop timings,and the FIFO transit time must be known precisely as well.The CFSMs can then route data exactly when it is predicted to be ready from the local processors—no time is spent waiting for ?ow-control information.

The next most dynamic model relaxes the purely static approach to allow utilization of ?ow-control information.In our current pro-totype,this model imposes a factor of two slowdown over fully static routing,since the full/empty bits are only available on the cycle following data being produced or consumed.A constrained C-language compilation environment has been developed to sup-port a static message-passing communication paradigm.The pro-grams written in this environment exhibit a cyclic control pattern and statically-determinable communication patterns.A scheduler generates the appropriate CFSM code from a pro?le of these pat-terns while local processor machine code is produced by a vendor-supplied C compiler.From the programmer’s viewpoint,nodes run individual C programs interconnected by static streams.As a result,this scheme provides for very natural code organization and transla-tion for certain applications.Early experiments include audio ?lters implemented as periodic computation modules interconnected to perform various transformations such as spectrogram display,pitch scaling,and auditory model computation,all of which are capable of using sampled audio data as inputs in addition to real-time data streams.

A similar approach is used to implement real-time video ?l-ters.These represent a set of applications with suf?ciently high bandwidth requirements that they cannot be supported with most contemporary general-purpose architectures and thus illustrate the advantage of a low-overhead static communication scheme.Even with real-time video constraints dictating a sustained communica-tion bandwidth of over 8MWord/sec,a prototype 10-node/8-DSP con?guration manages this data rate while executing such ?lters as vertical stripe permutation,posterization and edge-detection.Real-time speech recognition is the goal of another large-scale NuMesh application,developed in concert with the MIT Labo-ratory for Computer Science’s Spoken Language Systems (SLS)group [28].We have implemented a pipelined NuMesh version of the Viterbi search used to perform lexical access [9].The parallel decomposition of the Viterbi algorithm for the NuMesh partitions and distributes the lexical network to the processors,each of which is then able to perform Viterbi searching for its own part of the lex-ical https://www.doczj.com/doc/6216033721.html,munication between the processors occurs in the logical pattern of a binary tree,with data being ef?ciently merged and broadcast by the NuMesh.

Our implementation achieves a near-linear speedup on the num-ber of prototype nodes that have currently been built.For large dictionaries,nodes with convenient access to large memories are preferred,such as our SPARC nodes with 8MB of cached dynamic memory.However,the other phases of the speech recognition system (spectral analysis,acoustic segmentation and phonetic clas-si?cation)are best performed on DSPs.The ability to support such heterogeneity is a natural consequence of the de?nition of the NuMesh as purely a network substrate with a well-de?ned interface to the processing elements.

For vocabularies in the hundreds of words,a NuMesh network of less than a dozen nodes has currently achieved real-time lexical access for the speech recognition system.The SLS group typically runs their system on a SPARCstation 4/490with an attached DSP card;a con?guration which does not provide full real-time speech

recognition.We are in the process of evaluating the performance of an implementation of the entire SLS system from microphone

to recognized phrases for the NuMesh,using appropriate processor types to implement the different phases of the speech recognition model.

Branch-and-bound techniques to solve search problems such as traveling salesman(TSP)are also prime candidates for?ow-controlled static routing.In our implementation,we split a given TSP into an enumerable set of subproblems that can be indepen-dently solved.The strategy is to distribute these subproblems as tasks to the individual processorsin a NuMesh,collecting and merg-ing results until a de?nitive answer is computed.Primary commu-nication requirements are subtask allocation among processors and distribution of the current best bound.

One approach forms a Hamiltonian path of active processors through which a monotonic current subtask number and best bound are continually forwarded via?ow-controlled static routing.By embedding the dynamic communication paths in static streams of relatively high capacity,we are able to achieve good scaling perfor-mance over the modest-sized NuMesh con?gurations that have been constructed.A single-processor SPARCstation2implementation takes just over145seconds to run a given14-city tour;the same tour on a single NuMesh TMS320C30node runs in157seconds, and scales virtually linearly to about14.5seconds on the12-node mesh.Although this approach does ef?ciently provide a correct solution,its reliance on a precomputed message route implies that if any processor or CFSM fails,the computation is unable to com-plete.Furthermore,discovering the best Hamiltonian path among the active processors requires solving a TSP to begin with—a com-putationally intensive precompilation step.

An alternative model uses a task allocation mechanism that avoids these?aws by reallocation of subtasks between adjacent nodes based on relative sizes of task queues at each node.In an initial con?guration,the entire collection of subtasks is assigned to one densely loaded node.As the computation progresses subtasks dif-fuse towards less dense nodes and the system tends to a steady state in which subtasksare evenly distributed among all processors.Each processor periodically sends a?xed number of messages,one to each of its physical neighbors.By controlling the contents of these messages,the processor can send individual messages to particular neighbors.This diffusion scheduling[11]approach eliminates the need for any precomputed communication paths.

Tolerance to processor,router,and link failures is achieved via redundancy of subtask allocation.Each node keeps a record of all subtasks it has diffused away,although at a lower priority than non-diffused subtasks.In the case of perfect hardware operation,no redundant computation is performed.When nodes do fail,the lower priority subtasks are eventually executed and the correct answer is reached,albeit with an increase in total running time.In fact,we have demonstrated on our prototype that removing a node from the mesh during execution does not affect the computation beyond an incremental slowdown.The most?exible routing method is the dynamic routing technique discussed in Section2.3.The static multigrid simulation mentioned in Section5.1was re-implemented using dynamic routing with CFSM caching to provide a simple comparison.The simulated FSM code is reduced to one state(ROUTE and loop),and the processor is given the responsibility of forming explicit packets with a header word and(in this case)one data word.For a9-by-9multigrid run the dynamic routing simulation required two to four times as many cycles as the static version(depending on the assumed cache miss time),but required a maximum cache size of only17header words to hold all cached routes in the mesh.As the network size grows and cache requirements increase,the overhead will increase due to cache replacement.

Primitive exploration of such dynamic routing approachesusing current prototype hardware involves some combination of processor interaction and dynamic reprogramming of the CFSMs.This ap-proach was followed in the implementation of the diffusion schedul-ing described above.

The systems approach described here deliberately re?ects,and bor-rows heavily from,several trends increasingly evidenced in archi-tectural research as well as commercially available computers.

Many contemporary multiprocessors rely primarily upon run time decision-making for routing general communication traf?c[2, 7,8,10,25],whereas systolic architectures[14,15]and systems such as the Supercomputer Toolkit[1],use compile-time approaches to communication scheduling that offer potential cost/performance advantagesin applications where communication patterns are large-ly predictable and macroscopically static.The NuMesh shares the bias of these latter systems toward compile-time resolution of communication choreography,but uses a homogeneous substrate of communication support to provide a simpler physical model for spatially-aware compilers as well as the potential for post-manufacture scalability.

Generalized communications support has been integrated with processors in a variety of research and commercial projects,includ-ing iWarp[6],the Transputer[13],and the GDP[3];such provisions are beginning to appear in contemporary DSPs,such as the Texas Instruments TMS320C40.In the early1980’s,the Warp project[4] introduced the idea of a recon?gurable systolic communication framework that,like NuMesh,uses routing information obtained at compile-time to develop a communication pattern maximizing computational ef?ciency.Subsequently,iWarp[22],an enhanced version of Warp,provided improved compile-time capabilities and support for message-based communication using dynamic routing. It was found that although systolic communication was appropriate for many forms of scienti?c or business computing,some dynamic routing capabilities were needed to support general-purpose com-puting.

Current Transputersystems from Inmos[12]share NuMesh fea-tures such as run-time recon?gurability and high level programma-bility.The Transputer uses relatively slow asynchronous com-

munication links,and is targeted primarily at embedded control applications.

An extreme of recon?gurability in a processor mesh is reached by the novel Geometry-De?ning Processor(GDP)[3],whose pro-cessors communicate with neighbors using bit-serial optical links, also at modest speeds.The resulting?exibility supports an approach to the analysis of physical structures using processor con?gurations isomorphic to the emulated object.A typical GDP structure is used as an attached processor whose host provides a compilation,pre-and post-processing environment.

A major attraction of the NuMesh approach is its early promise of high performance in the restricted but important class of applications whose communication structures are amenable to compile-time analysis.Initial work in such domains as speech,image process-ing,?nite element analysis,and similar static,compute-intensive applications uses NuMesh for the prototyping of high-performance application-speci?c multiprocessor systems.

The NuMesh represents an abstraction for the speci?cation of digital systems that relies on reprogrammable,minimal hardware rather than on hard-coding current architectural theories in hard-ware.Thus,we can implement these theories in software,taking advantage of technological and architectural enhancements by pro-viding a highly recon?gurable base.

More ambitious goals of the project address generalized mod-els of computation,exploring the boundary between run-time and compile-time decision mechanism.Reconciliation of dynamic communication patterns with this approach involves exploration of new ground,and consequently higher technical risk.While we are optimistic that incremental compilation technologies com-bined with minimal hardware support for critical run-time routing decisions will yield attractive engineering alternatives to current practice,the most challenging of these goals must be viewed as addressing open research questions.

This paper presents an overview of and motivation for early work done by members of the Computer Architecture Group at MIT. Anant Agarwal,Bill Dally,and other members of the group have been important and continuing in?uences on the architecture and philosophy of the NuMesh;the name itself was suggested by Dally in deference to the NuBus,a relic of the group’s ancestry.

This work was supported in part by DARPA,Texas Instruments, and AT&T.

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新课标英语七年级上册单词表(含音标)

初一人教版英语上册单词表 Starter good[] adj. 好的;令人满意的 morning[] n 早晨;上午 good[] morning[] 早上好! evening[] n 晚上;黄昏 good[] evening[] 晚上好! How[] adv.怎样;怎么;如何 are[] v. 是 you pron.. 你;你们 How[] are[] you 你(身体)好吗? I[]. pron. 我 am[] v. 是 I'm =I[] am[] 我是 fine[] adj. 好的 thanks int. &n 谢谢 ok int. adv. & adj. 好;不错 name[] n 名字 list[] n 名单;列表 what pron. (疑问代词)什么;什么样的人(或事物) is[] v. 是 what's =what is[] this adj. pron.. 这;这个 in[] prep 表示表达方式,手段,,用,以 English[]. n 英语 an[] art. (元音前)一个(只,把…) it[] pron.. 它 it's= it[] is[] map[] n 地图 orange[] n 橘子 jacket[] n 茄克衫 key[] n 钥匙 quilt[] n 被子 pen[] n 钢笔 ruler n[] 直尺 P=parking abbr. 停车(区) NBA = abbr. (美国)全国篮球协会 kg=kilogram[] n 公斤;千克 spell v.拼写;拼字 please[]. v.请 color[] n 色;颜色 red[] adj. 红(色)的 yellow adj. 黄(色)的 green[] adj. 绿(色)的 blue[] adj. 蓝(色)的 black[] adj. 黑(色)的 white adj. 白(色)的 and[] conj. 和;又;而且 UFO abbr. 不明飞行物 CCTV.abbr. 中央电视台 UN=United Nations[] abbr. 联合国 the art. 定冠词 Unit 1 my[] pron.. 我的 name[] n 名字 is[] v. 是 name's=name[] is[] clock[] n 时钟 I[] pron.. 我 am[] v. 是 I'm=I[] am[] 我是 nice[] a.好的;令人愉快的 meet[] v. 遇见;相逢 you pron.. 你;你们 what pron.. & adj. 什么; what's=what is[] your pron.. 你的;你们的 hello[] int. 喂 hi[] int. 嗨 his[] pron.. 他的 and[] conj. 和; her[] pron.. 她的 question[] n 问题;难题;询问;疑问 answer[] n 回答 look[] v. 看;望;看起来 first[] adj. 第一的 first[] name[] 名字 last[] a.最后的;上一个的 last[] name[] 姓氏 boy[] n 男孩 girl[] n 女孩 zero num. . 零 one[] num. 一; two num. 二 three num. 三 four[] num. 四 five[] num. 五 six num. 六 seven num. 七 eight[] num. 八 nine[] num 九 telephone n , 电话 number[] n 数;数字 telephone number[] 电话号码 phone[] n 电话 phone[] number[] 电话号码 it[] pron.. 它 it's =It[] is[] card[] n 卡;卡片 ID[] card[] n 身份证 family[] n 家;家庭 family[] name[] 姓氏 Unit 2

aanthe的用法区别修订版

a a n t h e的用法区别 集团标准化小组:[VVOPPT-JOPP28-JPPTL98-LOPPNN]

三人行教育a,a n,t h e的用法区别(一)a, an的用法 1.a:用于辅音音素(不是辅音字母)开头的词前,表示单数的数量“一”。 a book a desk 2.an:用于元音音素(不是元音字母)开头的词前,表示单数的数量“一”。 an apple a big apple an old man 3.元音字母:以元音字母Aa, Ee, Ii, Oo开头的单词基本都是以元音音素开头 Uu较特殊 4.辅音字母:26个字母中,除了5个元音字母,其他是辅音字母 5.特殊情况:an umbrella(u发元音) a useful english book (u发辅音) an hour(h是辅音字母,但它不发音) 练习一:用a, an, the填空 1._____book 2._____apple 3._____orange 4._____uncle 5._____eraser 6._____ math book 7._____new book 8._____old book 9._____teacher 10.______English 11.____ hour 12._____good teacher 13.____idea 14.____good idea 15.____island 16.____ astronaut (二)the的用法 1.一般用于特指:The girl is my sister. 那个女孩是我的妹妹。

2.第二次出现:There is a book on the desk. The book is mine. 书桌上有一本书,那本书是我的。 3.世界上独一无二:the moon月亮 the earth地球the Great Wall长城the sun太阳 4.固定的词组:on the desk在书桌上 5.形容词最高级前:Jenny is the oldest girl in the class. 在 班里珍妮是年纪最大的女孩。 练习二:选择 ( )1.That’s _____ island. I like to go there. A.a B.an C.the ( )2.I have ___ new book. Jenny has ___ old book. A.a/ an B.an/ a C.an/ an ( )3.This is ___ orange. That’s ____big orange. A.a/ an B.an/ a C.an/ an ( )4.Yesterday I studied English for ____ hour. A.an B.the C.a ( )5.This is a bag. ____ bag is Tom’s. A.A B.An C.The ( )6.___ man is Lisa’s father. A.A B.The C.An ( )7.____ Great Wall is in China. A.A B.The C.An ( )8.My English book is in ___ desk. A.the B.an C./ ( )9.She has ___ idea. It’s a good idea. A.a B.an C.the 练习三:a, an, the填空

人教版新目标英语课文翻译七年级上全一册

预习单元1—3 Starter Unit 1 Section A 1a 早上好,海伦!嗨,鲍勃!早上好,艾丽斯!喂,弗兰克!喂,埃里克!早上好,戴尔! Section B 1 下午好,戴尔!嗨,辛蒂!你好吗?我很好,多谢。你好吗?我很好。 Self Check 1 嗨喂上午下午晚上好的好谢谢好的4 年龄手他床Just for Fun 晚上好! Starter Unit 2 Section A 1b 这用英语怎么说?一张地图。一个橙子。Section B 1a 用英语说这是什么?一把钥匙。请拼一下。Self Check 3夹克衫艾丽斯地图钥匙橙子戴尔海伦格雷斯辛蒂鲍勃钢笔弗兰克被子埃里克尺子 4 名字能他腿美好的牛奶去狗 Starter Unit 3 Section A 1a 这是什么?它是字母V。它是什么颜色的?它是红色的。这是什么?它是字母Z。它是黑白相间的。Section B 1b 这把钥匙是黄色的。这把尺子是蓝色的。这支钢笔是红色的。Self Check 它是绿色的。 字母意思(铅笔芯)硬黑激光唱片英国广播公司停车(美国)全国篮球协会千克小号/中号/大号不明飞行物中央电视台联合国 一单元 Section A 1a 我是吉娜。见到你真高兴。 Grammer Foucs你的名字是什么?我的名字是詹妮。我是詹妮。他的名字是什么?他的名字是托尼。她的名字是什么?她的名字是吉娜。 Section B 1c 你的电话号码是什么,李欣?是281-6926。3b 她的电话号码是什么?她的姓氏是什么?她的名字是什么? Self Check 1 我她是身份证什么我的喂你的他的她的名姓电话号码 Just for Fun你的名是什么?ZIG。你的姓是什么?ZAG。 二单元 Section A 1a 那是你的双肩背包吗?不,不是。它是他的双肩背包。这是你的铅笔吗?是的,它是。它是我的铅笔。这是你的尺子吗?不,不是。它是她的尺子。 铅笔钢笔书橡皮擦尺子铅笔盒书包卷笔刀词典 2b 请原谅,索尼亚。这是你的铅笔吗?是的,谢谢。那是我的橡皮。简,这是你的尺子吗?不,不是。它是她的尺子。好的,这是我的书。这是你的铅笔盒,简。Section B 1a 棒球手表电子游戏机身份证钥匙笔记本戒指钢笔 1b 这是什么?一块手表。你怎样拼写它?…… 3a 这是你的手表吗?给艾伦打电话495—3539。艾伦,失物招领箱中的电子游戏是你的吗?尼克招领:笔记本这是你的笔记本吗?请给玛丽打电话。电话#235—0285。寻物:我的学生证。我的名字是托尼。请打电话685—6034 3b 失物招领一串钥匙。请给大卫打电话529—6403 Self Check Just for Fun嘘!什么?用英语说这是什么?一块手表。你怎样拼写它?它(那个) 三单元 Section A 1a那是我的两个兄弟。并且那是我姐妹。母亲父亲父母兄弟祖母祖父朋友祖父母姐妹 1c 这是他的姐妹。这些是他的兄弟们。 2c 这是吉姆吗?,不,他不是。他是戴夫。 Grammer Foucs 这是你姐妹吗?不,不是的。这是我的朋友。这些是我的朋友们。那是你的兄弟吗?是的,他是。那个是我的兄弟。那些是我的兄弟们。 3a那是安娜,那是保罗。她是你的姐妹吗?是的,她是。他是你的兄弟吗?不,他不是。他是我的朋友。 4她是你阿姨吗?是的,她是。 Section B 2c 这些是我的父母。这是我的祖父。这是我的朋友,林方。亲爱的玛丽:谢谢你的全家福照片。这是我的全家福照片。你的朋友艾玛这是我的弟弟,托尼。这是我的妹妹,莫娜。这些是我的父母。 Self Check 1 这那这些那些妈妈爸爸父母姐妹兄弟(外)祖母朋友叔叔(舅舅)(外)祖父婶婶(舅妈)堂(表)兄弟(姐妹)(外)祖父她他 Just for Fun那是你的妹妹吗?不,不是。那是我表妹。那是你的妹妹吗?不,不是。那是我的姑姑。谁是你妹妹?这是我的妹妹。 四单元 Section A 1a桌子床梳妆台书柜沙发椅子双肩背包书钥匙棒球抽屉植物我的双肩背包在哪儿?在桌子下面。我的书在哪儿?在沙发上。我的棒球在哪儿?它在双肩背包里。1c 双肩背包在哪儿?在桌子下面。 2c 棒球在沙发上吗?不。不在。他在椅子下面。Grammar Focus棒球在哪儿?在双肩背包里。我的电子游戏机在哪儿?在床下。你的书在哪儿?他们在椅子上。他的钥匙在哪儿?在梳妆台上。她的钥匙在哪儿?在桌上。3a书包在哪儿?我不知道。它在梳妆台上吗?不,它不在。我的书在哪儿?我不知道。它们在床上吗?不,他们不在。 4 双肩背包在哪儿?它在桌子底下吗?不,它不在。它在桌子上。 Section B 1a 数学书闹钟激光唱片电子游戏机录像带帽子笔记本在哪儿?在床上。 3a 亲爱的飞飞:请把这些东西带给你的姐姐:她的帽子、手表、笔记本、钥匙和身份证。帽子在梳妆台上。手表在

英语冠词用法总结(完整)

英语冠词用法总结(完整) 一、单项选择冠词 1.An engineer has designed _______ robot that can work in _______ deep sea to clean waste. A.a; the B.a; a C./; the D.the; / 【答案】A 【解析】 这题考查冠词;第一空填a,泛指“一个机器人”,第二空填the,特指“在深海”,句意是:一个工程师发明的一个机器人可以在深海工作清除废物的。选A。 2.Mr. Brown, ______ chairman of the trade union, will visit our factory in _____ month of May. A./; the B.a; the C.the; / D.the; the 【答案】A 【解析】 这题冠词的用法:第一空不填,因为chairman是职位,第二空填the,是特指5月。选A。 3.----- Do you go to ______ church every Sunday? ----- Yes. I believe _______God blesses me all _____ time. A.the;/; the B./ ; /; / C.a; /; the D./; /; the 【答案】D 【解析】 考查冠词,第一空不填,表示go to church“去教堂”,第二空不填,上帝前面不加冠词,第三空填the,all the time“一直”,句意是:|你每个星期天做礼拜吗?|是的,我相信上帝会一直保佑我的。选D。 4._______ meeting held last night was _________ great success. A.A; a B.A ; / C.The ; a D.The ; / 【答案】C 【解析】 考查冠词。The meeting为特指昨天晚上举行的会议;success作为成功的人或事,为可数名词,选C。 5.What ________ wonderful time we had at ________ Smiths’ then! A.a; 不填B.a; the C.不填;the D.the; the 【答案】B 【解析】 句意:那时我们在史密斯家有一段多么美好的日子呀!第一空:time 在这指日子,时期。是可数名词所以用a,第二空:the+ Smiths,指史密斯一家,所以选B。

人教版新目标英语七年级上册同步阅读

人教版新目标英语七年级上册同步阅读 Unit 1 My name's Gina. 同步阅读 读短文,选择正确的答案。 I am a Chinese girl. My name is Zhang Hua. My English name is Mary. I'm 13 years old. I'm in No. 11 Middle School. At school I have a good friend, Ann. She is an American girl. She is 12. We are in Class 2, Grade 1. Our English teacher is Miss Li. She is a nice teacher. She looks young. We all like her. 1. Mary is girl. A. an English B. a Chinese C. an American 2. Zhang Hua is years old. A. 11 B. 12 C. 13 3. The two children are in Grade . A. One B. Two C. Three 4. Miss Li is our teacher. A. Chinese B. English C. math 5. --- How old is Miss Li? --- . A. She is young. B. She is 20.

C. Sorry, I don't know. Unit 2 Is this your pencil? 同步阅读读对话,选择正确的答案。 A: What's that over there? B: Where? A: Over there, on the floor under the desk. B: Let's go and see. Oh, it's a new watch. It looks like yours. A: Is it a black one? My watch is black. B: No, it's a white one. A: I know. It's Jim's. Jim can't find his watch. B: Let's go and ask him. Hi, Jim. What's the time? C: Sorry, I can't find my watch. B: Is your watch a white one like this? C: Let me see. Yes, it's mine. B: Here you are. C: Thank you very much. B: That's all right. 1. --- What's that on the floor? --- . A. A new watch B. A black one C. A white one D. A bag 2. --- Whose watch is it?

冠词a,anthe以及零冠词的用法及练习详解

冠词分为不定冠词(a, an),定冠词(the),和零冠词。一.不定冠词(a, an) 1.指一类人或事,相当于a kind of A plane is a machine that can fly. 2.第一次提及某人某物,非特指 A boy is waiting for you.有个男孩在等你。 3.表示“每一”相当于every,one We study eight hours a day. 4.表示“相同”相当于the same We are nearly of an age. 5.用于人名前,表示不认识此人或与某名人有类似性质的人或事 That boy is rather a Lei Feng.(活雷锋) 6.用于固定词组中 a couple of, a bit, once upon a time, in a hurry, have a walk, many a time 7.用于quite, rather, many, half, what, such之后 This room is rather a big one. 8.用于so(as, too, how)+形容词之后 She is as clever a girl as you can wish to meet. 9.用于抽象名词具体化的名词前 success(抽象名词)→a success(具体化) 成功的人或事 a failure 失败的人或事 a shame 带来耻辱的人或事 a pity 可惜或遗憾的事 a must 必需必备的东西 a good knowledge of 精通掌握某一方面的知识 10.与序数词连用,表示“又一,再一”。 In order to find a better job, he decided to study a second foreign language. 为了找到一个更好的工作,他决定再学习另外一门外语。 二.定冠词(the) 1.表示某一类人或物 In many places in China, ___ bicycle is still ___ popular means of transportation. A. a; the B. /; a C. the; a D. the; the 2.用于世上独一无二的事物名词前 the universe, the moon, the Pacific Ocean 3.表示说话双方都了解的或上文提到过的人或事 Would you mind opening the door? 4.用于演奏乐器 play the violin, play the guitar 5.用于形容词和分词前表示一类人 the reach, the living, the wounded 6.表示“一家人”或“夫妇”(对比上文的不定冠词用法5) —Could you tell me the way to ____ Johnsons, please? —Sorry, we don’t have ____ Johnson here in the village.

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努力和艰苦的奋斗得来的。 4)通过介绍英文名字的由来,使学生产生对西方文化的好奇及兴趣。4.认知目标: 1)词汇: clock, hello, hi, and, question, answer, look, first name, last name 2) 语法项目:一般现在时be的用法 以特殊疑问词what开头的问句 形容词性物主代词my, your, his, her What’s=What is I’m=I am My name’s=My name is 3) 语言目标: What’s your name? My name is Gina. I’m Gina. Nice to meet you. 2

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七年级英语上人教版教材听力原文

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Starter Unit 1

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