module clk_div(clk_p,clk_n,rst,clk_div);
input clk_p,rst;
input clk_n;
output clk_div;
reg clk_div;
reg[23:0] count;
wire clk;
always @ (posedge clk)
if(rst)
begin
count <= 1'b0;
clk_div <= 1'b0;
end
else
if ( count==24'hffffff)
begin
count <= count + 1'b1;
end
else
begin
count <= 1'b0;
clk_div <= ~clk_div;
end
//差分时钟例化原语
IBUFDS UUT_IBUFG(.I(clk_p),
.IB(clk_n),
.O(clk));
endmodule
ucf文件
NET "clk_p" LOC=AD12 |IOSTANDARD=LVDS; //200M
NET "clk_n" LOC=AD11 |IOSTANDARD=LVDS; //200M
NET "rst" LOC=AG5 |IOSTANDARD=LVCMOS15;//sw3
NET "clk_div" LOC=AB8 |IOSTANDARD=LVCMOS15;//LED0