Advanced Verification of Low Power Design
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1 Advanced Verification of Low Power
Designs
Stephen Bailey, Mentor Graphics
Gabriel Chidolue, Mentor Graphics
Longmont, USA
Newbury, UK
Abstract
Power consumption due to leakage has become a
major factor in the total power consumption
equation for battery powered and sub-100 nm
designs, compelling design teams to adopt various
power management design techniques. Power
gating is one of the most effective techniques for
managing leakage power. In addition, at sub-65 nm
process nodes, different biasing techniques are
being combined with power gating in order to
minimize leakage power.
Employing low power techniques, such as power
gating and substrate biasing, gives rise to many
thorny verification challenges. For example, are
the power control sequences correct; is my biasing
strategy functionally correct; do the “awake”
portions of the design still function correctly when
other domains are powered down; is adequate state
information retained when state retention is
employed; is the proper retention protocol
followed; and is my isolation strategy functionally
correct.
Table of Contents
1. Introduction 2. Power Management Techniques and Functional Verification Implications a. Power Gating and Biasing b. Multi Voltage c. Dynamic Voltage Scaling 3. Unified Power Format 4. Power Aware Verification Solution a. Power Domain Specification b. Power State Specification c. Specification of Isolation, Retention and Level Shifting d. Accurate Retention Register Modeling e. Accurate Simulation of Power-Aware Behavioral Semantics for Shut-Down and Bias f. Assertion Checks and Coverage Opportunities 5. Conclusion Introduction
There are two main sources of power dissipation in
today’s complex System-on-Chips (SoC): Dynamic
and Static. Dynamic power dissipation is associated
with switching activity. Static power dissipation is
the leakage current through transistors when they
are inactive.
The most commonly used technique for leakage
power reduction in ASIC design is power gating.
With power gating, during periods of no activity,
one or more functional sets of an SoC circuit are
switched off and the passage from source to ground
is blocked, thereby eliminating leakage in the
inactive portions of the SoC.
Substrate (also known as body or back) biasing
techniques exploit the physical properties of silicon
by applying a voltage the substrate (N-well or P-
well) increasing the threshold by which the
transistors switch. This slows the performance of
the transistor. More importantly, it significantly
reduces power leakage through the transistor. The
benefit of back biasing is the ability of the
transistors to retain their state as long as the data
input does not change. Back bias provides most of
the power efficiency gains of power gating without
requiring retention registers. Functional verification
of power gating and substrate biasing introduces
significant verification challenges
Until recently, these functional verification
challenges were attacked either at the gate level or,
at best, via RTL simulation run-scripts and user-
crafted PLI applications. Although these approaches
served the need when there were a few power
domains, they do not scale to the 10’s of domains
common in today’s SoCs. Gate-level verification
poses many issues including low productivity,
difficult debug, and complex debug resolution (fix
RTL and re-spin implementation or ECO the
change leaving the “golden” RTL wrong).
Specifying power information directly into RTL
code also has disadvantages. Directly instantiating
retention registers has a negative impact on the RTL
coding style where virtually all registers are
implicit. The RTL encapsulates reusable design
blocks, some of which are millions of gates in size.
Each chip incorporating the RTL IP has a unique
power architecture. Embedding power specifics into
the golden RTL reduces the benefits of reuse as it
must be updated for each chip implementation. This
breaks the separation of design from
implementation and forces re-verification of the
blocks simply due to power implementation
differences — a time consuming exercise. Thus,
verification of power aware designs must begin at
the RTL while preserving the separation of design
intent from implementation.
