CS5509-ASZR;CS5509-ASZ;中文规格书,Datasheet资料

中文使用说明VA 550 / VA 570流量传感器VA 550 VA 570 中文 V1.01页 1 of 31前言I. 前言亲爱的用户,非常感谢您决定选择VA 550 / VA 570. 请在安装和启动设备之前仔细阅读本安装和操作手册并按照我们的建议。

在仔细研究上述说明的情况下保证VA 550 / VA 570的无风险操作和正确的运作。

Sales Office South / Geschäftsstelle SüdZindelsteiner Str. 15D-78052 VS-TannheimTel.: +49 (0) 7705 978 99 0Fax: +49 (0) 7705 978 99 20Mail:***********************Web: Sales Office North / Geschäftsstelle NordAm Oxer 28cD-24955 HarrisleeTel.: +49 (0) 461 700 20 25Fax: +49 (0) 461 700 20 26Mail:***********************Web: VA 550 VA 570 英文V1.01 页 2 of 31目录表II.I. II. 1 2 3目录表前言 (2)目录表 (3)符号象征和标志 (5)信号根据ISO 3864 and ANSI Z 535 (5)安全注意事项 (6)3.1 3.2 设计用途 (7)安装调试 (7)4 技术参数 (8)4.14.1.14.1.2 电流型号 (9)Modbus (9)电流输出 (9)4.1.2.1 4.1.2.2 Aktive (9)Passive (9)4.1.34.1.4 4.2 4.3Pulse (9)Alarm (9)插入式流量计VA550 量程范围– (10)法兰版本VA570 量程范围 (11)5 尺寸 (12)5.1 5.1 5.2 5.3 VA 550 尺寸 (12)VA 570 尺寸 (13)螺纹版本VA 570 尺寸 (13)法兰版本VA 570 尺寸 (14)6 安装 (15)6.16.26.36.3.16.3.2 6.46.4.16.4.2 6.5 6.6 管/管要求 (15)进口 / 出口运行 (15)VA 550安装 (16)½“ 焊接接头带球阀 ½“ (16)定心钻带球阀 (16)传感器安装 (17)安装VA 550 进入到球阀上 (17)VA 570安装 (17)标准显示器(Housing) (18)紧固力矩 (18)VA 550 VA 570中文V1.01 页 3 of 31目录表7 连接图 (19)7.17.27.2.17.2.27.2.3 连接器引脚分配 (19)接线 (20)一般: (20)电源 (20)Modbus (termination): (20)8 VA 550 / VA 570操作 (21)8.18.1.1 8.28.38.3.18.3.2 主菜单(Home) (21)操作 (21)主菜单 (22)设置 (22)设置 (23)Modbus 设置 (24)8.3.2.1 8.3.2.2 Modbus 设置 (2001...2005).. (24)寄存器值(1001 ...1500 (25)8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 脉冲/报警 (27)用户设置 (27)先进 (27)4 -20mA (27)VA 550 / VA 570 Info (28)9 10 补充文档 (29)更改历史记录 (30)VA 550 VA 570 中文 V1.01 页 4 of 31象形图/ 符号12 象形图和符号一般警告符号 (危险, 警告, 注意)一般注意事项 安装指导手册 (铭牌) 安装和说明书要考虑Signalwords 根据 ISO3864 和ANSI Z 535 危险r!警告!注意!留意!重要的!迫在眉睫的危险由于不正确的处理结果:严重的人身伤害或死亡可能的危险由于不正确的处理结果: 可能的严重伤害或死亡迫在眉睫的危险由于不正确的处理结果: 可能的人身伤害或损害可能的危险由于不正确的处理结果: 可能的人身伤害或损害其他注意事项, 信息, 提示由于不正确的处理结果: 操作和维护的缺点, 没有危险VA 550 VA 570 中文 V1.01页5 of 31安全注意事项3安全注意事项请检查本手册是否有对应的设备型号按照本手册中的所有说明。

Copyright © Cirrus Logic, Inc. 2000CS5521/22/23/24/2816-Bit or 24-Bit, 2/4/8-Channel ADCs with PGIAFeaturesl Low Input Current (100pA), ChopperStabilized Instrumentation Amplifier l Scalable Input Span (Bipolar/Unipolar)-2.5V VREF: 25mV, 55mV, 100mV, 1V, 2.5V, 5V-External: 10V, 100 Vl Wide V REF Input Range (+1 to +5V)l Fourth Order Delta-Sigma A/D Converter l Easy to Use Three-wire Serial Interface Port-Programmable/Auto Channel Sequencer with Conversion Data FIFO-Accessible Calibration Registers per Channel -Compatible with SPI TM and Microwire TMl System and Self-Calibration l Eight Selectable Word Rates-Up to 617Hz (XIN =200kHz)-Single Conversion Settling-50/60Hz ±3Hz Simultaneous Rejectionl Single +5V Power Supply Operation-Charge Pump Drive for Negative Supply -+3 to +5V Digital Supply Operationl Low Power Consumption: 5.5mWGeneral DescriptionThe CS5521/22/23/24/28 are highly integrated ∆Σ Ana-log-to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) performance. The ADCs come as either two-channel (CS5521/22), four-channel (CS5523/24), or eight-channel (CS5528) devices, and include a low input current, chopper-stabilized instru-mentation amplifier. To permit selectable input spans of 25mV, 55mV, 100mV, 1V, 2.5V, and 5V, the ADCs include a PGA (programmable gain amplifier). To ac-commodate ground-based thermocouple applications,the devices include a Charge Pump Drive which pro-vides a negative bias voltage to the on-chip amplifiers.These devices also include a fourth order ∆Σ modulator followed by a digital filter which provides eight selectable output word rates . The digital filters are designed to settle to full accuracy within one conversion cycle and when operated at word rates below 30Hz, they reject both 50and 60Hz interference.These single supply products are ideal solutions for measuring isolated and non-isolated, low-level signals in process control applications.ORDERING INFORMATIONSee page 51.ProgrammableGainVA+AGND VREF+VREF-VD+DGND XIN XOUTSDOSDI NBVLatchDifferential Digital FilterCalibration Register Control RegisterOutput Register4th Order ∆ΣModulatorCalibration MemoryCalibration µCClock Gen.SCLK CS MUXAIN2++X20X1X1X1CS5524 ShownAIN2-AIN1+AIN1-AIN4+AIN4-AIN3+AIN3-A0A1CPDData FIFO MAY ‘00DS317F2TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS (5)ANALOG CHARACTERISTICS (5)TYPICAL RMS NOISE, CS5521/23 (7)TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 (7)TYPICAL RMS NOISE, CS5522/24/28 (8)TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 (8)5 V DIGITAL CHARACTERISTICS (9)3 V DIGITAL CHARACTERISTICS (9)DYNAMIC CHARACTERISTICS (10)RECOMMENDED OPERATING CONDITIONS (10)ABSOLUTE MAXIMUM RATINGS (10)SWITCHING CHARACTERISTICS (11)2. GENERAL DESCRIPTION (13)2.1 Analog Input (13)2.1.1 Instrumentation Amplifier (14)2.1.2 Coarse/Fine Charge Buffers (14)2.1.3 Analog Input Span Considerations (15)2.1.4 Measuring Voltages Higher than 5 V (15)2.1.5 Voltage Reference (16)2.2 Overview of ADC Register Structure and Operating Modes (16)2.2.1 System Initialization (18)2.2.2 Serial Port Initialization Sequence (18)2.2.3 Command Register Quick Reference (19)2.2.4 Command Register Descriptions (20)2.2.5 Serial Port Interface (25)2.2.6 Reading/Writing the Offset, Gain, and Configuration Registers (26)2.2.7 Reading/Writing the Channel-Setup Registers (26)2.2.7.1 Latch Outputs (28)2.2.7.2 Channel Select Bits (28)2.2.7.3 Output Word Rate Selection (28)2.2.7.4 Gain Bits (28)2.2.7.5 Unipolar/Bipolar Bit (28)2.2.8 Configuration Register (28)2.2.8.1 Chop Frequency Select (28)2.2.8.2 Conversion/Calibration Control Bits (28)2.2.8.3 Power Consumption Control Bits (28)Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: /corporate/contacts/SPI™ is a trademark of Motorola Inc., Microwire™ is a trademark of National Semiconductor Corp.Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval sys-tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at .2.2.8.4 Charge Pump Disable (29)2.2.8.5 Reset System Control Bits (29)2.2.8.6 Data Conversion Error Flags (29)2.3 Calibration (31)2.3.1 Self Calibration (31)2.3.2 System Calibration (32)2.3.3 Calibration Tips (34)2.3.4 Limitations in Calibration Range (34)2.4 Performing Conversions and Reading the Data Conversion FIFO (34)2.4.1 Conversion Protocol (35)2.4.1.1 Single, One-Setup Conversion (35)2.4.1.2 Repeated One-Setup Conversions without Wait (35)2.4.1.3 Repeated One-Setup Conversions with Wait (36)2.4.1.4 Single, Multiple-Setup Conversions (36)2.4.1.5 Repeated Multiple-Setup Conversions without Wait (37)2.4.1.6 Repeated Multiple-Setup Conversions with Wait (37)2.4.2 Calibration Protocol (38)2.4.3 Example of Using the CSRs to Perform Conversions and Calibrations (38)2.5 Conversion Output Coding (40)2.5.1 Conversion Data FIFO Descriptions (41)2.6 Digital Filter (42)2.7 Clock Generator (42)2.8 Power Supply Arrangements (43)2.8.1 Charge Pump Drive Circuits (45)2.9 Digital Gain Scaling (45)2.10 Getting Started (46)2.11 PCB Layout (47)3. PIN DESCRIPTIONS (48)3.1 Clock Generator (49)3.2 Control Pins and Serial Data I/O (49)3.3 Measurement and Reference Inputs (49)3.4 Power Supply Connections (50)4. SPECIFICATION DEFINITIONS (51)5. ORDERING GUIDE (51)6. PACKAGE DIMENSION DRAWINGS (52)LIST OF FIGURESFigure 1. Continuous Running SCLK Timing (Not to Scale) (12)Figure 2. SDI Write Timing (Not to Scale) (12)Figure 3. SDO Read Timing (Not to Scale) (12)Figure 4. Multiplexer Configurations (13)Figure 5. Input Models for AIN+ and AIN- pins, £(100 mV Input Ranges (14)Figure 6. Input Models for AIN+ and AIN- pins, >100 mV input ranges (14)Figure 7. Input Ranges Greater than 5 V (16)Figure 8. Input Model for VREF+ and VREF- Pins (16)Figure 9. CS5523/24 Register Diagram (17)Figure 10. Command and Data Word Timing (25)Figure 11. Self Calibration of Offset (Low Ranges) (32)Figure 12. Self Calibration of Offset (High Ranges) (32)Figure 13. Self Calibration of Gain (All Ranges) (32)Figure 14. System Calibration of Offset (Low Ranges) (32)Figure 15. System Calibration of Offset (High Ranges) (33)Figure 16. System Calibration of Gain (Low Ranges) (33)Figure 17. System Calibration of Gain (High Ranges) (33)Figure 18. Filter Response (Normalized to Output Word Rate = 1) (42)Figure 19. Typical Linearity Error for CS5521/23 (42)Figure 20. Typical Linearity Error for CS5522/24/28 (42)Figure 21. CS5522 Configured to use on-chip charge pump to supply NBV (43)Figure 22. CS5522 Configured for ground-referenced Unipolar Signals (44)Figure 23. CS5522 Configured for Single Supply Bridge Measurement (44)Figure 24. Charge Pump Drive Circuit for VD+ = 3 V (45)Figure 25. Alternate NBV Circuits (45)LIST OF TABLESTable 1. Relationship between Full Scale Input, Gain Factors, and Internal AnalogSignal Limitations (15)Table 2. Command Register Quick Reference (19)Table 3. Channel-Setup Registers (27)Table 4. Configuration Register (30)Table 5. Offset and Gain Registers (31)Table 6. Output Coding for 16-bit CS5521/23 and 24-bit CS5522/24/28 (40)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS (T A = 25° C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND,NBV = -2.1 V, XIN = 32.768 kHz, CFS1-CFS0 = ‘00’, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40° C ~ +85° C.2.Specifications guaranteed by design, characterization, and/or test.3.Specification applies to the device only and does not include any effects by external parasiticthermocouples. LSB N : N is 16 for the CS5521/23 and N is 24 for the CS5522/24/284.Drift over specified temperature range after calibration at power-up at 25° C.5.Measured with Charge Pump Drive off.6.All outputs unloaded. All input CMOS levels and the CS5521/23 do not have a low power mode.ParameterCS5521/23CS5522/24/28Unit Min Typ Max Min Typ Max Accuracy Resolution --16--24Bits Linearity Error -±0.0015±0.003-±0.0007±0.0015%FS Bipolar Offset (Note 3)-±1±2-±16±32LSB N Unipolar Offset (Note 3)-±2±4-±32±64LSB N Offset Drift (Notes 3 and 4)-20--20-nV/°C Bipolar Gain Error -±8±31-±8±31ppm Unipolar Gain Error -±16±62-±16±62ppm Gain Drift (Note 4)-13-13ppm/°CPower SuppliesPower Supply Currents (Normal Mode)I A+(Note 5)I D+I NBV- - - 0.990260 1.2135375 - - - 1.590525 1.9135700mA µA µA Power Consumption (Note 6)Normal Mode Low Power Mode Standby Sleep-N/A -- 5.5N/A 1.25007.5N/A ------95.51.2500127.5--mW mW mW µW Power Supply RejectionPositive Supplies dc NBV--120110----120110--dB dBANALOG CHARACTERISTICS (Continued)Notes:7.For the CS5528, the 25mV, 55mV and 100mV ranges cannot be used unless NBV is powered at -1.8to -2.5V8.See the section of the data sheet which discusses input models. Chop clock is 256Hz (XIN/128) forPGIA (programmable gain instrumentation amplifier). XIN = 32.768kHz.9.The maximum full scale signal can be limited by saturation of circuitry within the internal signal path.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar ModeNBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mVRange = 1 V, 2.5 V, or 5 VNBV = AGND Range = 25 mV, 55 mV, or 100 mV (Note 7)Range = 1 V, 2.5 V, or 5 V-0.150NBV 1.850.0----0.950VA+2.65VA+V V V V CVF Current on AIN+ or AIN-(Note 8)Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V--10010300-pA nA Input Current Drift (Note 8)Range = 25 mV, 55 mV, or 100 mV-1-pA/°C Input Leakage for Multiplexer when Off -10-pA Common Mode Rejection dc50, 60 Hz--120120--dB dB Input Capacitance-10-pF Voltage Reference Input Range (VREF+) - (VREF-)12.5VA+V VREF+(VREF-)+1-VA+V VREF-NBV -(VREF+)-1V CVF Current (Note 8)- 5.0-nA Common Mode Rejection dc50, 60 Hz--110130--dB dB Input Capacitance-16-pFSystem Calibration SpecificationsFull Scale Calibration Range (VREF = 2.5V)Bipolar/Unipolar Mode25 mV 55 mV 100 mV 1 V 2.5 V 5 V1025400.401.02.0------32.571.51051.303.25VA+mV mV mV V V V Offset Calibration Range Bipolar/Unipolar Mode25 mV 55 mV 100 mV (Note 9)1 V 2.5 V 5 V------------±12.5±27.5±50±0.5±1.25±2.50mV mV mV V V VTYPICAL RMS NOISE, CS5521/23 (Notes 10 and 11)Notes:10.Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C.11.To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates.12.For input ranges <100mV and output rates ≥60Hz, 16.384kHz chopping frequency is used.TYPICAL NOISE FREE RESOLUTION (BITS), CS5521/23 (Note 13)Notes:13.For bipolar mode, the number of bits of Noise Free Resolution is LOG((2XInput Range)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5521/23’s output conversions are 16 bits. Noise free Resolution numbers are based uponVREF =2.5V and XIN =32.768kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor.Output Rate (Hz)-3 dB FilterFrequency Input Range, (Bipolar/Unipolar Mode)25 mV55 mV 100 mV 1 V 2.5 V 5 V1.88 1.6490 nV 148 nV 220 nV 1.8 µV 3.9 µV 7.8 µV 3.76 3.27122 nV 182 nV 310 nV2.6 µV 5.7 µV 11.3 µV 7.51 6.55180 nV 267 nV 435 nV3.7 µV 8.5 µV 18.1 µV 15.012.7280 nV 440 nV 810 nV 5.7 µV 14 µV 28 µV 30.025.4580 nV 1.1 µV 2.1 µV 18.2 µV 48 µV 96 µV 61.6 (Note 12)50.4 2.6 µV4.9 µV 8.5 µV 92 µV 238 µV 390 µV 84.5 (Note 12)70.711 µV 27 µV 43 µV 458 µV 1.1 mV 2.4 mV 101.1 (Note 12)84.641 µV72 µV 130 µV 1.2 mV 3.4 mV6.7 mVOutput Rate (Hz)-3 dB FilterFrequency Input Range, (Bipolar Mode)25 mV55 mV 100 mV 1 V 2.5 V5 V 1.88 1.641616161616163.76 3.271616161616167.51 6.5515161616161615.012.715151516161630.025.414141414141461.6 (Note 12)50.412121212121284.5 (Note 12)70.7999999101.1 (Note 12)84.6888888TYPICAL RMS NOISE, CS5522/24/28 (Notes 14 and 15)Notes:14.Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C.15.To estimate Peak-to-Peak Noise, multiply RMS noise by 6.6 for all ranges and output rates.16.For input ranges <100mV and output rates ≥60Hz, 16.384kHz chopping frequency is used.TYPICAL NOISE FREE RESOLUTION (BITS), CS5522/24/28 (Note 17)Notes:17.For bipolar mode, the number of bits of Noise Free Resolution is LOG((2XInput Range)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For unipolar mode, the number of bits of Noise Free Resolution is LOG((Input Range)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. Also, the CS5522/24/28’s output conversions are 24 bits. Noise free Resolution numbers are based uponVREF =2.5V and XIN =32.768kHz. The values will be affected directly by changes in VREF, but the effects due to changes in the XIN frequency will be minor.Output Rate (Hz)-3 dB FilterFrequency Input Range, (Bipolar/Unipolar Mode)25 mV55 mV 100 mV 1 V 2.5 V 5 V1.88 1.6490 nV 95 nV 140 nV 1.5 µV 3 µV 6 µV 3.76 3.27110 nV 130 nV 190 nV 2 µV 4 µV 8 µV 7.51 6.55170 nV 200 nV 275 nV2.5 µV 6 µV 11.5 µV 15.012.7250 nV 330 nV 580 nV 4.5 µV 10 µV 20 µV 30.025.4500 nV 1 µV 1.5 µV 16 µV 45 µV 85 µV 61.6 (Note 16)50.4 2 µV 4 µV 8 µV 72 µV 195 µV 350 µV 84.5 (Note 16)70.710 µV 20 µV 35 µV 340 µV 900 µV 2 mV 101.1 (Note 16)84.630 µV60 µV 105 µV 1.1 mV 3 mV5.3 mVOutput Rate (Hz)-3 dB FilterFrequency Input Range, (Bipolar Mode)25 mV55 mV 100 mV 1 V 2.5 V5 V 1.88 1.641617181818183.76 3.271617171718187.51 6.5515161717171715.012.715161616161630.025.414141414141461.6 (Note 16)50.412121212121284.5 (Note 16)70.7101010101010101.1 (Note 16)84.68888885 V DIGITAL CHARACTERISTICS (T A = 25° C; VA+, VD+ = 5 V ±5%; GND = 0;See Notes 2 and 18.))Notes:18.All measurements performed under static conditions.19.I out = -100µA unless stated otherwise. (V OH = 2.4 V @ I out = -40µA.)3 V DIGITAL CHARACTERISTICS (T A = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0;See Notes 2 and 18.)ParameterSymbol Min Typ Max Unit High-Level Input VoltageAll Pins Except XIN and SCLKXIN SCLK V IH0.6 VD+(VD+)-0.5(VD+) - 0.45------V V V Low-Level Input VoltageAll Pins Except XIN and SCLKXIN SCLKV IL------0.81.50.6V V V High-Level Output VoltageAll Pins Except CPD and SDO (Note 19)CPD, I out = -4.0 mA SDO, I out = -5.0 mA V OH(VA+) - 1.0(VD+) - 1.0(VD+) - 1.0------V V V Low-Level Output VoltageAll Pins Except CPD and SDO, I out = 1.6 mACPD, I out = 2 mA SDO, I out = 5.0 mA V OL------0.40.40.4V V V Input Leakage Current I in -±1±10µA 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-Level Input VoltageAll Pins Except XIN and SCLKXIN SCLK V IH0.6 VD+(VD+)-0.5(VD+) - 0.45------V V V Low-Level Input VoltageAll Pins Except XIN and SCLKXIN SCLKV IL------0.16 VD+0.30.6V V V High-Level Output VoltageAll Pins Except CPD and SDO, I out = -400 µACPD, I out = -4.0 mA SDO, I out = -5.0 mA V OH(VA+) - 0.3(VD+) - 1.0(VD+) - 1.0------V V V Low-Level Output VoltageAll Pins Except CPD and SDO, I out = 400 µACPD, I out = 2 mA SDO, I out = 5.0 mA V OL------0.30.40.4V V V Input Leakage Current I in -±1±10µA 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICSRECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 20.)Notes:20.All voltages with respect to ground.ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 20.)Notes:21.No pin should go more negative than NBV - 0.3V.22.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.23.Transient current of up to 100mA will not cause SCR latch-up. Maximum input current for a powersupply pin is ±50mA.24.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Frequencyf s XIN/4Hz Filter Settling Time to 1/2 LSB (Full Scale Step)t s1/f outsParameterSymbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog VD+VA+ 2.74.75 5.05.0 5.255.25V V Analog Reference Voltage (VREF+) - (VREF-)VRef diff 1.0 2.5VA+V Negative Bias VoltageNBV-1.8-2.1-2.5VParameterSymbol Min Typ Max Unit DC Power Supplies(Note 21)Positive Digital Positive Analog VD+VA+-0.3-0.3--+6.0+6.0V V Negative Bias VoltageNegative Potential NBV +0.3-2.1-3.0V Input Current, Any Pin Except Supplies (Note 22 and 23)I IN --±10mA Output Current I OUT --±25mA Power Dissipation (Note 24)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA NBV -0.3NBV -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage TemperatureT stg-65-150°CSWITCHING CHARACTERISTICS (T A = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF.))Notes:25.Device parameters are specified with a 32.768kHz clock; however, clocks up to 200kHz(CS5522/24/28) or 130kHz (CS5521/23) can be used for increased throughput.26.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.27.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.28.Applicable when SCLK is continuously running.Specifications are subject to change without notice.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 25)External Clock or Internal Oscillator (CS5522/24/28)(CS5521/23)XIN303032.76832.768200130kHz kHz Master Clock Duty Cycle 40-60%Rise Times(Note 26)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 26)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 32.768 kHz(Note 27)t ost -500-ms Power-on Reset Period t por-2006-XIN cycles Serial Port Timing Serial Clock FrequencySCLK 0-2MHz SCLK Falling to CS Falling for continuous running SCLK(Note 28)t 0100--ns Serial ClockPulse Width High Pulse Width Lowt 1t 2250250----ns ns SDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disablet 6100--ns SDO Read TimingCS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150nsFigure 1. Continuous Running SCLK Timing (Not to Scale)Figure 2. SDI Write Timing (Not to Scale)Figure 3. SDO Read Timing (Not to Scale)2. GENERAL DESCRIPTIONThe CS5521/22/23/24/28 are highly integrated ∆ΣAnalog-to-Digital Converters (ADCs) which use charge-balance techniques to achieve 16-bit (CS5521/23) and 24-bit (CS5522/24/28) perfor-mance. The ADCs come as either two-channel (CS5521/22), four-channel (CS5523/24), or eight-channel (CS5528) devices, and include a low input current, chopper-stabilized instrumentation ampli-fier. To permit selectable input spans of 25mV, 55mV, 100mV, 1V, 2.5V, and 5V, the ADCs in-clude a PGA (programmable gain amplifier). To accommodate ground-based thermocouple applica-tions, the devices include a CPD (Charge Pump Drive) which provides a negative bias voltage to the on-chip amplifiers.These devices also include a fourth order DS mod-ulator followed by a digital filter which provides eight selectable output word rates of 1.88Hz, 3.76Hz, 7.51Hz, 15Hz, 30Hz, 61.6Hz, 84.5Hz, and 101.1Hz (XIN=32.768kHz). The devices are capable of producing output update rates up to 617Hz when a 200kHz clock is used (CS5522/24/28) or up to 401Hz using a 130kHz clock (CS5521/23). Further note that the digital fil-ters are designed to settle to full accuracy within one conversion cycle and simultaneously reject both 50Hz and 60Hz interference when operated at word rates below 30Hz (assuming a XIN clock frequency of 32.768kHz).To ease communication between the ADCs and a micro-controller, the converters include an easy to use three-wire serial interface which is SPI™ and Microwire™ compatible.2.1 Analog InputFigure4 illustrates a block diagram of the analog in-put signal path inside the CS5521/22/23/24/28. The front end consists of a multiplexer (break before make configuration), a chopper-stabilized instru-mentation amplifier with fixed gain of 20X, coarse/fine charge buffers, and a programmable gain section. For the 25mV, 55mV, and 100mV input ranges, the input signals are amplified by the 20X in-strumentation amplifier. For the 1V, 2.5V, and 5V input ranges, the instrumentation amplifier is by-passed and the input signals are connected to the Programmable Gain block via coarse/fine charge buffers.Figure 4. Multiplexer Configurations2.1.1 Instrumentation AmplifierThe instrumentation amplifier is chopper stabilized and is activated any time conversions are performed with the low level input ranges, ≤100mV. The am-plifier is powered from VA+ and from the NBV (Negative Bias Voltage) pin allowing the CS5521/22/23/24/28 to be operated in either of two analog input configurations. The NBV pin can be bi-ased to a negative voltage between -1.8V and -2.5V, or tied to AGND (for the CS5528, NBV has to be between -1.8V and -2.5V for the ranges below 100mV when the amplifier is engaged). The com-mon-mode plus signal range of the instrumentation amplifier is 1.85V to 2.65V with NBV grounded. The common-mode plus signal range of the instru-mentation amplifier is -0.150V to 0.950V with NBV between -1.8V to -2.5V. Whether NBV is tied between -1.8V and -2.5V or tied to AGND, the (Common Mode + Signal) input on AIN+ and AIN- must stay between NBV and VA+.Figure5illustrates an analog input model for the ADCs when the instrumentation amplifier is en-gaged. The CVF (sampling) input current for each of the analog input pins depends on the CFS1 and CFS0 (Chop Frequency Select) bits in the configu-ration register (see Configuration Register for de-tails). Note that the CVF current is lowest with the CFS bits in their default states (cleared to logic 0s). Further note that the CVF current into the instru-mentation amplifier is less than 300 pA over -40°C to +85°C. Note that Figure5 is for input current modeling only. For physical input capacitance see ‘Input Capacitance’ specification under ANALOG CHARACTERISTICS. Also refer to Applications Note AN30 “Switched-Capacitor A/D Converter Input Structures” for more details on input models and input sampling currents.Note: Residual noise appears in the converter’s baseband for output word rates greater than 61.6Hz if the CFS bits are logic 0 (chop clock=256Hz). For word rates of 30Hz and lower, 256Hz chopping is recommended, and for 61.6Hz, 84.5Hz and 101.1Hz filters, 4096Hz chopping is recommended.2.1.2 Coarse/Fine Charge BuffersThe unity gain buffers are activated any time conver-sions are performed with the high level inputs rang-es, 1V, 2.5V, and 5V. The unity gain buffers are designed to accommodate rail to rail input signals. The common-mode plus signal range for the unity gain buffer amplifier is NBV to VA+.Typical CVF (sampling) current for the unity gain buffer amplifiers is about 10nA (XIN=32.768kHz, see Figure6).Figure 5. Input Models for AIN+ and AIN- pins, ≤(100 mV Input Ranges Figure 6. Input Models for AIN+ and AIN- pins,>100 mV input ranges2.1.3 Analog Input Span ConsiderationsThe CS5521/22/23/24/28 is designed to measure full scale ranges of 25mV, 55mV, 100mV, 1V,2.5V and 5V. Other full scale values can be ac-commodated by performing a system calibration within the limits specified. See the Calibration sec-tion for more details. Another way to change the full scale range is to increase or to decrease the voltage reference to a voltage other than 2.5 . See the Voltage Reference section for more details. Three factors set the operating limits for the input span. They include: instrumentation amplifier satu-ration, modulator 1’s density, and a lower reference voltage. When the 25mV, 55mV or 100mV range is selected, the input signal (including the common mode voltage and the amplifier offset voltage)must not cause the 20X amplifier to saturate in ei-ther its input stage or output stage. To prevent sat-uration the absolute voltages on AIN+ and AIN-must stay within the limits specified (refer to the Analog Input section). Additionally, the differen-tial output voltage of the amplifier must not exceed 2.8V. The equationABS(VIN + VOS) x 20 = 2.8Vdefines the differential output limit, whereVIN = (AIN+) - (AIN-)is the differential input voltage and VOS is the ab-solute maximum offset voltage for the instrumenta-tion amplifier (VOS will not exceed 40mV). If the differential output voltage from the amplifier ex-ceeds 2.8V, the amplifier may saturate, which will cause a measurement error.The input voltage into the modulator must not cause the modulator to exceed a low of 20 percent or a high of 80 percent 1's density. The nominal full scale input span of the modulator (from 30 percent to 70 percent 1’s density) is determined by the VREF voltage divided by the Gain Factor. See Table 1 to determine if the CS5521/22/23/24/28are being used properly. For example, in the 55mV range, to determine the nominal input volt-age to the modulator, divide VREF (2.5V) by the Gain Factor (2.2727).When a smaller voltage reference is used, the re-sulting code widths are smaller causing the con-verter output codes to exhibit more changing codes for a fixed amount of noise. Table 1 is based upon a VREF =2.5V. For other values of VREF, the values in Table 1 must be scaled accordingly.2.1.4 Measuring Voltages Higher than 5 VSome systems require the measurement of voltages greater than 5V. The input current of the instru- Note:1.The converter’s actual input range, the delta-sigma’s nominal full scale input, and the delta-sigma’smaximum full scale input all scale directly with the value of the voltage reference. The values in the table assume a 2.5 V VREF voltage.2.The 2.8V limit at the output of the 20X amplifier is the differential output voltage.Input Range (1)Max. Differential Output20X AmplifierVREF Gain Factor∆-Σ Nominal (1)Differential Input∆-Σ(1)Max. Input ±25 mV 2.8 V (2) 2.5V 5±0.5 V ±0.75 V ±55 mV 2.8 V (2) 2.5V 2.272727...±1.1 V ±1.65 V ±100 mV 2.8 V (2)2.5V 1.25±2.0 V ±3.0 V ±1.0 V - 2.5V 2.5±1.0 V ±1.5 V ±2.5 V - 2.5V 1.0±2.5 V ±5.0 V ±5.0 V- 2.5V0.5±5.0 V0V, VA+Table 1. Relationship between Full Scale Input, Gain Factors, and Internal AnalogSignal Limitations。

Multi-vendor Communications with CIP Messages: Data can be exchanged with a
variety of devices connected by EtherNet/IP because it supports the standard CIP (Common Industrial Protocol) message communications. This allows easy communication from an Omron PLC to other vendors EtherNet/IP PLCs.
Troubleshooting Functions: A variety of functions are provided to quickly identify and handle errors.
• Self-diagnosis at power ON. • PING command to check the connection with another node • Error Log functions record the time of occurrence and other error details
OMRON CANADA, INC. • HEAD OFFICE Toronto, ON, Canada • 416.286.6465 • 866.986.6766 •
OMRON ELETRÔNICA DO BRASIL LTDA • HEAD OFFICE São Paulo, SP, Brasil • 55.11.2101.6300 • .br
Rapid Troubleshooting – A variety of built-in functions enable you to quickly identify and handle errors, including connection check with other nodes, unit self-diagnosis and error logging.

105 dB, 192 kHz, Multi-Bit Audio A/D ConverterFeaturesAdvanced Multi-bit Delta-Sigma Architecture 24-bit ConversionSupports All Audio Sample Rates Including192kHz105dB Dynamic Range at 5V -98dB THD+N90 mW Power ConsumptionHigh-Pass Filter to Remove DC Offsets Analog/Digital Core Supplies from 3.3V to 5V Supports Logic Levels between 1.8V and 5V Auto-Detect Mode Selection in Slave Mode Auto-Detect MCLK DividerGeneral DescriptionThe CS5341 is a complete analog-to-digital converter for digital audio systems. It performs sampling, analog-to-digital conversion, and anti-alias filtering, generating 24-bit values for both left and right inputs in serial form at sample rates up to 200kHz per channel.The CS5341 uses a 5th-order, multi-bit Delta-Sigma modulator followed by digital filtering and decimation,which removes the need for an external anti-alias filter. The CS5341 is available in a 16-pin TSSOP package for Commercial (-10° to +70° C) and Automotive grades (-40° to +85° C). The CDB5341 Customer Demonstra-tion Board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 22 for complete ordering information.The CS5341 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as set-top boxes, DVD-karaoke players, DVD record-ers, A/V receivers, and automotive applications.CS5341CS5341 TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS (4)SPECIFIED OPERATING CONDITIONS (4)ABSOLUTE MAXIMUM RATINGS (4)ANALOG CHARACTERISTICS - COMMERCIAL GRADE (5)ANALOG CHARACTERISTICS - AUTOMOTIVE GRADE (6)DIGITAL FILTER CHARACTERISTICS (7)DC ELECTRICAL CHARACTERISTICS (10)DIGITAL CHARACTERISTICS (10)SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (11)2. PIN DESCRIPTION (13)3. TYPICAL CONNECTION DIAGRAM (14)4. APPLICATIONS (15)4.1 Single-, Double-, and Quad-Speed Modes (15)4.2 Operation as Either a Clock Master or Slave (15)4.2.1 Operation as a Clock Master (16)4.2.2 Operation as a Clock Slave with Auto-Detect (16)4.2.3 Master Clock (17)4.3 Serial Audio Interface (17)4.4 Power-Up Sequence (18)4.5 Analog Connections (18)4.6 Grounding and Power Supply Decoupling (18)4.7 Synchronization of Multiple Devices (18)4.8 Capacitor Size on the Reference Pin (FILT+) (19)5. PARAMETER DEFINITIONS (20)6. PACKAGE DIMENSIONS (21)THERMAL CHARACTERISTICS (21)7. ORDERING INFORMATION (22)8. REVISION HISTORY (22)CS5341 LIST OF FIGURESFigure 1.Single-Speed Mode Stopband Rejection (8)Figure 2.Single-Speed Mode Stopband Rejection (8)Figure 3.Single-Speed Mode Transition Band (Detail) (8)Figure 4.Single-Speed Mode Passband Ripple (8)Figure 5.Double-Speed Mode Stopband Rejection (8)Figure 6.Double-Speed Mode Stopband Rejection (8)Figure 7.Double-Speed Mode Transition Band (Detail) (9)Figure 8.Double-Speed Mode Passband Ripple (9)Figure 9.Quad-Speed Mode Stopband Rejection (9)Figure 10.Quad-Speed Mode Stopband Rejection (9)Figure 11.Quad-Speed Mode Transition Band (Detail) (9)Figure 12.Quad-Speed Mode Passband Ripple (9)Figure 13.Master Mode, Left-Justified SAI (12)Figure 14.Slave Mode, Left-Justified SAI (12)Figure 15.Master Mode, I²S SAI (12)Figure 16.Slave Mode, I²S SAI (12)Figure 17.Typical Connection Diagram (14)Figure 18.CS5341 Master Mode Clocking (16)Figure 19.I²S Serial Audio Interface (17)Figure 20.Left-Justified Serial Audio Interface (17)Figure 21.CS5341 Recommended Analog Input Buffer (18)Figure 22.CS5341 THD+N versus Frequency (19)LIST OF TABLESTable 1. Speed Modes and the Associated Output Sample Rates (Fs) (15)Table 2. CS5341 Mode Control (15)Table 3. Master Clock (MCLK) Ratios (17)Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample Rates (17)CS53411.CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at typical supply voltages and T A = 25°C.)SPECIFIED OPERATING CONDITIONS(GND = 0V, all voltages with respect to 0V.)Notes:1.This part is specified at typical analog voltages of 3.3 V and 5.0 V. See Analog Characteristics - Com-mercial Grade and Analog Characteristics - Automotive Grade, below, for details.ABSOLUTE MAXIMUM RATINGS(GND = 0 V, All voltages with respect to ground.) (Note 2)2.Operation beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.3.Any pin except supplies. Transient currents of up to ±100mA on the analog input pins will not causeSRC latch-up.4.The maximum over/under voltage is limited by the input current.ParameterSymbol Min TypMaxUnitPower SuppliesAnalog Digital Logic VA VD VL 3.13.11.7(Note 1)3.33.35.255.255.25V V V Ambient Operating TemperatureCommercial AutomotiveT AC T AC-10-40--7085°C °CParameterSymbol Min Max Units DC Power Supplies:Analog Logic Digital VA VL VD -0.3-0.3-0.3+6.0+6.0+6.0V V V Input Current (Note 3)I in -10+10mA Analog Input Voltage (Note 4)V IN GND-0.7VA+0.7V Digital Input Voltage(Note 4)V IND-0.7VL+0.7VAmbient Operating Temperature (Power Applied)T A-50+95°CStorage TemperatureT stg-65+150°CCS5341ANALOG CHARACTERISTICS - COMMERCIAL GRADETest Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.5.Referred to the typical full-scale input voltageDynamic Performance for Commercial Grade VA = 5 V VA = 3.3 VSingle-Speed Mode Fs = 48kHzSymbol MinTypMaxMinTypMaxUnitDynamic RangeA-weighted unweighted 9996105102--969310299--dB dBTotal Harmonic Distortion + Noise(Note 5) -1dB -20dB -60dBTHD+N----98-82-42-92------95-79-39-89--dB dB dBDouble-Speed Mode Fs = 96kHzSymbol MinTypMaxMinTypMaxUnitDynamic RangeA-weighted unweighted40kHz bandwidth unweighted 9996-10510299---9693-1029996---dB dB dBTotal Harmonic Distortion + Noise (Note 5) -1dB -20dB -60dB40kHz bandwidth -1dBTHD+N-----98-82-42-95-92--------95-79-39-87-89---dB dB dB dBQuad-Speed Mode Fs = 192kHzSymbol MinTypMaxMinTypMaxUnitDynamic RangeA-weighted unweighted40kHz bandwidth unweighted 9996-10510299---9693-1029996---dB dB dBTotal Harmonic Distortion + Noise (Note 5) -1dB -20dB -60dB40kHz bandwidth -1dBTHD+N-----98-82-42-95-92--------95-79-39-87-89---dB dB dB dBDynamic Performance All ModesMinTypMaxUnitInterchannel Isolation-90-dBDC AccuracyInterchannel Gain Mismatch -0.1-dB Gain Error -5-+5%Gain Drift-±100-ppm/°CAnalog Input CharacteristicsFull-Scale Input Voltage 0.53*VA0.56*VA 0.59*VAVppInput Impedance-25-k ΩCS5341ANALOG CHARACTERISTICS - AUTOMOTIVE GRADETest Conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz.6.Referred to the typical full-scale input voltageDynamic Performance for Automotive Grade VA = 5 V VA = 3.3 VSingle-Speed Mode Fs = 48kHzSymbol MinTypMaxMinTypMaxUnitDynamic RangeA-weighted unweighted 9794105102--949110299--dB dBTotal Harmonic Distortion + Noise(Note 6) -1dB -20dB -60dBTHD+N----98-82-42-90------95-79-39-87--dB dB dBDouble-Speed Mode Fs = 96kHzSymbol MinTypMaxMinTypMaxUnitDynamic RangeA-weighted unweighted40kHz bandwidth unweighted 9794-10510299---9491-1029996---dB dB dBTotal Harmonic Distortion + Noise (Note 6) -1dB -20dB -60dB40kHz bandwidth -1dBTHD+N-----98-82-42-95-90--------95-79-39-87-87---dB dB dB dBQuad-Speed Mode Fs = 192kHzSymbol MinTypMaxMinTypMaxUnitDynamic RangeA-weighted unweighted40kHz bandwidth unweighted 9794-10510299---9491-1029996---dB dB dBTotal Harmonic Distortion + Noise (Note 6) -1dB -20dB -60dB40kHz bandwidth -1dBTHD+N-----98-82-42-95-90--------95-79-39-87-87---dB dB dB dBDynamic Performance All ModesMinTypMaxUnitInterchannel Isolation-90-dBDC AccuracyInterchannel Gain Mismatch -0.1-dB Gain Error -10-+10%Gain Drift-±100-ppm/°CAnalog Input CharacteristicsFull-Scale Input Voltage 0.50*VA0.56*VA 0.62*VAVppInput Impedance-25-k ΩCS5341DIGITAL FILTER CHARACTERISTICS7.Filter characteristics scale precisely with Fs8.Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.ParameterSymbol Min Typ Max UnitSingle-Speed ModePassband (-0.1 dB)(Note 7)0-0.4895Fs Passband Ripple -0.035-0.035dB Stopband(Note 7)0.5687--Fs Stopband Attenuation70--dB Total Group Delay (Fs = Output Sample Rate)t gd-12/Fs -s Double-Speed ModePassband (-0.1 dB)(Note 7)0-0.4895Fs Passband Ripple -0.025-0.025dB Stopband(Note 7)0.5604--Fs Stopband Attenuation69--dB Total Group Delay (Fs = Output Sample Rate)t gd-9/Fs -s Quad-Speed ModePassband (-0.1 dB)(Note 7)0-0.2604Fs Passband Ripple -0.025-0.025dB Stopband(Note 7)0.5--Fs Stopband Attenuation60--dB Total Group Delay (Fs = Output Sample Rate)t gd-5/Fs -s High-Pass Filter CharacteristicsFrequency Response -3.0 dB -0.13 dB (Note 8)-120--Hz Hz Phase Deviation @ 20Hz(Note 8)-10-Deg Passband Ripple--0dBFigure 1. Single-Speed Mode Stopband Rejection Figure 2. Single-Speed Mode Stopband RejectionFigure 5. Double-Speed Mode Stopband Rejection Figure 6. Double-Speed Mode Stopband RejectionCS5341Figure 7. Double-Speed Mode Transition Band (Detail)Figure 8. Double-Speed Mode Passband RippleFigure 9. Quad-Speed Mode Stopband Rejection Figure 10. Quad-Speed Mode Stopband RejectionFigure 11. Quad-Speed Mode Transition Band (Detail)Figure 12. Quad-Speed Mode Passband RippleCS5341DC ELECTRICAL CHARACTERISTICS(GND = 0V, all voltages with respect to 0V. MCLK=12.288MHz; Master Mode)9.Power-Down Mode is defined as RST = Low, with all clocks and data lines held static at a valid logiclevels.10.Valid with the recommended capacitor values on FILT+ and VQ as shown in the Typical ConnectionDiagram.DIGITAL CHARACTERISTICSParameterSymbolMinTypMaxUnitDC Power Supplies:Positive Analog Positive DigitalPositive LogicVA VD VL 3.13.11.7--- 5.255.255.25V V V Power Supply CurrentVA = 5 V (Normal Operation)VA = 3.3 V VL,VD = 5V VL,VD = 3.3VI A I A I D I D ----2118.215925.522.518.510mA mA mA mA Power Supply CurrentVA = 5V (Power-Down Mode) (Note 9)VL,VD=5VI A I D -- 1.50.4--mA mA Power Consumption VL, VD, VA = 5V (Normal Operation)VL, VD, VA = 3.3V (Power-Down Mode)------180909.5220107.2-mW mW mW Power Supply Rejection Ratio (1kHz)(Note 10)PSRR-65-dB V Q Nominal Voltage Output Impedance--VA ÷225--V k ΩFilt+ Nominal Voltage Output ImpedanceMaximum allowable DC current source/sink---VA 360.01---V k ΩmAParameterSymbolMinTypMaxUnitsHigh-Level Input Voltage (% of VL)V IH 70%--V Low-Level Input Voltage(% of VL)V IL --30%V High-Level Output Voltage at I o = 100µA (% of VL)V OH 70%--V Low-Level Output Voltage at I o =100µA (% of VL)V OL --15%V Input Leakage CurrentI in-10-+10µACS5341SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT(Logic "0" = GND = 0V; Logic "1" = VL, C L = 20pF)11. For a description of speed modes, please refer to Table 1 on page 15.Parameter Symbol Min Typ Max UnitMCLK SpecificationsMCLK Periodt clkw39-45ns 78-1953ns MCLK Pulse Duty Cycle40-60%Master ModeSCLK falling to LRCKSingle-Speed t mslr-20-20ns Double-Speed -20-20ns Quad-Speed-8-8ns SCLK falling to SDOUT valid. t sdo--32ns SCLK Duty Cycle.Single-Speed -50-%Double-Speed -50-%Quad-Speed-33-%Slave ModeSingle-Speed (Note 11)LRCK Duty Cycle 405060%SCLK Period t sclkw156--ns SCLK Duty Cycle455055%SDOUT valid before SCLK rising t stp 10--ns SDOUT valid after SCLK rising t hld 5--ns SCLK falling to LRCK edget slrd -20-20ns Double-Speed (Note 11)LRCK Duty Cycle 405060%SCLK Period t sclkw156--ns SCLK Duty Cycle455055%SDOUT valid before SCLK rising t stp 10--ns SDOUT valid after SCLK rising t hld 5--ns SCLK falling to LRCK edge.t slrd-20-20ns Quad-Speed (Note 11)LRCK Duty Cycle 405060%SCLK Period t sclkw78--ns SCLK Duty Cycle29.73350%SDOUT valid before SCLK rising t stp 10--ns SDOUT valid after SCLK rising t hld 5--ns SCLK falling to LRCK edge.t slrd-8-8nsCS5341Figure 13. Master Mode, Left-Justified SAI Figure 14. Slave Mode, Left-Justified SAIFigure 15. Master Mode, I²S SAI Figure 16. Slave Mode, I²S SAICS5341 2.PIN DESCRIPTIONPin Name#Pin DescriptionM0 M1116Mode Selection (Input) - Determines the operational mode of the device.MCLK2Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. VL3Logic Power (Input) - Positive power for the digital input/output.SDOUT4Serial Audio Data Output (Output) - Output for two’s complement serial audio data. GND5,14Ground (Input) - Ground reference. Must be connected to analog ground.VD6Digital Power (Input) - Positive power supply for the digital section.SCLK7Serial Clock (Input/Output) - Serial clock for the serial audio interface.LRCK8Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio data line.RST9Reset (Input) - The device enters a low power mode when low.AINL AINR 1012Analog Input (Input) - The full-scale analog input level is specified in the Analog Charac-teristics specification table.VQ11Quiescent Voltage (Output) - Filter connection for the internal quiescent reference voltage.VA13Analog Power (Input) - Positive power supply for the analog section.FILT+15Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.M0M1MCLK FILT+VL REF_GNDSDOUT VAGND AINRVD VQSCLK AINLLRCK RST11634785261514131211109CS5341 3.TYPICAL CONNECTION DIAGRAMCS53414.APPLICATIONS4.1Single-, Double-, and Quad-Speed ModesThe CS5341 can support output sample rates from 2kHz to 200kHz. The proper speed mode can be de-termined by the desired output sample rate and the external MCLK/LRCK ratio, as shown in Table 1.Table 1. Speed Modes and the Associated Output Sample Rates (Fs)4.2Operation as Either a Clock Master or SlaveThe CS5341 supports operation as either a clock master or slave. As a clock master, the LRCK and SCLK pins are outputs with the left/right and serial clocks synchronously generated on-chip. As a clock slave, the LRCK and SCLK pins are inputs and require the left/right and serial clocks to be externally generated. The selection of clock master or slave is made via the Mode pins as shown in Table 2.Speed ModeMCLK/LRCKRatioOutput Sample Rate Range (kHz)Single-Speed Mode 512x 43 - 50256x 2 - 50Double-Speed Mode 256x 86 - 100128x 50 - 100Quad-Speed Mode128x 172 - 20064x*100 - 200* Quad-Speed Mode, 64x only available in Master Mode.M1 (Pin 16)M0 (Pin 1)MODE00Clock Master, Single-Speed Mode 01Clock Master, Double-Speed Mode 10Clock Master, Quad-Speed Mode 11Clock Slave, All Speed ModesTable 2. CS5341 Mode ControlCS53414.2.1Operation as a Clock MasterAs a clock master, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally de-rived from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 18.4.2.2Operation as a Clock Slave with Auto-DetectLRCK and SCLK operate as inputs in clock Slave Mode. It is recommended that the left/right clock be synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance.A unique feature of the CS5341 is the automatic selection of either Single-, Double- or Quad-Speed Mode when operating as a clock slave. The auto-mode select feature negates the need to configure the Mode pins to correspond to the desired mode. The auto-mode selection feature supports all standard audio sample rates from 2 to 200kHz. However, there are ranges of non-standard audio sample rates that are not supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed Modes, respectively). Please refer to Table 1 for supported sample rate ranges.Figure 18. CS5341 Master Mode ClockingCS53414.2.3Master ClockThe CS5341 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.There is also an internal MCLK divider which is automatically activated based on the speed mode and frequency of the MCLK. Table 3 shows a listing of the external MCLK/LRCK ratios that are required.Table 4 lists some common audio output sample rates and the required MCLK frequency. Please note that not all of the listed sample rates are supported when operating with a fast MCLK (512x, 256x, 128x for Single-, Double-, and Quad-Speed Modes, respectively).4.3Serial Audio InterfaceThe CS5341 supports both I²S and Left-Justified serial audio formats. Upon start-up, the CS5341 will detect the logic level on SDOUT (pin 4). A 10 k Ω pull-up to VL is needed to select I²S format, and a 10 k Ω pull-down to GND is needed to select Left-Justified format. Figures 19 and 20 illustrate the I²S and Left-Justified audio formats. Please see Figures 13 through 16, for more information on the required timing for the two serial audio interface formats. Also see Application Note AN282 for a detailed discussion of the serial audioSingle-Speed ModeDouble-Speed ModeQuad-Speed ModeMCLK/LRCK Ratio256x, 512x128x, 256x64x*,128x* Quad Speed, 64x only available in Master Mode.Table 3. Master Clock (MCLK) RatiosSAMPLE RATE (kHz)MCLK (MHz)328.192 44.111.289622.57924812.28824.576648.19288.211.289622.57929612.28824.57619212.28824.576Table 4. Master Clock (MCLK) Frequencies for Standard Audio Sample RatesCS5341 4.4Power-Up SequenceReliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks andconfiguration pins are stable. It is also recommended that reset be enabled if the analog or digital suppliesdrop below the minimum specified operating voltages to prevent power-glitch-related issues.4.5Analog ConnectionsThe analog modulator samples the input at half of the MCLK frequency, or nominally 6.144MHz. The digitalfilter will reject signals within the stopband of the filter. However, there is no rejection for input signals whichare multiples of the input sampling frequency (n×6.144MHz), where n=0,1,2,... Refer to Figure21, which shows the suggested filter that will attenuate any noise energy at 6.144MHz in addition to providing the op-timum source impedance for the modulators. The use of capacitors that have a large voltage coefficient(such as general-purpose ceramics) must be avoided since these can degrade signal linearity. Array4.6Grounding and Power Supply DecouplingAs with any high resolution converter, achieving optimal performance from the CS5341 requires careful at-tention to power supply and grounding arrangements. Figure17 shows the recommended power arrange-ments, with VA and VL connected to clean supplies. VD, which powers the digital filter, may be run from thesystem logic supply or may be powered from the analog supply via a resistor. In this case, no additionaldevices should be powered from VD. Decoupling capacitors should be as near to the ADC as possible, withthe low-value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away fromthe FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decou-pling capacitors, particularly the 0.01µF, must be positioned to minimize the electrical path from FILT+ andREF_GND. Furthermore, all ground pins on CS5341 should be referenced to the same ground reference.The CDB5341 evaluation board demonstrates the optimum layout and power supply arrangements. To min-imize digital noise, connect the ADC digital outputs only to CMOS inputs.4.7Synchronization of Multiple DevicesIn systems where multiple ADCs are required, the user can achieve simultaneous sampling if the MCLK andLRCK signals are the same for all of the CS5341’s in the system. If only one master clock source is needed,one solution is to place one CS5341 in Master Mode, and slave all of the other CS5341’s to the one master.If multiple master clock sources are needed, a possible solution would be to supply all clocks from the sameexternal source and time the CS5341 reset with the inactive (falling) edge of MCLK. This will ensure that allconverters begin sampling on the same clock edge.CS53414.8Capacitor Size on the Reference Pin (FILT+)The CS5341 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in Figure 22, with larger capacitor values used to optimize low frequency distortion performance. This plot was taken using the CDB5341 evaluation platform, with the device running in Single-Speed Mode and VA=VD=VL=5 V.Figure 22. CS5341 THD+N versus Frequency47 uF100 uF22 uF10 uF6.8 uF4.7 uF3.3 uF2.2 uF1 uF5.6 uFCS5341 5.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made witha -60dBFS signal. 60dB is added to resulting measurement to refer the measurement to full-scale. Thistechnique ensures that the distortion components are below the noise level and do not affect the measure-ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.Total Harmonic Distortion + NoiseThe ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels. Measured at -1 and -20dBFS as suggested in AES17-1991 Annex A.Frequency ResponseA measure of the amplitude response variation from 10Hz to 20kHz relative to the amplitude response at1kHz. Units in decibels.Interchannel IsolationA measure of crosstalk between the left and right channels. Measured for each channel at the converter'soutput with no signal to the input under test and a full-scale signal applied to the other channel. Units in deci-bels.Interchannel Gain MismatchThe gain difference between left and right channels. Units in decibels.Gain ErrorThe deviation from the nominal full-scale analog input for a full-scale digital output.Gain DriftThe change in gain value with temperature. Units in ppm/°C.Offset ErrorThe deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.DS564F121CS53416.PACKAGE DIMENSIONS1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include moldmismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm per side.2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be0.13mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-duce dimension “b” by more than 0.07mm at least material condition.3.These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips.THERMAL CHARACTERISTICSINCHES MILLIMETERSNOTEDIM MIN NOM MAX MIN NOM MAX A ----0.043---- 1.10A10.0020.0040.0060.05--0.15A20.033460.03540.0370.850.900.95b 0.007480.00960.0120.190.2450.302,3D 0.1930.19690.201 4.90 5.00 5.101E 0.2480.25190.256 6.30 6.40 6.50E10.1690.17320.177 4.30 4.40 4.501e --0.026 BSC ----0.65 BSC --L 0.0200.0240.0280.500.600.70µ0°4°8°0°4°8°JEDEC #: MO-153Controlling Dimension is MillimetersParameterSymbol MinTypMaxUnit Allowable Junction Temperature --135°C Junction to Ambient Thermal ImpedanceθJA-75-°C/W16L TSSOP (4.4mm BODY) PACKAGE DRAWINGEN123eb 2A1A2ADSEATING PLANE E11LSIDE VIEWEND VIEWTOP VIEW∝22DS564F1CS53417.ORDERING INFORMATION8.REVISION HISTORYProductDescription Package Pb-Free Grade Temp Range ContainerOrder #CS5341105 dB, 192 kHz, Multi-BitAudio A/D Converter 16-TSSOP YES Commercial -10° to +70° CBulk CS5341-CZZ Tape & ReelCS5341-CZZR CS5341105 dB, 192 kHz, Multi-BitAudio A/D Converter 16-TSSOP YES Automotive -40° to +85° CBulk CS5341-DZZ Tape & ReelCS5341-DZZR CDB5341 CS5341 Evaluation Board -----CDB5341ReleaseChangesA1Initial Advance releaseA2Updated serial port timing specificationsPP1Change value of capacitors in analog input buffer diagram Update Sample Rate rangeAdded Applications section on FILT+ filter capacitor Add CS5341-CZZ as part numberReplace available part number CS5341-DZ with CS5341-DZZ Initial Preliminary product releasePP2Add lead-free option to ordering information F1Remove CS5341-CZ from Ordering InformationRedefine Serial Audio Port Switching Characteristics Correct dimension “e” under Package Dimensions Update maximum current and power specifications Update Filt+ output impedance specificationContacting Cirrus Logic SupportFor all product questions and inquiries, contact a Cirrus Logic Sales Representative. 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