Mixed-Signal Digital Storage Oscilloscope

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FA 7.4: A 0.4W Mixed-Signal Digital Storage Oscilloscope Processor with Moire Prevention, Embedded 393kb RAM and 50MSamplels 8b ADC

M. Vertregt’, W. Rey’, M. Boonen2, J. Verhaegh2, W. Wiertsema2

’Philips Research Laboratories, Eindhoven, The Netherlands 2Philips Semiconductors ASG Microtel, Eindhoven, The Netherlands

On a digital storage oscilloscope display, confusing Moire patterns are commonly created by interference of an input signal with the bitmap to which this signal is rendered. The timebase used to zoom through eight decades of selectable time windows aggravates this effect. This dedicated real-time Stochastic Allocation algorithm, realized on silicon, prevents Moire patterns. A previous single- chip oscilloscope implementation focuses on the analog signal conditioning [l] . This low-power, mixed-signal, one-chip-sys- tem digital storage oscilloscope processor (DSOP) performs data acquisition and image rasterizing. For enhanced display confidence, the image processing features a maximum update rate of 50k waveforms (13M-Pixels) per secondinto the embedded screenmemory bit map, typical ofbenchtop equipment solutions [2,3]. The DSOP read-out is at VGA-type 6OFrameds.

The architecture of the DSOP is shown in Figure 1. Its only inputs are an analog signal (conditioned to fit the range of the AID

converter), a trigger pulse and a system clock (50MHz). The output consists of 5 wires: a two bit intensity data bus, a 6.25MHz pixel clock, a line sync and a frame sync. The ADC, a partially pipe-lined derivative of the module presented in Reference 4, runs up to 50MSample/s. The time transformation from input to output is handled in three steps through embedded memory buffers. In this way, the various signal processing tasks on either side ofthe buffer are decoupled. This increases the overall datapath throughput. The sampleddataisfirststoredinanon-chipacquisitionRAM(max. 16k

points), implemented as a double buffer. The image processor treats the points storedin the complementary buffer that was filled during the previous waveform acquisition.

Figure 2 illustrates the stochastic allocation method. Pixel bright- ness is stochastically rendered into either of two adjacent bitmap columns (conventional methods accumulate pixel brightness into a single bitmap column). The X (or time) position of a physical or interpolated sample within the actual bitmap column is used as the probabilitylevel to decide whether a hit occurs in either column-i or column-i+l. Suppose a sample has a position 60% away from the previous columnboundaryand40%from thenext. Apseudo-random selection method then creates a 60% chance to accumulate bright- ness in a pixel of the next column and a 40% chance to accumulate brightness in the current column. By manipulating the bitmap in this way the systematic relationship between the input signal and the fixed screen raster (causing the Moire interference) is broken. The high-throughput architecture superimposes many sampled waveforms per display cycle. This provides abundant stochastic allocations per active pixel ofthe displayedwaveform. In Figure 3a, where standard accumulation is applied, the Moire patterns are noticeable. In Figure 3b, these confusing patterns are not generated. The bitmap columns are implemented as

SRAM

memories (a triple buffer configuration with 256xl2b each). Not data, only a pointer moves from buffer to buffer. High-through- put for recombination with column-i-1 of the screen RAM justifies the third buffer. Image processing uses the brightness as a third dimension to enhance display quality. Pixel brightness is proportional to the sample-to-sample amplitude step. Filter-

ing the sequence of pixel brightness and step values yields

control variables for two recursive, adaptive, algorithms: one for automatic brightness scaling and one for image recombina- tion [5]. This assures visibility of superimposed waveforms in a bitmap with minimal brightness range. The complete screen RAM 256x256 bitmap works with 2b-per-pixel and is embedded.

The display controller governs the read-out of the screen RAM at a

fxed clock rate over the full eight decades of timebase

settings. Decremented brightness write-back can be turned ON and OFF under 12C control.

The coverage of acquisition time to physical time is 100% for timebase settings from 50s/DIV down to 200ps/DIV. Towards the fastest 5OOns/DIV setting, the coverage decreases to 25% (a