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MT9V113: Outgoing Defect SpecificationIntroduction

PDF:3861480893/Source:7453158224Aptina reserves the right to change products or specifications without notice.MT9V113_ODS-Rev. F Pub. 11/10 EN1©2007 Aptina Imaging Corporation. All rights reserved.Aptina Confidential and Proprietary

Outgoing Defect Specification

MT9V113

IntroductionThis document defines outgoing defect specifications (preliminary) for the Aptina MT9V113 image sensor. The sensor defect regions, as well as types of pixel and cluster defects, are defined.

Sensor DefectsThe sensor array is partitioned into two regions: Region I and Region II. These dimen-sions are defined in Figure 1.Figure 1: Sensor Array

Region II

Region I

40pixels40pixels

40 pixels40 pixels

480 pixels640 pixels MT9V113: Outgoing Defect SpecificationDefect Specifications

PDF:3861480893/Source:7453158224Aptina reserves the right to change products or specifications without notice.MT9V113_ODS-Rev. F Pub. 11/10 EN2©2007 Aptina Imaging Corporation. All rights reserved.Aptina Confidential and Proprietary

Defect SpecificationsTable1 and Table2 specify the maximum number of defects for each of the regions defined in Figure1 on page1.

Note:Image sensor is tested without a lens. Multiple images captured and analyzed in Bayer format. Setup: VAA=VAA_PIX=VDD_PLL = 2.8V, VDD= VDD_IO = 1.8V.

Note:Image sensor is tested without a lens. Multiple images captured and analyzed in YCbCr format. Setup: VAA=VAA_PIX=VDD_PLL = 2.8V, VDD= VDD_IO = 1.8V.Conditions for Image Test A•Full resolution images (four frames) are captured at 15 fps in SOC bypass mode (raw Bayer format) in dark condition with no defect correction and without a lens system. Frames are averaged for analysis.•Sensor analog gain is 8x for all color planes and digital gain is 1x (unity).•The sensor is operated at maximum external clock frequency with PLL enabled.Conditions for Image Test B•Full resolution images (four frames) are captured at 30 fps in SOC bypass mode (raw Bayer format) with light condition equivalent to get 50 percent of sensor full-scale output, without a lens system. Frames are averaged for analysis.•Sensor analog gain is 1x for all color planes and digital gain is 1x (unity).•The sensor is operated at maximum external clock frequency with PLL enabled.Table 1: Defect Specification with Defect Correction Disabled (Bayer Format)Operating condition: TJ = 55°C

Defect DefinitionNumber of DefectsDefinition NumberRegion IRegion IIVery hot, very bright, or very dark pixel defectsTotal ≤ 20Total ≤ 65Total ≤ 101, 3, 5Hot or bright pixel defects2, 4Dark pixel defects6Bright clusters07Dark clusters08

Table 2: Defect Specification with Defect Correction Enabled (YCbCr Format)Operating condition: TJ = 55°C

Defect DefinitionNumber of DefectsDefinition NumberRegion IRegion IIBright pixel defects09, 14Dark pixel defects010, 15Bright clusters011Dark clusters012Row or column defects013 MT9V113: Outgoing Defect SpecificationDefect Specifications

PDF:3861480893/Source:7453158224Aptina reserves the right to change products or specifications without notice.MT9V113_ODS-Rev. F Pub. 11/10 EN3©2007 Aptina Imaging Corporation. All rights reserved.Aptina Confidential and Proprietary

Conditions for Image Test C•Full resolution images (four frames) are captured at 5 fps in SOC YCbCr mode with 1.5 lux incident light with defect correction enabled and without a lens system. Frames are averaged for analysis.•Sensor analog gain is 16x for blue color plane and all digital gain is 1x (unity). ADC reference and gamma are set to default conditions.•The sensor is operated at maximum external clock frequency with PLL enabled.Conditions for Image Test D•Full resolution images (4 frames) are captured at 7.5 fps in SOC YCbCr mode with 1.5 lux incident light, without a lens system. Frames are averaged for analysis.•Sensor analog gain is 8X for blue color plane and all digital gains are unity. ADC refer-ence and gamma are set to default conditions.•The sensor is operated at maximum external clock frequency with PLL enabled. MT9V113: Outgoing Defect SpecificationCluster Defects

PDF:3861480893/Source:7453158224Aptina reserves the right to change products or specifications without notice.MT9V113_ODS-Rev. F Pub. 11/10 EN4©2007 Aptina Imaging Corporation. All rights reserved.Aptina Confidential and Proprietary

Cluster DefectsFigure2 and Figure3 represent the same sub-area of pixels. Figure2 represents the raw Bayer pixel output form. Figure3 represents the pixel output separated by color plane. Clusters are analyzed by looking at one particular pixel and its surrounding eight adja-cent pixels within the same color plane, as seen in Figure3. For example, if the center pixel is a dark pixel and any of its surrounding eight pixels within the same color plane are dark pixels then it is defined as a dark cluster.Figure 2: Raw Pixel Data

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Electrical Specifications – AC Characteristics and Operating Conditions(Asynchronous)Table 41: AC Characteristics: Asynchronous Command, Address, and DataParameterSymbolMode 0Mode 1Mode 2Mode 3Mode 4Mode 5UnitNotesMinMaxMinMaxMinMaxMinMaxMinMaxMinMaxClock period1005035302520nsFrequency≈10≈20≈28≈33≈40≈50MHzALE to data starttADL200–100–100–100–70–70–ns1ALE hold timetALH20–10–10–5–5–5–nsALE setup timetALS50–25–15–10–10–10–nsALE to RE# delaytAR25–10–10–10–10–10–nsCE# access timetCEA–100–45–30–25–25–25nsCE# hold timetCH20–10–10–5–5–5–nsCE# HIGH to outputHigh-ZtCHZ–100–50–50–50–30–30ns2CLE hold timetCLH20–10–10–5–5–5–nsCLE to RE# delaytCLR20–10–10–10–10–10–nsCLE setup timetCLS50–25–15–10–10–10–nsCE# HIGH to outputholdtCOH0–15–15–15–15–15–nsCE# setup timetCS70–35–25–25–20–15–nsData hold timetDH20–10–5–5–5–5–nsData setup timetDS40–20–15–10–10–7–nsOutput High-Z toRE# LOWtIR10–0–0–0–0–0–nsRE# cycle timetRC100–50–35–30–25–20–nsRE# access timetREA–40–30–25–20–20–16ns3RE# HIGH hold timetREH30–15–15–10–10–7–ns3RE# HIGH to outputholdtRHOH0–15–15–15–15–15–ns3RE# HIGH to WE#LOWtRHW200–100–100–100–100–100–nsRE# HIGH to outputHigh-ZtRHZ–200–100–100–100–100–100ns2, 3RE# LOW to outputholdtRLOH0–0–0–0–5–5–ns3RE# pulse widthtRP50–25–17–15–12–10–nsReady to RE# LOWtRR40–20–20–20–20–20–nsWE# HIGH toR/B# LOWtWB–200–100–100–100–100–100ns4WE# cycle timetWC100–45–35–30–25–20–ns32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NANDElectrical Specifications – AC Characteristics and OperatingConditions (Asynchronous)Figure 36: Synchronous Address CycleCLKALECLEDQSDQ[7:0]tCKLtCALHtCALStCALHtCALS