Chronologic_Whitepaper

GlobleCurrency：新型数字资产质流通系统

摘要：比特币证明了点对点电子货币系统的可行性，以太坊建立了基于智能合约

的去中心化应用平台，目前多种公链以及私有链、联盟链的大量共存，形成了数

据和价值的孤岛。GlobleCurrency通过动态同步索引侧链实现跨链资产映射及交

换。

1.简介

GlobleCurrency（以下简称GC）是一种通过动态索引同步侧链实现跨链资产映射

及交换的系统，所有业务均以智能合约侧链的方式与父级链通过动态索引实现交

互。

2.动态索引

主链与侧链直接通过主链的Merkle树交互，主链对不同侧链链的索引会使用不同的索引策略，通常会在侧链区块基本可以确认不是孤块之后进行索引。

3.树形侧链

通过GC的主侧链架构，以GC为主链，GC的侧链可以成为自身侧链的主链，因此理论上系统可以映射所有链上数字资产并能够通过智能合约无限扩展数字资产业务。

4.代币产出

为致敬BTC，GC的理论总产出数量被设定为allGC=21,000,000枚，与BTC总量相

等，GC地址生成算法也与BTC相同。

GC的产出方式有两种，BTC层级置换及算力产出。

BTC层级置换即使用BTC按照层级置换比例换取GC，该方式产出GC总量为

7,000,000枚，BTC层级置换保证了GC的价值与BTC的对应关系，层级的增加对

应了GC以BTC计价的升值，当置换产出GC数量达到7,000,000枚或者层级置换

停留在某一层级并维持30天，层级置换停止，即GC的BTC层级置换产出方式

结束，此时如果置换GC数量不足7,000,000枚，则剩余部分GC销毁，GC理论

总产出数量将不足21,000,000枚。

第i层的BTC容量

)26,2min(1iBTCii

第i层BTC置换GC比例

)055.1,)2(055.02max(/(round21iRatioRatioii

1000001Ratio

即第1层初始置换比例为1BTC：100000GC。算力的产生有两种方式，一是锁定GC或BTC产生算力，锁定GC产生的算力适

SP601 Hardware

User Guide

UG518 (v1.7) September 26, 2012SP601 Hardware User

UG518 (v1.7) September 26, 2012© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.DISCLAIMERThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at /warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: /warranty.htm#critapps.

High-Level Synthesis Tools for Xilinx FPGAs

©

2010 BDTI (). All rights reserved.An Independent Evaluation of:Berkeley Design Technology, IncBy the staff ofExecutive SummaryIn 2009, Berkeley Design Technology Inc.(BDTI), an independent benchmarking and analysisfirm, launched the BDTI High-Level Synthesis ToolCertification Program™ to evaluate high-level syn-thesis tools for FPGAs. Such tools take as their inputa high-level representation of an application (writtenin C or MATLAB, for example) and generate a regis-ter-transfer-level (RTL) implementation for anFPGA. Thus far, two high-level synthesis tools,AutoESL’s AutoPilot and Synfora’s PICO, havebeen certified under the program. BDTI’s evaluation program uses two exampleapplications, a video motion analysis application anda wireless receiver, to evaluate high-level synthesistools (HLSTs) on a number of quantitative and qual-itative metrics. As shown in Figure1 and Figure2,we found that the Xilinx Spartan-3A DSP 3400FPGA used with either of the two HLSTs providedroughly 40X better performance than a mainstreamDSP processor, and that the high-level synthesis toolswere able to achieve FPGA resource utilization levelscomparable to hand-written RTL code. Furthermore,as we will discuss in this white paper, implementingour video application using the HLSTs along withXilinx FPGA tools required a similar level of effort asthat required for the DSP processor. This finding willno doubt be surprising to many, as FPGAs have his-torically required much more development time thanDSPs.Based on our analysis, we believe that HLSTs cansignificantly increase the productivity of currentFPGA users. For those using DSP processors inhighly demanding applications, we believe thatFIGURE 1. Maximum frame rate achieved (at 720p resolution)on the BDTI Optical Flow Workload (a video application) on aDSP processor and a Spartan-3A DSP FPGA using HLSTs.Performance (Frames/Second) 4PrcHigher is Better5.1195050100150200250DSPHLST + FPGA0x erfomaneFIGURE 2. FPGA resource utilization on the BDTI DQPSKWorkload (a wireless receiver) implemented using HLSTs(average result) versus hand-written RTL code.FPGA UtilizationLower is Better5.9%5.9%0.0%1.0%2.0%3.0%4.0%5.0%6.0%7.0%RTLHLSTCERTIFIEDPage 2©

Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter

AD9122

Rev. A Information furnished by Analresponsibility is assumed by Anarights of third parties that may relicense is granted by implicationTrademarks and registered trad MA 02062-9106, Inc. All rights reserved.

NOTES1. AQM = ANALOG QUADRATURE MODULATOR.

og Devices is believed to be accurate and reliable. However, no log Devices for its use, nor for any infringements of patents or other sult from its use. Specifications subject to change without notice. No or otherwise under any patent or patent rights of Analog Devices. emarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood,Tel: 781.329.4700 Fax: 781.461.3113 ©2010 Analog Devices,FEATURES

Flexible LVDS interface allows word, byte, or nibble load