SH79F166A CV2.1中文资料

The VC707 board uses power regulators and PMBus compliant digital PWM system controllersfrom Texas Instruments to supply the core and auxiliary voltages listed in Table1-29.Table 1-29:Onboard Power System DevicesDevice Type ReferenceDesignatorDescriptionPower RailNet NamePower RailVoltageSchematicPageCore voltage controller and regulatorsUCD9248PFC(1)U42PMBus Controller (Addr=52)46PTD08A020WU25Adjustable switching regulator20A, 0.6V to 3.6VVCCINT_FPGA 1.00V47PTD08D210W(V OUT A)U20Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCCAUX 1.80V48PTD08D210W (V OUT B)Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCC3V3 3.30V48PTD08A010WU12Adjustable switching regulator10A, 0.6V to 3.6VVCC_ADJ0-3.30V49Auxiliary voltage controller and regulatorsUCD9248PFC(2)U43PMBus Controller(Addr=53)50PTD08D210W(V OUT A)U21Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCC2V5_FPGA 2.50V51PTD08D210W (V OUT B)Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCC1V5_FPGA 1.50V51PTD08D210W(V OUT A)U22Adjustable switching regulatordual 10A, 0.6Vto 3.6VMGTA VCC 1.00V52PTD08D210W (V OUT B)Adjustable switching regulatordual 10A, 0.6Vto 3.6VMGTA VTT 1.20V52UCD9248PFC(3)U64PMBus Controller(Addr=54)53PTD08D210W(V OUT A)U62Dual 10A 0.6V - 3.6V Adj. Switching Regulator VCCAUX_IO 2.00V54PTD08D210W(V OUT B)Dual 10A 0.6V - 3.6V Adj. Switching Regulator VCCBRAM 1.00V54PTD08D210W(V OUT A)U63Dual 10A 0.6V - 3.6V Adj. Switching Regulator MGTVCCAUX 1.80V55PTD08D021W(V OUT B)Dual 10A 0.6V - 3.6V Adj. Switching Regulator VCCBRAM 1.00V55 Linear regulatorsLMZ12002U71Fixed Linear Regulator 2A VCC5V0 5.00V46 TL1962ADC U62Fixed Linear Regulator, 1.5A VCC1V8 1.80V46 ADP123U17Fixed Linear Regulator, 300mA VCC_SPI 2.80V46 ADP123U18Fixed Linear Regulator, 300mA XADC_VCC 1.80V31Feature DescriptionsData sheets for the Texas Instruments controller and regulators are available at the Texas Instruments website [Ref 25], and for the Analog Devices ADP123 at [Ref 26].FMC_VADJ Voltage ControlThe FMC_V ADJ rail is set to 1.8V . When the VC707 board is powered on, the state of theFMC_V ADJ_ON_B signal wired to header J51 is sampled by the TI UCD9248 controller U42. If a jumper is installed on J51 signal FMC_V ADJ_ON_B is held low, and the TI controller U42 energizes the FMC_V ADJ rail at power on.Because the rail turn on decision is made at power on time based on the presence of the J51 jumper, removing the jumper at J51 after the board is powered up does not affect the 1.8V power delivered to the FMC_V ADJ rail and it remains on.A jumper installed at J51 is the default setting.If a jumper is not installed on J51, signal FMC_V ADJ_ON_B is high, and the VC707 board does not energize the FMC_V ADJ 1.8V at power on. In this mode the user can control when to turn on FMC_V ADJ and to what voltage level (1.2V , 1.5V , 1.8V). With FMC_V ADJ off, the FPGA still configures and has access to the TI controller PMBUS along with the V ADJ_ON_B signal. The combination of these allows the user to develop code to command the FMC_V ADJ rail to be set to something other than the default setting of 1.8V . After the new FMC_V ADJ voltage level has been programmed into TI controller U42, the V ADJ_ON_B signal can be driven low by the user logic and the FMC_V ADJ rail comes up at the new FMC_V ADJ voltage level. Installing a jumper at J51 after a VC707 board powers up in this mode turns on the FMC_V ADJ rail.Documentation describing PMBUS programming for the UCD9248 digital power controller is available at the Texas Instruments website [Ref 25].Monitoring Voltage and CurrentV oltage and current monitoring and control are available for selected power rails through Texas Instruments' Fusion Digital Power graphical user interface. The three onboard TI power controllers (U42 at address 52, U43 at address 53, and U64 at address 54) are wired to the same PMBus. The PMBus connector, J5, is provided for use with the TI USB Interface Adapter PMBus pod (TI part number EVM USB-TO-GPIO), which can be ordered from the TI website [Ref 25], and the associated TI Fusion Digital Power Designer GUI (downloadable from [Ref 25]). This is thesimplest and most convenient way to monitor the voltage and current values for the power rail listed in Table 1-30, Table 1-31, and Table 1-32.In each of these the three tables (one per controller), the Power Good (PG) On Threshold is the set-point at or above which the particular rail is deemed “good”. The PG Off Threshold is theset-point at or below which the particular rail is no longer deemed “good”. The controller internally OR's these PG conditions together and drives an output PG pin high only if all active rail PG states are “good”. The On and Off Delay and rise and fall times are relative to when the board power on-off slide switch SW12 is turned on and off.TPS51200DR U33Tracking Regulator, 3AVTTDDR0.75V46Notes:1.See Table 1-30.2.See Table 1-31.3.See Table 1-34.Table 1-29:Onboard Power System Devices (Cont’d)Device TypeReference DesignatorDescriptionPower Rail Net Name Power Rail Voltage Schematic PageChapter 1:VC707 Evaluation Board FeaturesTable 1-30 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 52 (U42).Table 1-31 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 53 (U43).Table 1-30:Power Rail Specifications for UCD9248 PMBus Controller at Address 52Shutdown Threshold (1)Rail Number Rail Name Schematic Rail NameN o m i n a l V O U T (V )P G O n T h r e s h o l d (V )P G O f f T h r e s h o l d (V )O n D e l a y (m s )R i s e T i m e (m s )O f f D e l a y (m s )F a l l T i m e (m s )V O U T O v e r F a u l t (V )I O U T O v e r F a u l t (A )T e m p O v e r F a u l t (°C )1Rail #1VCCINT_FPGA 10.90.8505101 1.1520902Rail #2VCCAUX 1.8 1.62 1.530551 2.0710.41903Rail #3VCC3V3 3.3 2.97 2.8050541 3.79510.41904Rail #4V ADJ1.81.621.535312.0710.4190Notes:1.The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value is exceeded.Table 1-31:Power Rail Specifications for UCD9248 PMBus Controller at Address 53Shutdown Threshold (1)Rail Number Rail Name Schematic Rail NameN o m i n a l V O U T (V )P G O n T h r e s h o l d (V )P G O f f T h r e s h o l d (V )O n D e l a y (m s )R i s e T i m e (m s )O f f D e l a y (m s )F a l l T i m e (m s )V O U T O v e r F a u l t (V )I O U T O v e r F a u l t (A )T e m p O v e r F a u l t (°C )1Rail #1VCC2V5_FPGA 2.5 2.25 2.1250511 2.87510.41902Rail #2VCC1V5 1.5 1.35 1.2750501 1.72510.41903Rail #3MGTA VCC 10.90.850571 1.4510.41904Rail #4MGTA VTT1.21.081.025811.3810.4190Notes:1.The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut down if the value is exceeded.Feature Descriptions Table1-32 defines the voltage and current values for each power rail controlled by the UCD9248PMBus controller at address 54 (U64).Table 1-32:Power Rail Specifications for UCD9248 PMBus Controller at Address 54Shutdown Threshold(1)Rail NumberRailNameSchematicRail NameNominalVOUT(V)PGOnThreshold(V)PGOffThreshold(V)OnDelay(ms)RiseTime(ms)OffDelay(ms)FallTime(ms)VOUTOverFault(V)IOUTOverFault(A)TempOverFault(°C)1Rail #1VCCAUX_IO2 1.8 1.70521 2.310.4190 2Rail #2VCC_BRAM10.90.850591 1.1510.4190 3Rail #3MGTVCCAUX 1.8 1.62 1.530571 2.0710.4190 4Rail #4VCC1V8_FPGA 1.8 1.62 1.530551 2.0710.4190Chapter 1:VC707 Evaluation Board FeaturesConfiguration OptionsThe FPGA on the VC707 board can be configured by the following methods:•Master BPI (uses the Linear BPI Flash).•JTAG (uses the USB-to-JTAG Bridge or Download cable). See USB JTAG for more informationSee 7Series FPGAs Configuration User Guide (UG470) [Ref 3] for further details on configuration modes.The method used to configure the FPGA is controlled by the mode pin (M2, M1, M0) settings selected through DIP switch SW11. Table 1-34 lists the supported mode switch settings.Figure 1-36 shows mode switch SW13.The mode pins settings on SW11 determine if the Linear BPI Flash is used for configuring the FPGA. DIP switch SW11 also provides the upper two address bits for the Linear BPI Flash and can be used to select one of multiple stored configuration bitstreams. Figure 1-37 shows the connectivity between the onboard nonvolatile Flash devices used for configuration and the FPGA.To obtain the fastest configuration speed an external 80MHz oscillator is wired to the EMCCLK pin of the FPGA. This allows users to create bitstreams that configure the FPGA over the 16-bit datapath from the Linear BPI Flash memory at a maximum synchronous read rate of 80MHz.Table 1-34:Mode Switch SW11 SettingsMode Pins (M2, M1, M0)Configuration Mode010Master BPI 101JTAGFigure 1-36:Mode Switch。

Pin DescriptionsFunctional Block DiagramNumber Name I/O Description1FOLD O Multiplexed CMOS level output (see Programming Description section)2XIN I Reference crystal oscillator or external clock input with internally biased amplifier 3XOUT O Reference crystal oscillator output used with external resonator 4VSSA —Ground (aux PLL)5FINA I VCO frequency input with internally biased input amplifier (aux PLL)6VDDA —Nominal 3.0 V supply voltage (aux PLL)7DOA O Single-ended charge pump output (aux PLL)8ENA I Enable control input; normal operation when high, power-down mode when low (aux PLL)9ENM I Enable control input; normal operation when high, power-down mode when low (main PLL)10DOM O Single-ended charge pump output (main PLL)11VDDM —Nominal 3.0 V supply voltage (main PLL)12FINM I VCO frequency input with internally biased input amplifier (main PLL)13VSSM —Ground (main PLL)14LE I Latch enable input 15DATA I Serial data input 16CLKIShift register clock inputPFDFOLD FINM DATA CLK LE ENM CONTROL LOGICR-COUNTERSHIFT REGISTERAUX LATCH FOLDDOMFINALOCK DETECTORENAN-COUNTERMAIN LATCHN-COUNTERR-COUNTER PFDCHARGE PUMPLOCK DETECTOROSCCHARGE PUMPMAIN PRESCALERAUX PRESCALERXOUT XIN DOAMUXAbsolute Maximum RatingsV SS = 0 VRecommended Operating ConditionsV SS = 0 VParameterSymbol RatingUnit Supply voltageV DD,main V SS – 0.3 to V SS + 6.5V V DD,aux V SS – 0.3 to V SS + 6.5V Input voltage range V FIN,main V SS – 0.3 to V DD,main + 0.3V V FIN,aux V SS – 0.3 to V DD,aux + 0.3V Operating temperature range T OPR –40 to 85°C Storage temperature range T STG –40 to 125°C Soldering temperature range T SLD 255°C Soldering time ranget SLD10sParameterSymbolValueUnitmin.typ.max.Supply voltage rangeV DD,main2.73.6V V DD,auxV DD,main V DD,mainV Operating temperatureT A–402585°CElectrical Characteristics(VDD,main = VDD,aux= VDD= 3.0 V, TA= 25 °C unless otherwise noted)Parameter Symbol ConditionValueUnitmin.typ.max.GENERALCurrent consumption I DD,total 1.1 GHz + 1.1 GHz 5.0mA1.1 GHz only2.5mAStandby current consumption I DD,standby ENM = ENA = low1µAFIN operating frequency range f FINMain1001100MHz Auxiliary1001100MHzXIN operating frequency range f XIN Logic mode140MHz Crystal mode120MHzFIN input sensitivity P FINMain–150dBm Auxiliary–150dBmXIN input sensitivity V XIN0.5V DD,aux V pk-pk DIGITAL INTERFACELogic LOW input voltage V IL 0.2 ×VDDVLogic HIGH input voltage V IH 0.8 ×VDDVLogic LOW input current I IL V IL = 0 V, V DD = 3.6 V–11µA Logic HIGH input current I IH V IH = V DD = 3.6 V–11µA XIN logic LOW input current I IL,XIN V IL = 0 V, V DD = 3.6 V–100µA XIN logic HIGH input current I IH,XIN V IH = V DD = 3.6 V100µAXOUT output current magnitude I XOUT Logic mode, VXOUT=VDD/2, VDD= 3.6 V|200|µACrystal mode, VXOUT=VDD/2, VDD= 2.7 V|300|µALogic LOW output voltage V OL I OL = 500 µA0.4VLogic HIGH output voltage V OH I OH = –500 µA VDD–0.4VSERIAL PROGRAMMING TIMINGDATA to CLK setup time t SU150nS DATA to CLK hold time t H110nSCLK to LE setup time t SU250nS CLK pulse width logic HIGH t PWH 50nS CLK pulse width logic LOW t PWL 50nS LE pulse width t PW50nSCHARGE PUMPCharge pump output currentI DO,sourceHigh gain mode, V DOM ,V DOA = V DD /2–1600µA Low gain mode, V DOM ,V DOA = V DD /2–160µA I DO,sinkHigh gain mode, V DOM ,V DOA = V DD /2+1600µA Low gain mode, V DOM ,V DOA = V DD /2+160µA Charge pump high-Z state current I DO,high-Z1nAElectrical Characteristics (continued)(V DD,main = V DD,aux = V DD = 3.0 V, T A = 25 °C unless otherwise noted)ParameterSymbolConditionValueUnitmin.typ.max.0.5 V V DOM ,V DOA V DD 0.5 V–≤≤Functional DescriptionThe FS8160 dual phase-locked loop (PLL) IC contains two identical PLLs (main and aux-iliary). Both the main and auxiliary PLLs share the crystal oscillator, serial data input logic, and multi-function lock detector output circuits. Each PLL has its own program-mable input and reference frequency dividers, phase/frequency detectors, programmable charge pumps, and digital-filtered lock detectors.Programmable Input Frequency DividerThe VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as f V . The programmable input frequency divider consists of a ÷ 16/17 (P /P +1) dual-modulus prescaler and a 16-bit (N ) counter, which is further comprised of a 4-bit swallow (A ) counter, and a 12-bit main (B ) counter. The total divide ratio, M , is related to values for P , A , and B through the relationwith The minimum programmable divisor for continuous counting is given by and the valid total divide ratio range for the input divider is Programmable Reference Frequency DividerThe crystal oscillator output is divided by the programmable divider and then internally output to the PFD as f R . The programmable reference frequency divider consists of a 13-bit reference (R ) counter. Because of its design, the valid total divide ratio range for the reference divider is M P 1+()A P B A –()×+×P B A ,+×==B A .≥P P 1–()×1615×240,==M 240 to 65535.=R 2 to 4095.=cated below.The definition of the contents of the shift register relating to each particular latch location is listed in the table below.The 12-bit main and auxiliary reference (R ) divider ratios are specified by theMAINR[11:0] and AUXR[11:0] bits, respectively, and are defined in the table below.Table 1: Latch enable control bitsCB[1]CB[0]Latch Location00Aux. R 01Aux. N 10Main R 11Main NTable 2: Serial data input formatFirst bit Shift Register Bit Location Last bit 17161514131211109876543210Aux. R FOLD[3:0]AUXR[11:0])00Aux. N AUXB[11:0]AUXA[3:0]01Main R CP_CNTRL[3:0]MAINR[11:0]10Main NMAINB[11:0]MAINA[3:0]11Table 3: Reference divider ratiosDivide Ratio MAINR[11:0] and AUXR[11:0]111098765432102000000000010311•••••••••••••4095111111111111Similarly, the 16-bit main and auxiliary input (N ) divider ratios are specified by theMAINA[3:0] + MAINB[11:0] and AUXA[3:0] + AUXB[11:0] bits, respectively, and are defined in the table below.The charge pump control bits CP_CNTRL[3:0] set (1) the phase detector polarity and (2) the magnitude of the charge pump source/sink current, and are defined below.Table 4: Input divider ratiosDivide RatioMAINB[11:0] and AUXB[11:0]Divide RatioMAINA[3:0] and AUXA[3:0]11109876543210321030000000000110000041101••••••••••••••••••4095111111111111151111Table 5: Charge pump and PFD control bitsBitLatch LocationFunction“0”“1”CP_CNTRL[3]Main R, bit 17Aux. charge pump current Low, 160 µA High, 1600 µA CP_CNTRL[2]Main R, bit 16Main charge pump current Low, 160 µA High, 1600 µA CP_CNTRL[1]Main R, bit 15Aux. phase/frequency detector polarity a a.When the VCO frequency increases with increasing control voltage, set the phase/frequency detector polarity to positive . When the VCO frequency decreases with increasing control voltage, set the phase/frequency detector polarity to negative .Negative Positive CP_CNTRL[0]Main R, bit 14Main phase/frequency detector polarityNegativePositiveThe outputs selected by the FOLD[3:0] control bits for the multiplexed FOLD output pin are defined in the table below.Serial input data timing waveforms are shown in Fig. 3.Fig. 3 – Serial input data timing waveformsTable 6: Multiplexed FOLD output control bitsFOLD[3]FOLD[2]FOLD[1]FOLD[0]FOLD Output StateAux. R, bit 17Aux. R, bit 16Aux. R, bit 15Aux. R, bit 140000“0”0001“1”001×Main lock detector output 010×Aux. lock detector output 011×Main AND Aux. lock detector output100×Main R -divider output 101×Aux. R -divider output 110×Main N -divider output 111×Aux. N -divider outputt SU1t SU2t H1DATACLK LEDATACLKLEM S B2345678910111213141516171L S B18t PWHt PWLt PW。