HCF4040BEY中文资料

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) temperature range.
Min Typ Max
3
-
15
0
-
VDD
−40 -
+85
-
-
3.75
-
-
0.5
-
-
0.08
Unit V V °C ns/V ns/V ns/V
HEF4049B_5
Product data sheet
Rev. 05 — 11 November 2008
© NXP B.V. 2008. All rights reserved.
6. Pinning information
6.1 Pinning
Fig 4. Pin configuration
HEF4049B
VDD 1 1Y 2 1A 3 2Y 4 2A 5 3Y 6 3A 7
VSS 8
16 n.c. 15 6Y 14 6A 13 n.c. 12 5Y 11 5A 10 4Y 9 4A 001aae602
HEF4049BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm

CD4017是5位Johnson计算器，具有10个译码输出端，CP，CR，INH输入端。

时钟输入端的斯密特触发器具有脉冲整形功能，对输入时钟脉冲上升和下降时间无限制。

INH为低电平时，计算器在时钟上升沿计数；反之，计数功能无效。

CR 为高电平时，计数器清零。

Johnson计数器，提供了快速操作，2输入译码选通和无毛刺译码输出。

防锁选通，保证了正确的计数顺序。

译码输出一般为低电平，只有在对应时钟周期内保持高电平。

在每10个时钟输入周期CO信号完成一次进位，并用作多级计数链的下级脉动时钟。

CD4017引脚功能：
CD4017内部是除10的计数器及二进制对10进制译码电路。

CD4017有16支脚，除电源脚VDD及VSS为电源接脚，输入电压范围为3–15V之外，其余接脚为：
A、频率输入脚：CLOCK(Pin14)，为频率信号的输入脚。

B、数据输出脚：
a、 Q1-Q9(Pin3，2，4，7，10，1，5，6，9，11)，为*后的时进制输出接脚，被计数到的值，其输出为Hi，其余为Lo 电位。

b、CARRY OUT（Pin12），进位脚，当4017计数10个脉冲之后，CARRY OUT将输出一个脉波，代表产生进位，共串级计数器使用。

D、 控制脚：
a、 CLEAR(Pin15)：清除脚或称复位(Reset)脚，当此脚为Hi时，会使CD4017的Q0为”1”，其余Q1-Q9为”0”。

b、CLOCK ENABLE(Pin13)，时序允许脚，当此脚为低电位，CLOCK输入脉波在正缘时，会使CD4017计数，并改变Q1-Q9的输出状态。

74VHC4046中文资料TL F 1167574VHC4046CMOS Phase Lock LoopOctober 199574VHC4046CMOS Phase Lock LoopGeneral DescriptionThe 74VHC4046is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high fre-quency operation both in the phase comparator and VCO sections This device contains a low power linear voltage controlled oscillator (VCO) a source follower and three phase comparators The three phase comparators have a common signal input and a common comparator input The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or directly coupled with standard input logic levels This device is similar to the CD4046except that the Zener diode of the metal gate CMOS device has been replaced with a third phase comparatorPhase Comparator I is an exclusive OR (XOR)gate It pro-vides a digital error signal that maintains a 90phase shift between the VCO’s center frequency and the input signal (50%duty cycle input waveforms) This phase detector is more susceptible to locking onto harmonics of the input fre-quency than phase comparator I but provides better noise rejectionPhase comparator III is an SR flip-flop gate It can be used toprovide the phase comparator functions and is similar to the first comparator in performancePhase comparator II is an edge sensitive digital sequential network Two signal outputs are provided a comparator out-put and a phase pulse output The comparator output is a TRI-STATE output that provides a signal that locks the VCO output signal to the input signal with 0phase shift be-tween them This comparator is more susceptible to noise throwing the loop out of lock but is less likely to lock onto harmonics than the other two comparatorsIn a typical application any one of the three comparators feed an external filter network which in turn feeds the VCO input This input is a very high impedance CMOS input which also drives the source follower The VCO’s operating frequency is set by three external components connected to the C1A C1B R1and R2pins An inhibit pin is provided to disable the VCO and the source follower providing a meth-od of putting the IC in a low power stateThe source follower is a MOS transistor whose gate is con-nected to the VCO input and whose drain connects the De-modulator output This output normally is used by tying a resistor from pin 10to ground and provides a means of looking at the VCO input without loading down modifying the characteristics of the PLL filterFeaturesY Low dynamic power consumption (V CC e 4 5V)YMaximum VCO operating frequency 12MHz (V CC e 4 5V)YFast comparator response time (V CC e 4 5V)Comparator I 25ns Comparator II 30ns Comparator III 25ns Y VCO has highlinearity and high temperature stability YPin and function compatible with the 74HC4046Commercial Package Package Description Number 74VHC4046M M16A 16-Lead Molded JEDEC SOIC 74VHC4046N N16E16-Lead Molded DIPNote Surface mount packages are also available on Tape and Reel Specify by appending the suffix letter ‘‘X’’to the ordering codeTRI-STATE is a registered trademark of National Semiconductor Corporation C 1995National Semiconductor CorporationRRD-B30M125 Printed in U S ABlock and Connection DiagramsTL F 11675–1Pin Assignment forSOIC and PDIPTL F 11675–22Absolute Maximum Ratings(Notes1 2) Supply Voltage(V CC)b0 5to a7 0V DC Input Voltage(V IN)b1 5to V CC a1 5V DC Output Voltage(V OUT)b0 5to V CC a0 5V Clamp Diode Current(I IK I OK)g20mA DC Output Current per pin(I OUT)g25mA DC V CC or GND Current per pin(I CC)g50mA Storage Temperature Range(T STG)b65 C a150 C Power Dissipation(P D)(Note3)600mW S O Package only500mW Lead Temperature(T L)(Soldering10seconds)260 C Operating ConditionsMin Max Units Supply Voltage(V CC)26V DC Input or Output Voltage0V CC V (V IN V OUT)Operating Temp Range(T A)74VHC b40a85 C Input Rise or Fall Times(t r t f)V CC e2 0V1000ns V CC e4 5V500nsV CC e6 0V400nsDC Electrical Characteristics(Note4)T A e25 C 74VHCSymbol Parameter Conditions V CC T A eb40to85 C UnitsTyp Guaranteed LimitsV IH Minimum High Level Input2 0V1 51 5V Voltage4 5V3 153 15V6 0V4 24 2V V IL Maximum Low Level Input2 0V0 50 5V Voltage4 5V1 351 35V6 0V1 81 8V V OH Minimum High Level Output V IN e V IH or V ILVoltage l I OUT l s20m A2 0V2 01 91 9V4 5V4 54 44 4V6 0V6 05 95 9VV IN e V IH or V ILl I OUT l s4 0mA4 5V4 23 983 84Vl I OUT l s5 2mA6 0V5 75 485 34V V OL Maximum Low Level Output V IN e V IH or V ILVoltage l I OUT l s20m A2 0V00 10 1V4 5V00 10 1V6 0V00 10 1VV IN e V IH or V ILl I OUT l s4 0mA4 5V0 20 260 33Vl I OUT l s5 2mA6 0V0 20 260 33V I IN Maximum Input Current(Pins3 5 9)V IN e V CC or GND6 0V g0 1g1 0m A I IN Maximum Input Current(Pin14)V IN e V CC or GND6 0V205080m A I OZ Maximum TRI-STATE Output V OUT e V CC or GND6 0V g0 25g2 5m ALeakage Current(Pin13)I CC Maximum Quiescent Supply V IN e V CC or GND6 0V304065m ACurrent I OUT e0m AV IN e V CC or GND6 0V6007501200m APin14OpenNote1 Maximum Ratings are those values beyond which damage to the device may occurNote2 Unless otherwise specified all voltages are referenced to groundNote3 Power Dissipation temperature derating plastic‘‘N’’package b12mW C from65 C to85 CNote4 For a power supply of5V g10%the worst case output voltages(V OH and V OL)occur for VHC at4 5V Thus the4 5V values should be used when designing with this supply Worst case V IH and V IL occur at V CC e5 5V and4 5V respectively (The V IH value at5 5V is3 85V )The worst case leakage current(I IN I CC and I OZ)occur for CMOS at the higher voltage and so the6 0V values should be used3AC Electrical Characteristics V CC e2 0to6 0V CL e50pF t r e t f e6ns(unless otherwise specified )Symbol Parameters Conditions V CCT e25C74VHCUnits Typ Guaranteed LimitsAC Coupled C(series)e100pF2 0V25100150mVInput Sensitiv-f IN e500kHz4 5V50150200mVity Signal In6 0V135250300mV t r t f Maximum Output2 0V307595ns Rise and Fall4 5V91519nsTime6 0V81215ns C IN Maximum Input7pFCapacitancePhase Comparator It PHL t PLH Maximum Prop-3 3V65117146ns agation Delay4 5V254050ns6 0V203443ns Phase Comparator IIt PZL Maximum TRI-3 3V75130160ns STATE Enable4 5V254556nsTime6 0V223848ns t PZH t PHZ Maximum TRI-3 3V88140175ns STATE Enable4 5V304860nsTime6 0V254151ns t PLZ Maximum TRI-3 3V90140175ns STATE Disable4 5V324860nsTime6 0V284151ns t PHL t PLH Maximum Prop-3 3V100146180ns agation Delay4 5V345063nsHigh to Low6 0V274353nsto Phase PulsesPhase Comparator IIIt PHL t PLH Maximum Prop-3 3V75117146ns agation Delay4 5V254050ns6 0V223443nsC PD Maximum Power All Comparators130pFDissipation V IN e V CC and GNDCapacitanceVoltage Controlled Oscillator(Specified to operate from V CC e3 0V to6 0V)f MAX Maximum C1e50pFOperating R1e100X4 5V74 5MHzFrequency R2e%6 0V117MHzVCO in e V CCC1e0pF4 5V12MHzR1e100X6 014MHzVCO in e V CCDuty Cycle50% Demodulator OutputOffset Voltage R s e20k X4 5V0 751 31 5VVCO in–V demOffset R s e20k X4 5VVariation VCO in e1 75V0 65V2 25V0 12 75V0 754Typical Performance CharacteristicsTypical Center Frequencyvs R1 C1V CC e4 5VTL F 11675–3Typical Center Frequencyvs R1 C1V CC e6VTL F 11675–4Typical Offset Frequencyvs R2 C1V CC e4 5VTL F 11675–5Typical Offset Frequencyvs R2 C1V CC e6VTL F 11675–6 5Typical Performance Characteristics(Continued) VHC4046Typical VCO Power Dissipation Center Frequency vs R1TL F 11675–7VHC4046Typical VCO Power Dissipation f min vs R2TL F 11675–8VHC4046VCO in vs f out V CC e4 5VTL F 11675–9VHC4046VCO in vs f out V CC e4 5VTL F 11675–10VHC4046VCO out vsTemperature V CC e4 5VTL F 11675–11VHC4046VCO out vsTemperature V CC e6VTL F 11675–12 6Typical Performance Characteristics(Continued)VHC4046Typical Source Follower Power Dissipation vs RSTL F 11675–13Typical f max f min vs R2 R1V CC e 4 5V 6V f max f minTL F 11675–14VHC4046Typical VCO Linearity vs R1 C1TL F 11675–15VHC4046Typical VCO Linearity vs R1 C1TL F 11675–16VCO WITHOUT OFFSETR2e %VCO WITH OFFSET(a)TL F 11675–17FIGURE 17Comparator I Comparator II III R2e%R2i%R2e%R2i%–Given f0–Given f0and f L–Given f max–Given f min and f max –Use f0with curve titled–Calculate f min from the–Calculate f0from the–Use f min with curve titled center frequency vs R1 C equation f min e f o b f L equation f o e f max 2offset frequencyvs R2to determine R1and C1–Use f min with curve titled–Use f0with curve titled C to determine R2and C1offset frequency vs R2 C center frequency vs R1 C–Calculate f max f minto determine R2and C1to determine R1and C1–Use f max f min with curve–Calculate f max f min from titled f max f min vs R2 R1the equation f max f min e to determine ratio R2 R1f o a f L f o b f L to obtain R1–Use f max f min with curvetitled f max f min vs R2 R1to determine ratio R2 R1to obtain R1(b)FIGURE1(Continued)Detailed Circuit DescriptionVOLTAGE CONTROLLED OSCILLATOR SOURCEFOLLOWERThe VCO requires two or three external components to op-erate These are R1 R2 C1 Resistor R1and capacitor C1 are selected to determine the center frequency of the VCO R1controls the lock range As R1’s resistance decreases the range of f min to f max increases Thus the VCO’s gain decreases As C1is changed the offset(if used)of R2 and the center frequency is changed (See typical performance curves)R2can be used to set the offset frequency with0V at VCO input If R2is omitted the VCO range is from0Hz As R2is decreased the offset frequency is increased The ef-fect of R2is shown in the design information table and typi-cal performance curves By increasing the value of R2the lock rangeof the PLL is offset above0Hz and the gain (Volts rad )does not change In general when offset is de-sired R2and C1should be chosen first and then R1should be chosen to obtain the proper center frequency Internally the resistors set a current in a current mirror as shown in Figure1 The mirrored current drives one side ofTL F 11675–18FIGURE2 Logic Diagram for VCO8Detailed Circuit Description (Continued)the capacitor once the capacitor charges up to the thresh-old of the schmitt trigger the oscillator logic flips the capaci-tor over and causes the mirror to charge the opposite side of the capacitor The output from the internal logic is then taken to pin4The input to the VCO is a very high impedance CMOS input and so it will not load down the loop filter easing the filters design In order to make signals at the VCO input accessible without degrading the loop performance a source follower transistor is provided This transistor can be used by con-necting a resistor to ground and its drain output will follow the VCO input signalAn inhibit signal is provided to allow disabling of the VCO and the source follower This is useful if the internal VCO is not being used A logic high on inhibit disables the VCO and source followerThe output of the VCO is a standard high speed CMOS output with an equivalent LSTTL fanout of 10 The VCO output is approximately a square wave This output can ei-ther directly feed the comparator input of the phase compar-ators or feed external prescalers (counters)to enable fre-quency synthesis PHASE COMPARATORSAll three phase comparators share two inputs Signal In and Comparator In The Signal In has a special DC bias network that enables AC coupling of input signals If the signals are not AC coupled then this input requires logic levels the same as standard 74VHC The Comparator input is a stan-dard digital input Both input structures are shown in Figure 3The outputs of these comparators are essentially standard 74VHC voltage outputs (Comparator II is TRI-STATE )TL F 11675-19FIGURE 3 Logic Diagram for Phase Comparator I and the Common Input Circuit for All Three ComparatorsTL F 11675–20FIGURE 4 Typical Phase Comparator I Waveforms9Detailed Circuit Description(Continued)Thus in normal operation V CC and ground voltage levels are fed to the loop filter This differs from some phase detectors which supply a current output to the loop filter and this should be considered in the design (The CD4046also pro-vides a voltage ) Figure5shows the state tables for all three comparators PHASE COMPARATOR IThis comparator is a simple XOR gate similar to the 54 74HC86 and its operation is similar to an overdriven balanced modulator To maximize lock range the input fre-quencies musthave a50%duty cycle Typical input and output waveforms are shown in Figure4 The output of the phase detector feeds the loop filter which averages the out-put voltage The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range The capture range for phase detector I is dependent on the loop filter employed The capture range can be as large as the lock range which is equal to the VCO frequency rangeTo see how the detector operates refer to Figure4 When two square wave inputs are applied to this comparator an output waveform whose duty cycle is dependent on the phase difference between the two signals results As the phase difference increases the output duty cycle increases and the voltage after the loop filter increases Thus in order to achieve lock when the PLL input frequency increases the VCO input voltage must increase and the phase difference between comparator in and signal in will increase At an input frequency equal f min the VCO input is at0V and this requires the phase detector output to be ground hence the two input signals must be in phase When the input frequen-cy is f max then the VCO input must be V CC and the phase detector inputs must be180 out of phaseThe XOR is more susceptible to locking onto harmonics of the signal input than the digital phase detector II This can be seen by noticing that a signal2times the VCO frequency results in the same output duty cycle as a signal equal the VCO frequency The difference is that the output frequency of the2f example is twice that of the other example The loop filter and the VCO range should be designed to prevent locking on to harmonics PHASE COMPARATOR IIThis detector is a digital memory network It consists of fourflip-flops and some gating logic a three state output and a phase pulse output as shown in Figure6 This comparator acts only on the positive edges of the input signals and is thus independent of signal duty cyclePhase comparator II operates in such a way as to force the PLL into lock with0phase difference between the VCO output and the signal input positive waveform edges Figure 7shows some typical loop waveforms First assume that the signal input phase is leading the comparator input ThisPhase Comparator State DiagramsTL F 11675–21FIGURE5 PLL State Tables10Detailed Circuit Description(Continued)TL F 11675–22FIGURE6 Logic Diagram for Phase Comparator IITL F 11675–23FIGURE7 Typical Phase Comparator II Output Waveforms11Detailed Circuit Description (Continued)means that the VCO’s frequency must be increased to bring its leading edge into proper phase alignment Thus the phase detector II output is set high This will cause the loop filter to charge up the VCO input increasing the VCO fre-quency Once the leading edge of the comparator input is detected the output goes TRI-STATE holding the VCO input at the loop filter voltage If the VCO still lags the signal then the phase detector will again charge up to VCO input for the time between the leading edges of both waveformsIf the VCO leads the signal then when the leading edge of the VCO is seen the output of the phase comparator goes low This discharges the loop filter until the leading edge of the signal is detected at which time the output TRI-STATE itself again This has the effect of slowing down the VCO to again make the rising edges of both waveform coincident When the PLL is out of lock the VCO will be running either slower or faster than the signal input If it is running slower the phase detector will see more signal rising edges and so the output of the phase comparator will be high a majority of the time raising the VCO’s frequency Conversely if the VCO is running faster than the signal the output of the de-tector will be low most of the time and the VCO’s output frequency will be decreasedAs one can see when the PLL is locked the output of phase comparator II will be almost always TRI-STATE except for minor corrections at the leading edge of the waveforms When the detector is TRI-STATE the phase pulse output is high This outputcan be used to determine when the PLL is in the locked condition This detector has several interesting characteristics Over the entire VCO frequency range there is no phase differ-ence between the comparator input and the signal input The lock range of the PLL is the same as the capture rangeMinimal power is consumed in the loop filter since in lock the detector output is a high impedance Also when no sig-nal is present the detector will see only VCO leading edges and so the comparator output will stay low forcing the VCO to f min operating frequencyPhase comparator II is more susceptible to noise causing the phase lock loop to unlock If a noise pulse is seen on the signal input the comparator treats it as another positive edge of the signal and will cause the output to go high until the VCO leading edge is seen potentially for a whole signal input period This would cause the VCO to speed up during that time When using the phase comparator I the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset PHASE COMPARATOR IIIThis comparator is a simple S-R Flip-Flop which can func-tion as a phase comparator Figure 8 It has some similar characteristics to the edge sensitive comparator To see how this detector works assume input pulses are applied to the signal and comparator inputs as shown in Figure 9 When the signal input leads the comparator input the flop is set This will charge up the loop filter and cause the VCO to speed up bringing the comparator into phase with the sig-nal input When using short pulses as input this comparator behaves very similar to the second comparator But one can see that if the signal input is a long pulse the output of the comparator will be forced to a one no matter how manycomparator input pulses are received Also if the VCO input is a square wave (as it is)and the signal input is pulse then the VCO will force the comparator output low much of the time Therefore it is ideal to condition the signal and com-parator input to short pulses This is most easily done by using a series capacitorTL F 11675–24FIGURE 8 Phase Comparator III Logic DiagramTL F 11675–25FIGURE 9 Typical Waveforms for Phase Comparator III12Ordering InformationThe device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as followsTL F 11675–26 Physical Dimensions inches(millimeters)16-Lead(0 150 Wide)Molded Small Outline Package JEDEC Order Number74VHC4046MNS Package Number M16A1374V H C 4046C M O S P h a s e L o c k L o o pPhysical Dimensions inches (millimeters)(Continued)Molded Dual-In-Line Package (N)Order Number 74VHC4046N NS Package Number N16ELIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectivenessbe reasonably expected to result in a significant injury to the userNational Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation EuropeHong Kong LtdJapan Ltd1111West Bardin RoadFax (a 49)0-180-530858613th Floor Straight Block Tel 81-043-299-2309。

Low Profile, High Current InductorFor technical questions, contact: magnetics@Document Number: 34193IHLP-4040DZ-01Vishay DaleFEATURES•Shielded construction•Frequency range up to 5.0 MHz•Lowest DCR/µH, in this package size•Handles high transient current spikes without saturation•Ultra low buzz noise, due to composite construction •100 % lead (Pb)-free and RoHS compliantManufactured under one or more of the following:US Patents; 6,198,375/6,204,744/6,449,829/6,460,244.Several foreign patents, and other patents pending.NOTES:1. All test data is referenced to 25 °C ambient2. Operating Temperature Range - 55 °C to + 125 °C3. DC current (A) that will cause an approximate ΔT of 40 °C4. DC current (A) that will cause Lo to drop approximately 20 %5. The part temperature (ambient + temp rise) should not exceed 125 °C under worst case operating conditions. Circuit design,component placement, PWB trace size and thickness, airflow and other cooling provisions all affect the part temperature. Part temperature should be verified in the end application.STANDARD ELECTRICAL SPECIFICATIONSLoINDUCTANCEµH ± 20 %at 100 kHz, 0.25 V, 0 ADCR m Ω TYPICAL 25 °C DCR m ΩMAX 25 °C HEATRATING CURRENT DC AMPS 3 TYPICAL SATURATION CURRENT DC AMPS 4 TYPICAL 0.190.8750.9540.090.00.36 1.30 1.4031.560.00.56 1.70 1.8027.549.01.0 3.70 4.1017.536.01.5 5.30 5.8015.027.52.28.209.0012.025.63.310.8011.8010.018.64.715.0016.509.517.05.617.6019.308.516.06.821.2023.308.013.51033.2036.506.812.0APPLICATIONS•PDA/Notebook/Desktop/Server applications •High current POL converters•Low profile, high current power supplies •Battery powered devices•DC/DC converters in distributed power systems•DC/DC converter for Field Programmable Gate Array (FPGA)Low Profile, High Current Inductor Vishay DaleDocument Number: 34193For technical questions, contact: magnetics@ IHLP-4040DZ-01Vishay Dale Low Profile, High Current Inductor Array For technical questions, contact: magnetics@ Document Number: 34193Disclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网。