C504RU中文资料

Chapter 1:CycloneIV Device DatasheetOperating Conditions

Cyclone IV Device Handbook,Volume 3ESD PerformanceThis section lists the electrostatic discharge (ESD) voltages using the human body model (HBM) and charged device model (CDM) for CycloneIV devices general purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table1–5 lists the ESD for CycloneIV devices GPIOs and HSSI I/Os.VCCA_GXBTransceiver PMA and auxiliary power supply—2.3752.52.625VVCCL_GXBTransceiver PMA and auxiliary power supply—1.161.21.24VVIDC input voltage—–0.5—3.6VVODC output voltage—0—VCCIOVTJOperating junction temperatureFor commercial use0—85°CFor industrial use–40—100°CtRAMPPower supply ramp timeStandard power-on reset (POR) (7)50 µs—50 ms—Fast POR (8)50 µs—3 ms—IDiodeMagnitude of DC current across PCI-clamp diode when enabled———10mANotes to Table1–4:(1)All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time.(2)You must connect VCCD_PLL to VCCINT through a decoupling capacitor and ferrite bead.(3)Power supplies must rise monotonically.(4)VCCIO for all I/O banks must be powered up during device operation. Configurations pins are powered up by VCCIO of I/O Banks 3, 8, and 9 where I/O Banks 3 and 9 only support VCCIO of 1.5, 1.8, 2.5, 3.0, and 3.3V. For fast passive parallel (FPP) configuration mode, the VCCIO level of I/O Bank8 must be powered up to 1.5, 1.8, 2.5, 3.0, and 3.3 V.(5)You must set VCC_CLKIN to 2.5 V if you use CLKIN as a high-speed serial interface (HSSI) refclk or as a DIFFCLK input.(6)The CLKIN pins in I/O Banks 3B and 8B can support single-ended I/O standard when the pins are used to clock left PLLs in non-transceiverapplications.(7)The POR time for Standard POR ranges between 50 and 200ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating range within 50 ms.(8)The POR time for Fast POR ranges between 3 and 9ms. VCCINT, VCCA, and VCCIO of I/O Banks 3, 8, and 9 must reach the recommended operating range within 3 ms.Table1–4.Recommended Operating Conditions for CycloneIVGX Devices(Part 2 of 2)SymbolParameterConditionsMinTypMaxUnit

DC Characteristics and Timing Specifications

Differential I/O StandardsThe RSDS and mini-LVDS I/O standards are only supported on output pins. The LVDS I/O standard is supported on both receiver input pins and transmitter output pins.1For more information on how these differential I/O standards are implemented, refer to the High-Speed Differential Interfaces in CycloneII Devices chapter of the CycloneII Device Handbook.Figure5–1 shows the receiver input waveforms for all differential I/O standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II, differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and differential SSTL-18 class I and II).

1.5-V HSTL class I8–80.4VCCIO – 0.41.5V HSTL class II16–160.4VCCIO – 0.4Notes to Table5–7:(1)The values in this table are based on the conditions listed in Tables5–2 and 5–6.(2)This specification is supported across all the programmable drive settings available as shown in the CycloneII Architecture chapter of the CycloneII Device Handbook.Table5–7.DC Characteristics of User I/O Pins Using Single-Ended StandardsNotes(1), (2)(Part 2 of2)I/O Standard Test Conditions Voltage ThresholdsIOL (mA)IOH (mA)Maximum VOL (V)Minimum VOH (V)Altera Corporation 5–11February 2008Cyclone II Device Handbook, Volume 1DC Characteristics and Timing Specifications

DC Characteristics and Timing Specifications

High Speed I/O Timing Specifications

The timing analysis for LVDS, mini-LVDS, and RSDS is different compared to other I/O standards because the data communication is source-synchronous.

You should also consider board skew, cable skew, and clock jitter in your calculation. This section provides details on the timing parameters for high-speed I/O standards in CycloneII devices.

Table5–47 defines the parameters of the timing diagram shown in Figure5–3.

SSTL_2_CLASS_IOCT_50_OHMS676970254260254260

SSTL_18_CLASS_IOCT_50_OHMS303336474951474951Table5–46.Maximum Output Clock Toggle Rate Derating Factors(Part 4 of4)

I/O StandardDrive StrengthMaximum Output Clock Toggle Rate Derating Factors (ps/pF)

Column I/O PinsRow I/O PinsDedicated Clock Outputs

–6Speed Grade–7Speed Grade–8Speed Grade–6Speed Grade–7Speed Grade–8Speed Grade–6Speed Grade–7Speed Grade–8Speed Grade

ISO 10042:2018

铝及铝合金的弧焊接头缺欠质量分级

狮子十之八九 译

目录

前言

引言

1 范围

2 引用标准（略）

3 名词和术语

4 符号

5 缺欠的评定

附录A（信息） 确定气孔缺欠百分比示例

附录B（信息） 附加信息和本标准使用指导

文献（略）

前言

ISO（国际标准化组织）是一个世界范围内的国家标准学会（ISO成员组织）的联合体。制定国际标准的工作

经由ISO技术委员会归口负责。每个成员组织开发一个项目，由此便形成一个技术委员会，此成员组织有权

代表该技术委员会。国际组织、政府与非政府机构协同ISO共同参与工作。ISO针对于电工标准化所有事宜

和国际电工委员会（IEC）紧密合作。

本文件的制订和进一步修订程序在ISO/IEC 指令中第1部分中有描述，须特别注意针对不同类型的ISO文件，

有不同的审批标准。本文件的起草符合ISO/IEC 指令中第2部分的相关规则(见/directives)。

请注意本文件有些部分可能涉及专利权。ISO不识别这些专利权。关于制订该文件所涉专利权的细节，见ISO

专利声明清单(见/patent)。

本文档中使用的任何商业名称都是为了方便用户而提供的信息，而不是一种认可。

关于标准的自愿性质、ISO特定术语的含义以及与符合性评估有关的表达的含义，以及关于ISO 在技术性贸

易壁垒(TBT)中遵守世界贸易组织(WTO)原则的信息，见/iso/foreword.html。

本标准是由技术委员会ISO/TC44，焊接及相关工艺和SC10委员会，焊接质量管理 归口制订的。

此第三版代替失效的第二版（ISO 10042：2005），此版本有少量修改。与前一版本的改变如下：

——在“范围”部分，删除了根据ISO4063的焊接方法代号；

——在表1，1.3中，根据ISO6520-1的缺欠代号从“2012 均布气孔”改变到“2018 表面气孔”；