CAT93C46LI-GT2中文资料

IS93C46BISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.1,024-BIT SERIAL ELECTRICALLY ERASABLE PROMJULY 2003FUNCTIONAL BLOCK DIAGRAMFEATURES•Industry-standard Microwire Interface —Non-volatile data storage —Low voltage operation: Vcc = 2.5V to 5.5V—Full TTL compatible inputs and outputs —Auto increment for efficient data dump •x16 bit organization•Hardware and software write protection—Defaults to write-disabled state at power-up —Software instructions for write-enable/disable •Enhanced low voltage CMOS E 2PROM technology•Versatile, easy-to-use Interface —Self-timed programming cycle —Automatic erase-before-write —Programming status indicator —Word and chip erasable—Chip select enables power savings •Durable and reliable—40-year data retention after 1M write cycles —1 million write cycles —Unlimited read cycles — Schmitt-trigger inputs•Industrial and Automotive Temperature GradeDESCRIPTIONThe IS93C46B is a low-cost 1kb non-volatile,ISSI ® serial EEPROM. It is fabricated using an enhanced CMOS design and process. The IS93C46B contains power-efficient read/write memory, and organization of 64 words of 16 bits.The IS93C46B is fully backward compatible with IS93C46.An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the device is write-enabled. A selected x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the two instructions WRITE ALL or ERASE ALL can program the entire array. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/BUSY status by raising chip select (CS). The self-timed write cycle includes an automatic erase-before-writecapability. The device can output any number of consecutive words using a single READ instruction.2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.A IS93C46BISSI®PIN CONFIGURATIONS8-Pin JEDEC SOIC “G”8-Pin JEDEC SOIC “GR”PIN DESCRIPTIONSCS Chip Select SK Serial Data Clock D IN Serial Data Input D OUT Serial Data Output NC Not Connected Vcc Power GNDGroundinstruction begins with a start bit of the logical “1” or HIGH. Following this are the opcode (2 bits),address field (6 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clock-speed flexibility. Upon completion of buscommunication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway.Read (READ)The READ instruction is the only instruction that outputs serial data on the D OUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical “0” bit precedes the actual 16-bit output data string.) The output on D OUT changes during the low-to-high transitions of SK (see Figure 3).Low Voltage ReadThe IS93C46B has been designed to ensure that data read operations are reliable in low voltage environments.They provide accurate operation with Vcc as low as 2.5V.Auto Increment Read OperationsIn the interest of memory transfer operation applications,the IS93C46B has been designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location ad-dress. Once the 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continu-ously with CS HIGH until the chip select (CS) control pin is brought LOW . This allows for single instruction data dumps to be executed with a minimum of firmware overhead.ApplicationsThe IS93C46B is very popular in many high-volume applications which require low-power, low-density storage. Applications using this device include industrial controls, networking, and numerous other consumer electronics.Endurance and Data RetentionThe IS93C46B is designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). It provides 40 years of secure data retention without power after the execution of 1M programming cycles.Device OperationsThe IS93C46B is controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each12348765CS SK D IN D OUTVCC NC NC GND12348765NC VCC CS SKNC GND D OUT D IN12348765CS SK D IN D OUTVCC NC NC GND(Rotated)8-Pin DIP, 8-Pin TSSOPIS93C46BISSI®Write All (WRALL)The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 250 ns (t CS ), the D OUT pin indicates the READY/BUSY status of the chip (see Figure 6).Write Disable (WDS)The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against acci-dental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation.Erase Register (ERASE)After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of t CS , will cause D OUT to indicate the READ/BUSY status of the chip: a logical “0” indicates programming is still in progress;a logical “1” indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8).Erase All (ERAL)Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical “1” (see Figure 9).Write Enable (WEN)The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL,ERASE, and ERAL) can be done. When Vcc is applied,this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.)Write (WRITE)The WRITE instruction includes 16 bits of data to be written into the specified register. After the last data bit has been applied to D IN , and before the next rising edge of SK, CS must be brought LOW. If the device is write-enabled, then the falling edge of CS initiates the self-timed programming cycle (see WEN).If CS is brought HIGH, after a minimum wait of 250 ns (5V operation) after the falling edge of CS (t CS ) D OUT will indicate the READY/BUSY status of the chip. Logical “0”means programming is still in progress; logical “1” means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle,t WP ; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag.INSTRUCTION SET - IS93C46B16-bit OrganizationInstruction Start BitOP Code Address (1)Input DataREAD110(A 5-A 0)—WEN (Write Enable)10011xxxx —WRITE101(A 5-A 0)(D 15-D 0) (2)WRALL (Write All Registers)10001xxxx (D 15-D 0) (2)WDS (Write Disable)10000xxxx —ERASE111(A 5-A 0)—ERAL (Erase All Registers)10010xxxx—Notes:1. x = Don't care bit.2.If input data is not 16 bits exactly, the last 16 bits will be taken as input data.IS93C46B ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV GND Voltage with Respect to GND–0.3 to +6.5VT BIAS Temperature Under Bias (Industrial)–40 to +85°CT BIAS Temperature Under Bias (Automotive)–40 to +125°CT STG Storage Temperature–65 to +150°CNotes:1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of thedevice at these or any other conditions above those indicated in the operational sections ofthis specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.OPERATING RANGERange Ambient Temperature V C CCommercial0°C to +70°C 2.5V to 5.5VIndustrial–40°C to +85°C 2.5V to 5.5VAutomotive–40°C to +125°C 2.7V to 5.5V or 4.5V to 5.5VCAPACITANCESymbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V5pFC OUT Output Capacitance V OUT = 0V5pF4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®DC ELECTRICAL CHARACTERISTICST A = 0°C to +70°C for Commercial, –40°C to +85°C for Industrial, and –40°C to +125°C for Automotive.Symbol Parameter Test Conditions Vcc Min.Max.Unit V OL Output LOW Voltage I OL = 100 µA 2.5V to 5.5V—0.2V V OL1Output LOW Voltage I OL = 2.1 mA 4.5V to 5.5V—0.4V V OH Output HIGH Voltage I OH = –100 µA 2.5V to 5.5V V CC – 0.2—V V OH1Output HIGH Voltage I OH = –400 µA 4.5V to 5.5V 2.4—V V IH Input HIGH Voltage 2.5V to 5.5V0.7X V CC V CC+1V4.5V to5.5V0.7X V CC V CC+1V IL Input LOW Voltage 2.5V to 5.5V–0.30.2X V CC V4.5V to5.5V–0.30.8I LI Input Leakage V IN = 0V to V CC (CS, SK,D IN,ORG)0 2.5µA I LO Output Leakage V OUT = 0V to V CC, CS = 0V0 2.5µA N o t e s:Automotive grade devices in this table are tested with Vcc = 2.7V to 5.5V and 4.5V to 5.5V.IS93C46B ISSI®POWER SUPPLY CHARACTERISTICST A = 0°C to +70°C for CommercialSymbol Parameter Test Conditions Vcc Min.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100µACMOS input levels 5.0V—500µAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mACMOS input levels 5.0V—3mAI SB Standby C urrent CS = V IH, SK = 0V 2.7V—10µA5.0V—30µAPOWER SUPPLY CHARACTERISTICST A = –40°C to +85°C for IndustrialSymbol Parameter Test Conditions Vcc Min.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100µACMOS input levels 5.0V—500µAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mACMOS input levels 5.0V—3mAI SB Standby C urrent CS = V IH, SK = 0V 2.7V—2µA5.0V—4µAPOWER SUPPLY CHARACTERISTICST A = –40°C to +125°C for AutomotiveSymbol Parameter Test Conditions Vcc Min.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz 2.7V—100µACMOS input levels 5.0V—500µAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz 2.7V—1mACMOS input levels 5.0V—3mAI SB Standby C urrent CS = V IH, SK = 0V 2.7V—3µA5.0V—8µA6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®AC ELECTRICAL CHARACTERISTICST A = T A = 0°C to +70°C for Commercial, –40°C to +85°C for IndustrialSymbol Parameter Test Conditions Vcc Min.Max.Unitf SK SK Clock Frequency 2.5V to 5.5V01Mhz2.7V to 5.5V01Mhz4.5V to5.5V02Mhzt SKH SK HIGH Time 2.5V to 5.5V500—ns2.7V to 5.5V350—ns4.5V to5.5V250—nst SKL SK LOW Time 2.5V to 5.5V500—ns2.7V to 5.5V350—ns4.5V to5.5V250—nst CS Minimum CS LOW Time 2.5V to 5.5V500—ns2.7V to 5.5V250—ns4.5V to5.5V250—nst CSS CS Setup Time Relative to SK 2.5V to 5.5V100—ns2.7V to 5.5V50—ns4.5V to5.5V50—nst DIS Din Setup Time Relative to SK 2.5V to 5.5V100—ns2.7V to 5.5V100—ns4.5V to5.5V100—nst CSH CS Hold Time Relative to SK 2.5V to 5.5V0—ns2.7V to 5.5V0—ns4.5V to5.5V0—nst DIH Din Hold Time Relative to SK 2.5V to 5.5V100—ns2.7V to 5.5V100—ns4.5V to5.5V100—nst PD1Output Delay to “1”AC Test 2.5V to 5.5V—400ns2.7V to 5.5V—350ns4.5V to5.5V—250nst PD0Output Delay to “0”AC Test 2.5V to 5.5V—400ns2.7V to 5.5V—350ns4.5V to5.5V—250nst SV CS to Status Valid AC Test 2.5V to 5.5V—400ns2.7V to 5.5V—250ns4.5V to5.5V—250nst DF CS to Dout in 3-state AC Test, CS=VIL 2.5V to 5.5V—200ns2.7V to 5.5V—200ns4.5V to5.5V—100nst WP Write Cycle Time 2.5V to 5.5V—10ms2.7V to 5.5V—10ms4.5V to5.5V—5msN o t e s:1. C L = 100pFIS93C46B ISSI®AC ELECTRICAL CHARACTERISTICST A = –40°C to +125°C for AutomotiveSymbol Parameter Test Conditions Vcc Min.Max.Unitf SK SK Clock Frequency 2.7V to 5.5V01Mhz4.5V to5.5V02Mhzt SKH SK HIGH Time 2.7V to 5.5V500—ns4.5V to5.5V250—nst SKL SK LOW Time 2.7V to 5.5V500—ns4.5V to5.5V250—nst CS Minimum CS LOW Time 2.7V to 5.5V250—ns4.5V to5.5V250—nst CSS CS Setup Time Relative to SK 2.7V to 5.5V100—ns4.5V to5.5V50—nst DIS Din Setup Time Relative to SK 2.7V to 5.5V100—ns4.5V to5.5V100—nst CSH CS Hold Time Relative to SK 2.7V to 5.5V0—ns4.5V to5.5V0—nst DIH Din Hold Time Relative to SK 2.7V to 5.5V100—ns4.5V to5.5V100—nst PD1Output Delay to “1”AC Test 2.7V to 5.5V—400ns4.5V to5.5V—250nst PD0Output Delay to “0”AC Test 2.7V to 5.5V—400ns4.5V to5.5V—250nst SV CS to Status Valid AC Test 2.7V to 5.5V—250ns4.5V to5.5V—250nst DF CS to Dout in 3-state AC Test, CS=VIL 2.7V to 5.5V—200ns4.5V to5.5V—100nst WP Write Cycle Time 2.7V to 5.5V—10ms4.5V to5.5V—5msN o t e s:1. C L = 100pF8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®AC WAVEFORMSFIGURE 2. SYNCHRONOUS DATA TIMINGNotes:To determine address bits An-A0 and data bits Dm-Do, see Instruction Set.IS93C46B ISSI®AC WAVEFORMSFIGURE 4. WRITE ENABLE (WEN) TIMINGNotes:1. After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status(D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.2. To determine address bits A n-A0 and data bits D m-D0, see Instruction Set.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C46B ISSI®AC WAVEFORMSFIGURE 6. WRITE ALL (WRALL) TIMINGIntegrated Silicon Solution, Inc. — — 1-800-379-477411 R e v.A07/23/03IS93C46B ISSI®AC WAVEFORMSFIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMINGNote for Figures 8 and 9:After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status (D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.A07/23/03IS93C46B ISSI®ORDERING INFORMATIONCommercial: 0ºC to +70ºCSpeed Voltage Range Order Part No.Package1Mhz * 2.5V to 5.5V IS93C46B-3P300-mil Plastic DIPIS93C46B-3G SOIC (rotated) JEDECIS93C46B-3GR SOIC JEDECIS93C46B-3Z169-mil TSSOPORDERING INFORMATIONIndustrial Range: -40ºC to +85ºCSpeed Voltage Range Order Part No.Package1Mhz * 2.5V to 5.5V IS93C46B-3PI300-mil Plastic DIPIS93C46B-3GI SOIC (rotated) JEDECIS93C46B-3GRI SOIC JEDECIS93C46B-3ZI169-mil TSSOPORDERING INFORMATIONAutomotive Range: -40ºC to +125ºCSpeed Voltage Range Order Part No.Package1Mhz * 2.7V to 5.5V IS93C46B-3PA300-mil Plastic DIPIS93C46B-3GRA SOIC JEDEC* The specification allows for higher speed. Please see the AC Charateristics for more information. Integrated Silicon Solution, Inc. — — 1-800-379-477413 R e v.A07/23/03。

altronic 控制器系统 de-2500型操作说明（型号 de-2500 ioi 09-01）1.1 为了使读者更好地把握本文档的各主题内容，52页提供了说明书的章节目录，从47页开始罗列了文档中使用的技术术语词汇表。

altronic de-2500控制器系统是基于微处理器的电子系统，设计用于自动检测各类模拟和数字输入信号，来控制和监测工业压缩机。

该系统是可以使用pc（个人电脑）和提供的de-2500终端编程器进行现场编程的，并且可以通过固定存储器存储这些设置。

提供了串行通信接口，用于连接pc接口、plc接口、调制解调器和用于远程通信的卫星链路。

背后照明的4 x 20 lcd 字符显示表示了系统的状态、可编程引擎/发动机和压缩机参数和通道标号。

安装在前端的掌上键盘充当用户操作接口。

de-2500 提供了安全关闭功能，以避免对远程操作设备造成不必要的损害；同时提供了闭环自动控制功能，以优化提高系统的运行效率。

另外，de-2500支持远程数据获取并可以通过一个低成本的简单工具包专门对工业压缩机的应用程序进行监督控制。

适合于压缩机生产能力管理的优化策略包括原动力转速自动调整和容量控制。

在旋转式调节压缩机中，容量控制可以通过抽气节流阀或使用提升阀、旋转阀或滑阀的内部气体旁路输送技术实现。

在活塞往复压气机中，可以使用外部气体旁路输送环或压力调节技术控制容量。

系统的输出选项范围很广，包括模拟电流环和数字输出，支持与当今使用的各类实际系统的接口连接。

并且实现了基于原动力功率容量或其它特殊应用约束（比如制冷能力）的自动负载限制。

可以使用终端程序激活auto start选项。

系统包括三个主要组成部分：安装有显示模块（display module）de-2500的面板、电源供给模块（power supply module）691122-1和接线端模块（terminal module）691127-1。

这些组件通过电缆组件（cable assembly）693115-1交互连接在一起。

Istbh Standby current
VPOR Power-on reset voltБайду номын сангаасge
SCL, SDA, ¯IN¯T¯
VIL (1) VIH (1)
Low level input voltage High level input voltage
IOL
IL CI (2) CO (2)
Low level output current Leakage current Input capacitance Output capacitance
元器件交易网
16-bit I²C and SMBus I/O Port with Interrupt
CAT9555
FEATURES
400kHz I²C bus compatible(1) 2.3V to 5.5V operation Low stand-by current 5V tolerant I/Os 16 I/O pins that default to inputs at power-up High drive capability Individual I/O configuration Polarity inversion register Active low interrupt output Internal power-on reset No glitch on power-up Noise filter on SDA/SCL inputs Cascadable up to 8 devices Industrial temperature range RoHS-compliant 24-lead SOIC and TSSOP, and

IS93C56A IS93C66AISSI®Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROMMAY 2006FUNCTIONAL BLOCK DIAGRAMFEATURES•Industry-standard Microwire Interface —Non-volatile data storage —Wide voltage operation: Vcc = 1.8V to 5.5V—Auto increment for efficient data dump •User Configured Memory Organization —By 16-bit or by 8-bit•Hardware and software write protection—Defaults to write-disabled state at power-up —Software instructions for write-enable/disable •Enhanced low voltage CMOS E 2PROM technology•Versatile, easy-to-use Interface —Self-timed programming cycle —Automatic erase-before-write —Programming status indicator —Word and chip erasable—Chip select enables power savings •Durable and reliable—40-year data retention after 1M write cycles —1 million write cycles —Unlimited read cycles — Schmitt-trigger inputs•Industrial and Automotive Temperature Grade •Lead-free availableDESCRIPTIONThe IS93C56A/66A are 2kb/4kb non-volatile,ISSI ® serial EEPROMs. They are fabricated using an enhanced CMOS design and process. The IS93C56A/66A contain power-efficient read/write memory, and organization of either 256/512 bytes of 8 bits or 128/256 words of 16 bits. When the ORG pin is connected to Vcc or left unconnected,x16 is selected; when it is connected to ground,x8 is selected. The IS93C56A/66A are fully backward compatible with IS93C56/66.An instruction set defines the operation of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all erase and write instructions are accepted only while the devices are write-enabled.A selected x8 byte or x16 word can be modified with a single WRITE or ERASE instruction.Additionally, the two instructions WRITE ALL or ERASE ALL can program an entire array. Once a device begins its self-timed program procedure,the data out pin (Dout) can indicate the READY/BUSY status by raising chip select (CS). The self-timed write cycle includes an automatic erase-before-write capability. The devices can output any number of consecutive bytes/words using a single READ instruction.2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.A IS93C56A IS93C66AISSI®PIN CONFIGURATIONS8-Pin JEDEC SOIC “GR”PIN DESCRIPTIONSCS Chip Select SK Serial Data Clock D IN Serial Data Input D OUT Serial Data Output ORG Organization Select NC Not Connected Vcc Power GNDGroundinstruction begins with a start bit of the logical “1” or HIGH. Following this are the opcode (2 bits),address field (8 or 9 bits), and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clock-speed flexibility. Upon completion of buscommunication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway.Read (READ)The READ instruction is the only instruction that outputs serial data on the D OUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory register into a serial shift register. (Please note that one logical “0” bit precedes the actual 8 or 16-bit output data string.) The output on D OUT changes during the low-to-high transitions of SK (see Figure 3).Low Voltage ReadThe IS93C56A/66A are designed to ensure that data read operations are reliable in low voltage environments. They provide accurate operation with Vcc as low as 1.8V.Auto Increment Read OperationsIn the interest of memory transfer operation applications,the IS93C56A/66A are designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location ad-dress. Once the 8 or 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continu-ously with CS HIGH until the chip select (CS) control pin is brought LOW . This allows for single instruction data dumps to be executed with a minimum of firmware overhead.ApplicationsThe IS93C56A/66A are very popular in manyapplications which require low-power, low-density storage. Applications using these devices include industrial controls, networking, and numerous other consumer electronics.Endurance and Data RetentionThe IS93C56A/66A are designed for applications requiring up to 1M programming cycles (WRITE, WRALL, ERASE and ERAL). They provide 40 years of secure data retention without power after the execution of 1M programming cycles.Device OperationsThe IS93C56A/66A are controlled by a set ofinstructions which are clocked-in serially on the Din pin.Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each12348765CS SK D IN D OUTVCC NC ORG GND12348765CS SK D IN D OUTVCC NC ORG GND8-Pin DIP, 8-Pin TSSOPIS93C56A IS93C66AISSI®Write All (WRALL)The write all (WRALL) instruction programs all registers with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 200 ns (t CS ), the D OUT pin indicates the READY/BUSY status of the chip (see Figure 6). Vcc is required to be above 4.5V for WRALL to function properly.Write Disable (WDS)The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against acci-dental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation.Erase Register (ERASE)After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the self-timed internal programming cycle. Bringing CS HIGH after a minimum of t CS , will cause D OUT to indicate the READ/BUSY status of the chip: a logical “0” indicates programming is still in progress;a logical “1” indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8).Erase All (ERAL)Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical “1” (see Figure 9). Vcc is required to be above 4.5V for ERALL to function properly.Write Enable (WEN)The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL,ERASE, and ERAL) can be done. When Vcc is applied,this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.)Write (WRITE)The WRITE instruction includes 8 or 16 bits of data to be written into the specified register. After the last data bit has been applied to D IN , and before the next rising edge of SK, CS must be brought LOW. If the device is write-enabled, then the falling edge of CS initiates the self-timed programming cycle (see WEN).If CS is brought HIGH, after a minimum wait of 200 ns (5V operation) after the falling edge of CS (t CS ) D OUT will indicate the READY/BUSY status of the chip. Logical “0”means programming is still in progress; logical “1” means the selected register has been written, and the part is ready for another instruction (see Figure 5). The READY/BUSY status will not be available if: a) The CS input goes HIGH after the end of the self-timed programming cycle,t WP ; or b) Simultaneously CS is HIGH, Din is HIGH, and SK goes HIGH, which clears the status flag.IS93C56A IS93C66A ISSI®INSTRUCTION SET - IS93C56A (2kb)8-bit Organization16-bit Organization(ORG = GND)(ORG = Vcc) Instruction(2)Start Bit OP Code Address (1)Input Data Address (1)Input Data READ110x(A7-A0)—x(A6-A0)—WEN (Write Enable)10011xxxxxxx—11xxxxxx—WRITE101x(A7-A0)(D7-D0)x(A6-A0)(D15-D0) WRALL (Write All Registers)10001xxxxxxx(D7-D0)01xxxxxx(D15-D0) WDS (Write Disable)10000xxxxxxx—00xxxxxx—ERASE111x(A7-A0)—x(A6-A0)—ERAL (Erase All Registers)10010xxxxxxx—10xxxxxx—Notes:1. x = Don't care bit.2.If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored,and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted.INSTRUCTION SET - IS93C66A (4kb)8-bit Organization16-bit Organization(ORG = GND)(ORG = Vcc) Instruction(2)Start Bit OP Code Address (1)Input Data Address (1)Input Data READ110(A8-A0)—(A7-A0)—WEN (Write Enable)10011xxxxxxx—11xxxxxx—WRITE101(A8-A0)(D7-D0)(A7-A0)(D15-D0) WRALL (Write All Registers)10001xxxxxxx(D7-D0)01xxxxxx(D15-D0) WDS (Write Disable)10000xxxxxxx—00xxxxxx—ERASE111(A8-A0)—(A7-A0)—ERAL (Erase All Registers)10010xxxxxxx—10xxxxxx—Notes:1. x = Don't care bit.2.If the number of bits clocked-in does not match the number corresponding to a selected command, all extra trailing bits are ignored,and WRITE, WRALL, ERASE, and ERAL are also ignored, but READ, WEN, WDS are accepted.4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C56A IS93C66A ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV S Supply Voltage–0.5 to +6.5VV P Voltage on Any Pin–0.5 to Vcc + 0.5VT BIAS Temperature Under Bias–55 to +125°CT STG Storage Temperature–65 to +150°CI OUT Output Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect reliability.OPERATING RANGE(IS93C56A-2, IS93C66A-2)Range Ambient Temperature V CCIndustrial–40°C to +85°C 1.8V to 5.5VNote: ISSI offers Industrial grade for Commercial applications (0o C to +70o C)OPERATING RANGE(IS93C56A-3, IS93C66A-3)Range Ambient Temperature V CCAutomotive–40°C to +125°C 2.5V to 5.5VCAPACITANCESymbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V5pFC OUT Output Capacitance V OUT = 0V5pFIS93C56A IS93C66A ISSI®DC ELECTRICAL CHARACTERISTICST A = –40°C to +85°C for Industrial and –40°C to +125°C for Automotive.Symbol Parameter Test Conditions Vcc Min.Max.Unit V OL2Output LOW Voltage I OL = 100 µA 1.8V to 2.7V—0.2VV OL1Output LOW Voltage I OL = 2.1mA 2.7V to 5.5V—0.4VV OH2Output HIGH Voltage I OH = –100 µA 1.8V to 2.7V V CC – 0.2—VV OH1Output HIGH Voltage I OH = –400 µA 2.7V to 5.5V 2.4—VV IH Input HIGH Voltage 1.8V to 5.5V0.7X V CC V CC+1VV IL Input LOW Voltage 1.8V to 5.5V–0.30.2X V CC VI LI Input Leakage V IN = 0V to V CC (CS, SK,D IN,ORG)0 2.5µA I LO Output Leakage V OUT = 0V to V CC, CS = 0V0 2.5µA Notes:Automotive grade devices in this table are tested with Vcc = 2.5V to 5.5V. An operation with Vcc <2.5V is not specified.POWER SUPPL Y CHARACTERISTICST A = –40°C to +85°C for Industrial, –40°C to +125°C for Automotive.Symbol Parameter Test Conditions Vcc Min.Typ.Max.UnitI CC1Vcc Read Supply Current CS = V IH, SK = 1 MHz, CMOS input levels 1.8V—0.11mACS = V IH, SK = 2 MHz, CMOS input levels 2.5V—0.21mACS = V IH, SK = 2 MHz, CMOS input levels 5.0V—0.52mAI CC2Vcc Write Supply Current CS = V IH, SK = 1 MHz, CMOS input levels 1.8V—0.51mACS = V IH, SK = 2 MHz, CMOS input levels 2.5V—12mACS = V IH, SK = 2 MHz, CMOS input levels 5.0V—23mAI SB1Standby Current CS = GND, SK = GND, 1.8V—0.11µAORG = V CC or Floating (x16) 2.5V—0.12µA5.0V—0.24µAI SB2Standby Current CS = GND, SK = GND, 1.8V—610µAORG = GND (x8) 2.5V—610µA5.0V—1015µA6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C56A IS93C66A ISSI®AC ELECTRICAL CHARACTERISTICST A = –40°C to +85°C for IndustrialSymbol Parameter Test Conditions Min.Max.Unitf SK SK Clock Frequency 1.8V ≤ Vcc < 2.5V01Mhz2.5V ≤ Vcc < 4.5V02Mhz4.5V ≤ Vcc ≤5.5V03Mhzt SKH SK HIGH Time 1.8V ≤ Vcc < 2.5V250—ns2.5V ≤ Vcc < 4.5V200—ns4.5V ≤ Vcc ≤5.5V200—nst SKL SK LOW Time 1.8V ≤ Vcc < 2.5V250—ns2.5V ≤ Vcc < 4.5V200—ns4.5V ≤ Vcc ≤5.5V100—nst CS Minimum CS LOW Time 1.8V ≤ Vcc < 2.5V250—ns2.5V ≤ Vcc < 4.5V200—ns4.5V ≤ Vcc ≤5.5V200—nst CSS CS Setup Time Relative to SK 1.8V ≤ Vcc < 2.5V200—ns2.5V ≤ Vcc < 4.5V100—ns4.5V ≤ Vcc ≤5.5V50—nst DIS Din Setup Time Relative to SK 1.8V ≤ Vcc < 2.5V100—ns2.5V ≤ Vcc < 4.5V50—ns4.5V ≤ Vcc ≤5.5V50—nst CSH CS Hold Time Relative to SK 1.8V ≤ Vcc < 2.5V0—ns2.5V ≤ Vcc < 4.5V0—ns4.5V ≤ Vcc ≤5.5V0—nst DIH Din Hold Time Relative to SK 1.8V ≤ Vcc < 2.5V50—ns2.5V ≤ Vcc < 4.5V50—ns4.5V ≤ Vcc ≤5.5V50—nst PD1Output Delay to “1”AC Test 1.8V ≤ Vcc < 2.5V—400ns2.5V ≤ Vcc < 4.5V—200ns4.5V ≤ Vcc ≤5.5V—100nst PD0Output Delay to “0”AC Test 1.8V ≤ Vcc < 2.5V—400ns2.5V ≤ Vcc < 4.5V—200ns4.5V ≤ Vcc ≤5.5V—100nst SV CS to Status Valid AC Test 1.8V ≤ Vcc < 2.5V—400ns2.5V ≤ Vcc < 4.5V—200ns4.5V ≤ Vcc ≤5.5V—200nst DF CS to Dout in 3-state AC Test, CS=VIL 1.8V ≤ Vcc < 2.5V—100ns2.5V ≤ Vcc < 4.5V—100ns4.5V ≤ Vcc ≤5.5V—100nst WP Write Cycle Time 1.8V ≤ Vcc < 2.5V—10ms2.5V ≤ Vcc < 4.5V—5ms4.5V ≤ Vcc ≤5.5V—5ms Notes:1. C L = 100pFIS93C56A IS93C66A ISSI®AC ELECTRICAL CHARACTERISTICST A = –40°C to +125°C for AutomotiveSymbol Parameter Test Conditions Min.Max.Unitf SK SK Clock Frequency 2.5V ≤ Vcc < 4.5V02Mhz≤ Vcc ≤ 5.5V03Mhz4.5Vt SKH SK HIGH Time 2.5V ≤ Vcc < 4.5V200—ns≤ Vcc ≤ 5.5V200—ns4.5Vt SKL SK LOW Time 2.5V ≤ Vcc < 4.5V200—ns≤ Vcc ≤ 5.5V100—ns4.5Vt CS Minimum CS LOW Time 2.5V ≤ Vcc < 4.5V200—ns≤ Vcc ≤ 5.5V200—ns4.5Vt CSS CS Setup Time Relative to SK 2.5V ≤ Vcc < 4.5V100—ns≤ Vcc ≤ 5.5V50—ns4.5Vt DIS Din Setup Time Relative to SK 2.5V ≤ Vcc < 4.5V50—ns≤ Vcc ≤ 5.5V50—ns4.5Vt CSH CS Hold Time Relative to SK 2.5V ≤ Vcc < 4.5V0—ns≤ Vcc ≤ 5.5V0—ns4.5Vt DIH Din Hold Time Relative to SK 2.5V ≤ Vcc < 4.5V50—ns≤ Vcc ≤ 5.5V50—ns4.5Vt PD1Output Delay to “1”AC Test 2.5V ≤ Vcc < 4.5V—200ns≤ Vcc ≤ 5.5V—100ns4.5Vt PD0Output Delay to “0”AC Test 2.5V ≤ Vcc < 4.5V—200ns≤ Vcc ≤ 5.5V—100ns4.5Vt SV CS to Status Valid AC Test 2.5V ≤ Vcc < 4.5V—200ns≤ Vcc ≤ 5.5V—200ns4.5Vt DF CS to Dout in 3-state AC Test, CS=VIL 2.5V ≤ Vcc < 4.5V—100ns≤ Vcc ≤ 5.5V—100ns4.5Vt WP Write Cycle Time 2.5V ≤ Vcc < 4.5V—5ms≤ Vcc ≤ 5.5V—5ms4.5VNotes:1. C L = 100pF8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C56A IS93C66A ISSI®AC WAVEFORMSFIGURE 2. SYNCHRONOUS DATA TIMINGNotes:To determine address bits An-A0 and data bits Dm-Do, see Instruction Set for the specific device.IS93C56A IS93C66A ISSI®AC WAVEFORMSFIGURE 4. WRITE ENABL E (WEN) CYCL E TIMINGNotes:1. After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status(D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.2. To determine address bits A n-A0 and data bits D m-D0, see Instruction Set for the specific device.10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.AIS93C56A IS93C66A ISSI®AC WAVEFORMSFIGURE 6. WRITE AL L (WRAL L) CYCL E TIMINGIntegrated Silicon Solution, Inc. — — 1-800-379-477411 Rev.A05/02/06IS93C56A IS93C66A ISSI®AC WAVEFORMSFIGURE 8. ERASE (REGISTER ERASE) CYCLE TIMINGNote for Figures 8 and 9:After the completion of the instruction (D OUT is in READY status) then it may perform another instruction. If device is in BUSY status (D OUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction.12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.A05/02/06IS93C56A IS93C66A ISSI®ORDERING INFORMATIONIndustrial Range: -40ºC to +85ºCVoltage Range Order Part No.Package1.8V to 5.5V IS93C56A-2PI300-mil Plastic DIPIS93C56A-2GRI SOIC JEDECIS93C56A-2ZI169-mil TSSOP1.8V to 5.5V IS93C66A-2PI300-mil Plastic DIPIS93C66A-2GRI SOIC JEDECIS93C66A-2ZI169-mil TSSOP2.5V to 5.5V IS93C56A-3PI300-mil Plastic DIPIS93C56A-3GRI SOIC JEDEC2.5V to 5.5V IS93C66A-3PI300-mil Plastic DIPIS93C66A-3GRI SOIC JEDECAutomotive Range: -40ºC to +125ºC, Lead-freeVoltage Range Order Part No.Package2.5V to 5.5V IS93C56A-3PLA3300-mil Plastic DIPIS93C56A-3GRLA3SOIC JEDECIS93C56A-3ZLA3169-mil TSSOP2.5V to 5.5V IS93C66A-3PLA3300-mil Plastic DIPIS93C66A-3GRLA3SOIC JEDECIS93C66A-3ZLA3169-mil TSSOPIndustrial Range: -40ºC to +85ºC, Lead-freeVoltage Range Order Part No.Package1.8V to 5.5V IS93C56A-2PLI300-mil Plastic DIPIS93C56A-2GRLI SOIC JEDECIS93C56A-2ZLI169-mil TSSOP1.8V to 5.5V IS93C66A-2PLI300-mil Plastic DIPIS93C66A-2GRLI SOIC JEDECIS93C66A-2ZLI169-mil TSSOPIntegrated Silicon Solution, Inc. — — 1-800-379-477413 Rev.A05/02/06PACKAGING INFORMATIONISSI®Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.D 02/14/03without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.300-mil Plastic DIP Package Code: N,PPACKAGING INFORMATIONISSI®Integrated Silicon Solution, Inc. — 1-800-379-47742Rev.C 10/03/01150-mil Plastic SOP Package Code: G, GRIntegrated Silicon Solution, Inc.PACKAGING INFORMATIONISSI®Thin Shrink Small Outline TSSOP Package Code: Z (8 pin, 14 pin)Rev B 02/01/02。