Lecture21_Matching_2up
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EECS240 –Spring 2010Lecture 21: Matching
Elad AlonDept. of EECS
EECS240Lecture 212Offset•To achieve zero offset, comparator devices must be perfectly matched to each other
•How well-matched can the devices be made?•Not arbitrary –direct function of design choices
Vi+Vi-EECS240Lecture 213
Device Mismatch Categories•Die-to-die•All devices on same chip (or wafer) have same characteristics
•Within die (long-range)•All devices within certain region have same characteristics
•Local (short-range)•Every device different, random•Usually most important source of mismatch
EECS240Lecture 214Sources of Local Variation•Deterministic sources:•Local poly density•Sub-90nm: stress, litho interactions, …
•Random sources:•Dopantfluctuations•Line-edge roughness•Oxide traps
•Focus our modeling on random variations•Deterministic handled with good layout practicesEECS240Lecture 215References•M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, "Matching properties of MOS transistors," IEEE JSSC,vol. 24, pp. 1433 -1439, Oct. 1989•Mismatch model•Statistical data for 2.5µm CMOS
•J. A. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, and H. E. Maes, “An easy-to-use mismatch model for the MOS transistor,”IEEE JSSC, vol. 37, pp. 1056 -1064, Aug. 2002•0.18µm CMOS data
EECS240Lecture 216Mismatch Statistics•Total mismatch set by composite of many single, independent events•Correlation distance << device dimensions•E.g., number of dopantatoms implanted into the channel
•Individual effects are small: linear superposition holds
•ÆMismatch is zero mean, Gaussian distributionEECS240Lecture 217Parameter Mismatch Model()2222
xPPDSWLAP+=∆
σ
()2: variance of P: active gate area: distance between device centers: measured area proportionality constant: measured distance proportionalityconstant, : xPPP
WLDAS
σ∆
0 for "good" layout≅
EECS240Lecture 218VTMismatch()2222T
T
V
TVx
A
VSDWLσ∆=+
,,2.5µm CMOS process:30 mV m35 mV mTTVNMOSVPMOS
A
Aµ
µ≅
≅
•Mismatch in VTbetween two identical devices:
•Often largest source ofoffsetEECS240Lecture 219Drain Bias, VDS
∆VTlargely independent of VDS
EECS240Lecture 2110Back-Gate Bias, VSB
•Mismatch can depend on VSB
•Why?EECS240Lecture 2111
Current Matching, ∆ID/ID
Strong bias dependence (we knew that already)
EECS240Lecture 2112Current FactorLWCox
µβ=EECS240Lecture 2113Sources of βMismatch•Mobility variations•E.g., due to dopantvariations, random defects
•Oxide thickness variation•Usually very well-controlled
•Edge roughness
EECS240Lecture 2114Edge ModelFor:Simplifies to:
()()()()()2222222222
nnoxoxCCLLW
W
µµσσσσββσ
+++=
()2222
222222
DSWLAWLALWAWL
A
oxCWL
β
µ
β
βσ++++=
()()WLLW1 and 122∝∝σσEECS240Lecture 2115
Orientation Effects•Si and transistors are not (perfectly) isotropic
•Ækeep direction ofcurrent flow same!
EECS240Lecture 2116Distance EffectEECS240Lecture 2117
Process Dependence•AVttends to scale with technology
•Proportional to tox
•Also depends on doping level
EECS240Lecture 21180.18 µm CMOSEECS240Lecture 2119
Current Matching
EECS240Lecture 2120Voltage MatchingEECS240Lecture 2121“Golden Rule”of Layout for Matching
•Everything you can think of might matter•Even whether or not there is metal above the devices
•How to avoid systematic errors?
Ref:A. Hastings, “The art of analog layout,”Prentice Hall, 2001
EECS240Lecture 2122Common Centroid Layout•Cancels lineargradients•Required for moderate matchingEECS240Lecture 2123
Simulating Mismatch•Brute force: Monte Carlo•HSPICE “throws the dice”…
EECS240Lecture 2124Simulating Mismatch