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74F02LMQB中文资料

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54F/74F02

Quad2-InputNORGate

GeneralDescription

Thisdevicecontainsfourindependentgates,eachofwhichperformsthelogicNORfunction.

OrderingCode:SeeSection0

CommercialMilitaryPackagePackageDescription

Number

74F02PCN14A14-Lead(0.300"Wide)MoldedDual-In-Line

54F02DM(Note2)J14A14-LeadCeramicDual-In-Line

74F02SC(Note1)M14A14-Lead(0.150"Wide)MoldedSmallOutline,JEDEC

74F02SJ(Note1)M14D14-Lead(0.300"Wide)MoldedSmallOutline,EIAJ

54F02FM(Note2)W14B14-LeadCerpack

54F02LM(Note2)E20A20-LeadCeramicLeadlessChipCarrier,TypeC

Note1:Devicesalsoavailablein13"reel.Usesuffix=SCXandSJX.Note2:Militarygradedevicewithenvironmentalandburn-inprocessing.Usesuffix=DMQB,FMQBandLMQB.LogicSymbolConnectionDiagrams

TRI-STATE®isaregisteredtrademarkofNationalSemiconductorCorporation.IEEE/IEC

DS009455-3PinAssignmentforDIP,SOICandFlatpak

DS009455-2PinAssignmentforLCC

DS009455-1December199454F/74F02

Quad

2-Input

NOR

Gate54F/74F02

©1997NationalSemiconductorCorporationDS009455www.national.com1

PrintDate=1997/09/03PrintTime=06:50:3711240ds009455Rev.No.1cmservProof1DSXXX元器件交易网www.cecb2b.comUnit

Loading/Fan

OutSeeSection0forU.L.definitions

54F/74F

PinNamesDescriptionU.L.InputIIH/IILHIGH/LOWOutputIOH/IOLAn,BnInputs1.0/1.020µA/−0.6mA

OnOutputs50/33.3−1mA/20mA

PrintDate=1997/09/03PrintTime=06:50:3711240ds009455Rev.No.1cmservProof2DSXXX

www.national.com2元器件交易网www.cecb2b.comAbsolute

Maximum

Ratings

(Note

3)

IfMilitary/Aerospacespecifieddevicesare

required,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.

StorageTemperature−65˚Cto+150˚CAmbientTemperatureunderBias−55˚Cto+125˚CJunctionTemperatureunderBias−55˚Cto+175˚CPlastic−55˚Cto+150˚CVCCPinPotentialtoGroundPin−0.5Vto+7.0VInputVoltage(Note4)−0.5Vto+7.0VInputCurrent(Note4)−30mAto+5.0mAVoltageAppliedtoOutputinHIGHState(withVCC=0V)StandardOutput−0.5VtoVCCTRI-STATE®Output−0.5Vto+5.5VCurrentAppliedtoOutputinLOWState(Max)twicetheratedIOL(mA)

RecommendedOperating

Conditions

FreeAirAmbientTemperatureMilitary−55˚Cto+125˚CCommercial0˚Cto+70˚CSupplyVoltageMilitary+4.5Vto+5.5VCommercial+4.5Vto+5.5VNote3:Absolutemaximumratingsarevaluesbeyondwhichthedevicemaybedamagedorhaveitsusefullifeimpaired.Functionaloperationundertheseconditionsisnotimplied.Note4:Eithervoltagelimitorcurrentlimitissufficienttoprotectinputs.

DCElectricalCharacteristics

SymbolParameter54F/74FUnitsVCCConditions

MinTypMax

VIHInputHIGHVoltage2.0VRecognizedasaHIGHSignal

VILInputLOWVoltage0.8VRecognizedasaLOWSignal

VCDInputClampDiodeVoltage−1.2VMinIIN=−18mA

VOHOutputHIGH54F10%VCC2.5IOH=−1mA

Voltage74F10%VCC2.5VMinIOH=−1mA

74F5%VCC2.7IOH=−1mA

VOLOutputLOW54F10%VCC0.5VMinIOL=20mA

Voltage74F10%VCC0.5IOL=20mA

IIHInputHIGH54F20.0µAMaxVIN=2.7V

Current74F5.0

IBVIInputHIGHCurrent54F100µAMaxVIN=7.0V

BreakdownTest74F7.0

ICEXOutputHIGH54F250µAMaxVOUT=VCCLeakageCurrent74F50

VIDInputLeakage74F4.75V0.0IID=1.9µA

TestAllotherpinsgrounded

IODOutputLeakage74F3.75µA0.0VIOD=150mV

CircuitCurrentAllotherpinsgrounded

IILInputLOWCurrent−0.6mAMaxVIN=0.5V

IOSOutputShort-CircuitCurrent−60−150mAMaxVOUT=0V

ICCHPowerSupplyCurrent3.75.6mAMaxVO=HIGH

ICCLPowerSupplyCurrent8.713.0mAMaxVO=LOW

3www.national.com

PrintDate=1997/09/03PrintTime=06:50:3911240ds009455Rev.No.1cmservProof3元器件交易网www.cecb2b.comAC

ElectricalCharacteristicsSeeSection0forWaveformsandLoadConfigurations

74F54F74F

TA=+25˚CTA,VCC=MilTA,VCC=ComFig.

SymbolParameterVCC=+5.0VCL=50pFCL=50pFUnitsNo.

CL=50pF

MinTypMaxMinMaxMinMax

tPLHPropagationDelay2.54.45.52.57.52.56.5nskk-kk

tPHLAn,BntoOn1.53.24.31.56.51.55.3

PrintDate=1997/09/03PrintTime=06:50:4011240ds009455Rev.No.1cmservProof4BookExtractEndDSXXX

DSXXX

www.national.com4元器件交易网www.cecb2b.comOrdering

Information

The

device

numberisusedtoformpart

ofasimplifiedpurchasingcodewherethepackagetypeandtemperaturerangearede-finedasfollows:

PhysicalDimensionsinches(millimeters)unlessotherwisenotedDS009455-4

20-LeadCeramicLeadlessChipCarrier(L)NSPackageNumberE20A

5www.national.com

PrintDate=1997/09/03PrintTime=06:50:4011240ds009455Rev.No.1cmservProof5BookExtractEnd元器件交易网www.cecb2b.comPhysical

Dimensions

inches

(millimeters)

unlessotherwisenoted(Continued)

14-Lead

CeramicDualIn-LinePackage(D)NSPackageNumberJ14A

14-Lead(0.150"Wide)MoldedSmallOutlinePackage,JEDEC(S)NSPackageNumberM14A

PrintDate=1997/09/03PrintTime=06:50:4111240ds009455Rev.No.1cmservProof6www.national.com6元器件交易网www.cecb2b.com

合集下载

74F822资料

74F822资料

元器件交易网

Philips SemiconductorsProduct specification

74F821/822/823/824/825/826Bus interface registers

21996 Jan 05853-1304 1619574F82110-bit bus interface register, non-inverting (3-State)

74F82210-bit bus interface register, inverting (3-State)

74F8239-bit bus interface register, non-inverting (3-State)

74F8249-bit bus interface register, inverting (3-State)

74F8258-bit bus interface register, non-inverting (3-State)

74F8268-bit bus interface register, inverting (3-State)

FEATURES

•High speed parallel registers with positive edge-triggered D-type

flip-flops

•High performance bus interface buffering for wide data/address

paths or busses carrying parity

•High impedance PNP base inputs for reduced loading (20µA in

high and low states)

•IIL is 20µA vs 1000µA for AM29821 series

•Buffered control inputs to reduce AC effects

74HC02DTR2G中文资料

74HC02DTR2G中文资料

© Semiconductor Components Industries, LLC, 2007March, 2007 − Rev. 11Publication Order Number:74HC02/D74HC02

Quad 2−Input NOR Gate

High−Performance Silicon−Gate CMOS

The 74HC02 is identical in pinout to the LS02. The device inputs are

compatible with standard CMOS outputs; with pullup resistors, they

are compatible with LSTTL outputs.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 40 FETs or 10 Equivalent Gates

•These are Pb−Free Devices

LOGIC DIAGRAM1Y12A1PIN 14 = VCCPIN 7 = GND3B1

Y4Y = A + B4Y25A2

6B2

10Y38A3

54F651SDMQB资料

54F651SDMQB资料

54F󰁋74F651

󰀣

54F󰁋74F652

Transceivers󰁋Registers

December1994

54F󰁋74F651󰀣54F󰁋74F652

Transceivers󰁋Registers

GeneralDescription

Thesedevicesconsistofbustransceivercircuitswith

D-typeflip-flops󰀷andcontrolcircuitryarrangedformulti-

plexedtransmissionofdatadirectlyfromtheinputbusor

frominternalregisters󰀟DataontheAorBbuswillbe

clockedintotheregistersastheappropriateclockpingoes

toHIGHlogiclevel󰀟OutputEnablepins(OEAB󰀷OEBA)are

providedtocontrolthetransceiverfunction󰀟Features

YIndependentregistersforAandBbuses

YMultiplexedreal-timeandstoreddata

YChoiceofnon-invertingandinvertingdatapaths

󰁚’F651inverting

󰁚’F652non-inverting

YGuaranteed4000VminimumESDprotection

CommercialMilitaryPackagePackageDescriptionNumber

74F651SPCN24C24-Lead(0󰀟300󰀂Wide)MoldedDual-In-Line

54F651SDM(Note2)J24F24-Lead(0󰀟300󰀂Wide)CeramicDual-In-Line

74LV4052中文资料

74LV4052中文资料

元器件交易网

Philips SemiconductorsProduct specification

74LV4052Dual 4-channel analog multiplexer/demultiplexer

21998 Jun 23853-1999 19618FEATURES

•

Optimized for low voltage applications: 1.0 to 6.0 V

•

Accepts TTL input levels between V

CC = 2.7 V and V

CC = 3.6 V

•

Low typ “ON” resistance:

60 W at V

cc – V

EE = 4.5 V

90 W at V

cc – V

EE = 3.0 V

145 Wat V

cc – V

EE = 2.0 V

•

Logic level translation: to enable 3 V logic to communicate with ± 3

V analog signals

•

Typical “break before make” built in

•

Analog/Digital multiplexing and demultiplexing

•

Signal gating

•

Output capability: non-standard

•

I

CC category: MSIDESCRIPTION

The 74LV4052 is a low-voltage CMOS device and is pin and

function compatible with the 74HC/HCT4052.

The 74LV4052 is a dual 4-channel analog multiplexer/demultiplexer

with a common select logic. Each multiplexer has four independent