54ffc9ad498ef6cbeda141d0

如果一个密码系统的加密密钥和解密密钥不同，并且 由加密密钥推导出解密密钥(或者由解密密钥推导出 加密密钥)是计算上不可行的，则称该密码系统采用 的是非对称密码体制。采用非对称密码体制的每个用 户都有一对选定的密钥，其中一个是可以公开的，一 个由用户自己秘密保存。 非对称密码体制的出现是现代密码学研究的一项重大 突破，它的主要优点是可以适应开放性的使用环境， 密钥管理问题相对简单，可以方便、安全地实现数字 签名和验证。但它的加/解密速度较慢(例如目前最快 的RSA芯片的加/解密速度为2Mb/s)，而且其保密强度 目前还远远达不到对称密码体制的水平。
（3）有限域的加法运算 在有限域的多项式表示中，GF(28)上两个元素的和仍 然是一个次数不超过7的多项式，其系数等于两个元 素对应系数的模2加（比特异或）。 由于AES算法中的字节被看作有限域上的元素，因此 有限域中的加法运算相当于对两个字节进行异或操作。 例如：在GF(28)域中，16进制数57和83所表示的多项 式的为： (x6+x4+x2+x+1)+(x7+x+1)=x7+x6+x4+x2 用二进制表示为 {01010111}⊕{10000011} = {11010100} 用十六进制表示为 {57}⊕{83} = {d4}
Li-1 Ri-1
扩展置换
ki
S-盒代替
P-盒置换
Li
Ri
பைடு நூலகம்16
DES的子密钥产生流程图
k 64位 密钥置换1 56位 28位 C0 循环左移 C1 28位 D0 循环左移 D1 密钥置换2 循环左移 C2 循环左移 D2 密钥置换2 循环左移 C16 循环左移 D16 密钥置换2 k16 (48位) k2 (48位) k1 (48位)

牧马人的epon设备（插拔光纤时onu认证的报文）1、扩展发现OAMsend OAM:pkt len = 50, port = 0============================================================================== 00194264: 01 80 c2 00 00 02 00 1a ec 01 03 39 88 09 03 00 ; ...........9.... 00194274: 50 00 01 10 01 00 00 00 0e 05 ee 00 13 25 00 00 ; P............%.. 00194284: 00 00 02 10 01 00 00 00 0f 05 ee 00 13 25 00 00 ; .............%.. 00194294: 00 00 ; ................[000019ef:IGMP:0] mc tmr heartbeat[000019ef:APP:5] LOOPDETECT_TIMER_EXPIRED:port(255)[000019ef:APP:5] open port 1 period time out[000019ef:APP:3] vlan flooding ,dport 1, vlan count 0[000019ef:APP:5] open port 2 period time out[000019ef:APP:3] vlan flooding ,dport 2, vlan count 0[000019ef:APP:5] open port 3 period time out[000019ef:APP:3] vlan flooding ,dport 3, vlan count 0[000019ef:APP:5] open port 4 period time out[000019ef:APP:3] vlan flooding ,dport 4, vlan count 0[00001a0d:PTP:1] The tod_info is: $GPZDA001964000119700019.[00001a0d:PTP:0] update sys time 64633442256[00001a0d:PTP:4] trigger 1pps signal at time 65000000000(0xd224d4a0) [00001a0d:PTP:4] trigger tod info at time 65001000000(0xd225c8c4) Rcv OAM:pkt len = 60, port = 0============================================================================== 0014f068: 01 80 c2 00 00 02 00 e0 8e 88 01 00 88 09 03 00 ; ................ 0014f078: 50 00 01 10 01 00 00 00 0f 05 ee 00 13 25 00 00 ; P............%.. 0014f088: 00 00 02 10 01 00 00 00 0e 05 ee 00 13 25 00 00 ; .............%.. 0014f098:00 00 fe 07 11 11 11 01 21 00 00 00 ; ........!.......oam_ctc_build_pdu_infoLength=7+4x 07是最小值0x01:支持OAM扩展0x00:不支持OAM扩展ONU支持电信的版本号send OAM:pkt len = 57, port = 0==============================================================================001941d4: 01 80 c2 00 00 02 00 1a ec 01 03 39 88 09 03 00 ; ...........9....001941e4: 50 00 01 10 01 00 00 00 0e 05 ee 00 13 25 00 00 ; P............%..001941f4: 00 00 02 10 01 00 00 00 0f 05 ee 00 13 25 00 00 ; .............%.. 00194204: 00 00 fe 07 11 11 11 01 21 ; ........!.......[00001a33:APP:3] app_pkt_rx len 64 type 10 port 0[00001a37:OAM:0] oam_ind_oampdu(2、扩展的组织特定（Organization Specific）OAMPDU消息概述2.1 扩展的组织特定（Organization Specific）OAMPDU消息结构及定义扩展的组织特定OAMPDU消息（即Organization Specific OAMPDU）应符合IEEE 802.3-2008 Clause57.4.3.6中关于OAM扩展的规定。

©1997DATA SHEETThe mark • shows major revised points.Document No.M12666EJ5V0DS00 (5th edition)Date Published July 1998 NS CP (K)Printed in JapanThe information in this document is subject to change without notice.DescriptionThe MC-454AD645 is a 4,194,304 words by 64 bits synchronous dynamic RAM module on which 16 pieces of 16M SDRAM: µPD4516821A are assembled.This module provides high density and large quantities of memory in a small space without utilizing the surface-mounting technology on the printed circuit board.Decoupling capacitors are mounted on power supply line for noise reduction.Features• 4,194,304 words by 64 bits organization • Clock frequency and clock access timeFamily/CAS latencyClock frequencyClock access timePower consumption (MAX.)(MAX.)(MAX.)Active Standby MC-454AD645F-A80CL = 3125 MHz 6 ns 5,414 mW 115.2 mW CL = 283 MHz 7 ns 4,406 mW (CMOS level input)MC-454AD645F-A10CL = 3100 MHz 7 ns 4,550 mW CL = 277 MHz 8 ns 3,686 mW MC-454AD645F-A12CL = 383 MHz 8 ns 3,974 mW CL = 267 MHz 9 ns 3,110 mW MC-454AD645FA-A10BCL = 3100 MHz 7 ns 3,686 mW CL = 277 MHz8 ns3,398 mW• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface• Possible to assert random column address in every cycle • Dual internal banks controlled by BA0 (Bank Select)• Programmable burst-length: 1, 2, 4, 8 and full page • Programmable wrap sequence (sequential / interleave)• Programmable /CAS latency (2, 3)• Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • All DQs have 10 Ω ± 10 % of series resistor • Single 3.3 V ± 0.3 V power supply • LVTTL compatible• 2,048 refresh cycles / 32 ms• Burst termination by Burst Stop command and Precharge command • 168-pin dual in-line memory module (Pin pitch = 1.27 mm)• Unbuffered type • Serial PD2Ordering InformationPart numberClock frequency(MAX.)PackageMounted devicesMC-454AD645F-A80125 MHz MC-454AD645F-A10100 MHz MC-454AD645F-A1283 MHz 16 pieces of µPD4516821AG5(400 mil TSOP (II))[Double side]MC-454AD645FA-A10B100 MHz168-pin Dual In-line Memory Module (Socket Type)Edge connector : Gold plated 29.21 mm (1.15 inch) height16 pieces of µPD4516821AG5 (Rev. P)(400 mil TSOP (II))[Double side]3Pin Configuration168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)[MC-454AD645F, MC-454AD645FA]A0 - A10:Address Inputs [Row : A0 - A10, Column : A0 - A8]BA0 (A11):SDRAM Bank Select DQ0 - DQ63:Data Inputs / Outputs CLK0 - CLK3:Clock Input CKE0, CKE1:Clock Enable Input /CS0 - /CS3:Chip Select Input /RAS :Row Address Strobe /CAS :Column Address Strobe /WE :Write EnableDQMB0 - DQMB7:DQ Mask EnableSA0 - SA2:Address Input for EEPROM SDA :Serial Data I/O for PD SCL :Clock Input for PD V CC :Power Supply V SS :Ground NC: No Connection/xxx indicates active low signal.SS SS SS SS (A11)SS SS SS SS SS V V V V V V V V V4Block DiagramA0 - A10A0 - A10: D0 - D15V CCD0 - D15D0 - D15SCLSDASA0SA1SA2A11: D0 - D15/RAS /RAS: D0 - D15/CAS /CAS: D0 - D15CKE: D0 - D7CLK0ΩCLK1CLK : D2, D6CLK : D3, D7V SSRemarks 1.The value of all resistors is 10 Ω except CKE1.2.D0 - D15 : µPD4516821A (1M words × 8 bits × 2 banks)5Electrical Specifications• All voltages are referenced to V SS (GND).• After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device operation is achieved.Absolute Maximum RatingsParameterSymbol ConditionRating Unit Voltage on power supply pin relative to GND V CC –1.0 to +4.6V Voltage on input pin relative to GND V T –1.0 to +4.6V Short circuit output current I O 50mA Power dissipationP D 16W Operating ambient temperature T A 0 to +70°C Storage temperatureT stg–55 to +125°CCaution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.Recommended Operating ConditionsParameterSymbol ConditionMIN.TYP.MAX.Unit Supply voltage V CC 3.0 3.33.6V High level input voltageV IHMC-454AD645F 2.0 4.6VMC-454AD645FA2.0V CC +0.3Low level input voltage V IL −0.3+0.8V Operating ambient temperatureT A70°C Capacitance (T A = 25 °C, f = 1 MHz)ParameterSymbol Test conditionMIN.TYP.MAX.Unit Input capacitanceC I1A0 - A10, BA0 (A11), /RAS, /CAS, /WE 80pFC I2CLK0 - CLK336C I3CKE0, CKE150C I4/CS0 - /CS334C I5DQMB0 - DQMB715Data input / output capacitance C I/ODQ0 - DQ63MC-454AD645F 15pF MC-454AD645FA205DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)[MC-454AD645F]Parameter Symbol Test condition Grade MIN.MAX.Unit Notes Operating current I CC1Burst length = 1/CAS latency= 2-A801,024mA1t RC≥t RC (MIN.), I O = 0mA-A10944-A12944/CAS latency= 3-A801,064-A10984-A12984Precharge standby current in I CC2P CKE ≤ V IL (MAX.), t CK = 15ns48mApower down mode I CC2PS CKE ≤ V IL (MAX.), t CK = ∞32Precharge standby current in I CC2N CKE ≥V IH (MIN.), t CK = 15ns, /CS≥V IH (MIN.),400mAnon power down mode Input signals are changed one time during 30ns.I CC2NS CKE ≥V IH (MIN.), t CK = ∞ ,96Input signals are stable.Active standby current in I CC3P CKE ≤ V IL (MAX.), t CK = 15ns48mApower down mode I CC3PS CKE ≤ V IL (MAX.), t CK = ∞32Active standby current in I CC3N CKE ≥V IH (MIN.), t CK = 15ns, /CS ≥V IH (MIN.),448mAnon power down mode Input signals are changed one time during 30ns.I CC3NS CKE ≥V IH (MIN.), t CK = ∞ ,160Input signals are stable.Operating current I CC4t CK≥t CK (MIN.),/CAS latency = 2-A801,224mA2 (Burst mode)I O = 0mA-A101,024-A12864/CAS latency = 3-A801,504-A101,264-A121,104Refresh current I CC5t RC = 100 ns, t CK = MIN.944mA3 Self refresh current I CC6CKE ≤ 0.2V32mAInput leakage current I I (L)V I = 0 to 3.6V,All other pins not under test = 0 V–80+80µAInput leakage current (CKE1)–500+500Output leakage current I O (L)D OUT is disabled, V O = 0 to 3.6V–10+10µAHigh level output voltage V OH I O = –2.0mA 2.4VLow level output voltage V OL I O = +2.0mA0.4VNotes 1.I CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, I CC1 is measured on condition that addresses are changed only one time during t CK (MIN.).2.I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Inaddition to this, I CC4 is measured on condition that addresses are changed only one time during t CK (MIN.).3.I CC5 is measured on condition that addresses are changed only one time during t CK (MIN.).6[MC-454AD645FA]Parameter Symbol Test condition Grade MIN.MAX.Unit Notes Operating current I CC1Burst length = 1/CAS latency= 2-A10B944mA1t RC≥t RC (MIN.), I O = 0mA/CAS latency= 3-A10B984Precharge standby current in I CC2P CKE ≤ V IL (MAX.), t CK = 15ns48mApower down mode I CC2PS CKE ≤ V IL (MAX.), t CK = ∞32Precharge standby current in I CC2N CKE ≥V IH (MIN.), t CK = 15ns, /CS≥V IH (MIN.),400mAnon power down mode Input signals are changed one time during 30ns.I CC2NS CKE ≥V IH (MIN.), t CK = ∞ ,96Input signals are stable.Active standby current in I CC3P CKE ≤ V IL (MAX.), t CK = 15ns48mApower down mode I CC3PS CKE ≤ V IL (MAX.), t CK = ∞32Active standby current in I CC3N CKE ≥V IH (MIN.), t CK = 15ns, /CS ≥V IH (MIN.),448mAnon power down mode Input signals are changed one time during 30ns.I CC3NS CKE ≥V IH (MIN.), t CK = ∞ ,192Input signals are stable.Operating current I CC4t CK≥t CK (MIN.),/CAS latency = 2-A10B904mA2 (Burst mode)I O = 0mA/CAS latency = 3-A10B1,024Refresh current I CC5t RC = 100 ns, t CK = MIN.944mA3 Self refresh current I CC6CKE ≤ 0.2V16mAInput leakage current I I (L)V I = 0 to 3.6V,All other pins not under test = 0 V–16+16µAInput leakage current (CKE1)–500+500Output leakage current I O (L)D OUT is disabled, V O = 0 to 3.6V–3+3µAHigh level output voltage V OH I O = –4.0mA 2.4VLow level output voltage V OL I O = +4.0mA0.4VNotes 1.I CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, I CC1 is measured on condition that addresses are changed only one time during t CK (MIN.).2.I CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Inaddition to this, I CC4 is measured on condition that addresses are changed only one time during t CK (MIN.).3.I CC5 is measured on condition that addresses are changed only one time during t CK (MIN.).78AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)AC Characteristics Test Conditions •AC measurements assume t T = 1 ns.•Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between V IH and V IL .•If t T is longer than 1 ns, reference level for measuring timing of input signals is V IH (MIN.) and V IL (MAX.).•An access time is measured at 1.4 V.2.0 V 1.4 V 0.8 VCLK2.0 V 1.4 V 0.8 VInputOutput9Synchronous Characteristics [MC-454AD645F]ParameterSymbol-A80-A10-A12UnitNoteMIN.MAX.MIN.MAX.MIN.MAX.Clock cycle time/CAS latency = 3t CK38(125 MHz)10(100 MHz)12(83 MHz)ns /CAS latency = 2t CK212(83 MHz)13(77 MHz)15(67 MHz)ns Access time from CLK/CAS latency = 3t AC3678ns 1/CAS latency = 2t AC2789ns 1CLK high level width t CH 3 3.54ns CLK low level width t CL 3 3.54ns Data-out hold timet OH 333ns 1Data-out low-impedance time t LZ 000nsData-out high-impedance time/CAS latency = 3t HZ3363738ns /CAS latency = 2t HZ2373839ns Data-in setup time t DS 2.0 2.5 3.0ns Data-in hold time t DH 1.0 1.0 1.5ns Address setup time t AS 2.0 2.5 3.0ns Address hold time t AH 1.0 1.0 1.5ns CKE setup time t CKS 2.0 2.5 3.0ns CKE hold timet CKH 1.0 1.0 1.5ns CKE setup time (Power down exit)t CKSP 2.0 2.5 3.0ns Command (/CS0 - /CS3, /RAS, /CAS, /WE,DQMB0 - DQMB7) setup timet CMS2.02.53.0nsCommand (/CS0 - /CS3, /RAS, /CAS, /WE,DQMB0 - DQMB7) hold timet CMH1.01.01.5nsNote 1. Output loadOutput50 pF50 ΩRemark These specifications are applied to the monolithic device.10[MC-454AD645FA]ParameterSymbol-A10BUnitNoteMIN.MAX.Clock cycle time/CAS latency = 3t CK310(100 MHz)ns /CAS latency = 2t CK213(77 MHz)ns Access time from CLK/CAS latency = 3t AC37ns 1/CAS latency = 2t AC28ns 1CLK high level width t CH 3.5ns CLK low level width t CL 3.5ns Data-out hold timet OH 3ns 1Data-out low-impedance time t LZ 0ns Data-out high-impedance time/CAS latency = 3t HZ337ns /CAS latency = 2t HZ238ns Data-in setup time t DS 2.5ns Data-in hold time t DH 1.0ns Address setup time t AS 2.5ns Address hold time t AH 1.0ns CKE setup time t CKS 2.5ns CKE hold timet CKH 1.0ns CKE setup time (Power down exit)t CKSP 2.5ns Command (/CS0 - /CS3, /RAS, /CAS, /WE,DQMB0 - DQMB7) setup timet CMS2.5nsCommand (/CS0 - /CS3, /RAS, /CAS, /WE,DQMB0 - DQMB7) hold timet CMH1.0nsNote 1. Output loadOutput50 pF50 ΩRemark These specifications are applied to the monolithic device.11Asynchronous Characteristics [MC-454AD645F]ParameterSymbol-A80-A10-A12Unit NoteMIN.MAX.MIN.MAX.MIN.MAX.REF to REF/ACT command period t RC 809090ns ACT to PRE command period t RAS 48120,00060120,00060120,000ns PRE to ACT command periodt RP 242630ns Delay time ACT to READ/WRITE command t RCD 242630ns ACT (0) to ACT (1) command period t RRD 162024ns Data-in to PRE command periodt DPL 81012ns Data-in to ACT (REF) command period (Auto precharge)/CAS latency = 3t DAL31CLK +241CLK +261CLK +30ns /CAS latency = 2t DAL21CLK +241CLK +261CLK +30ns Mode register set cycle time t RSC 222CLK Transition time t T 0.530130130ns Refresh timet REF 323232ms[MC-454AD645FA]Parameter Symbol-A10B Unit NoteMIN.MAX.REF to REF/ACT command period t RC90nsACT to PRE command period t RAS60120,000nsPRE to ACT command period t RP26nsDelay time ACT to READ/WRITE command t RCD26nsACT (0) to ACT (1) command period t RRD20nsData-in to PRE command period t DPL10nsData-in to ACT (REF) command/CAS latency = 3t DAL31CLK+26nsperiod (Auto precharge)/CAS latency = 2t DAL21CLK+26nsMode register set cycle time t RSC2CLKTransition time t T130nsRefresh time t REF32ms1213Serial PD[MC-454AD645F](1/2)Byte No.Function DescribedHex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes 0Defines the number of bytes written into serial PD memory80H 10000000128 bytes1Total number of bytes of serial PD memory08H 00001000256 bytes 2Fundamental memory type 04H 00000100SDRAM 3Number of rows 0BH 0000101111 rows 4Number of columns 09H 000010019 columns 5Number of banks 02H 00000010 2 banks 6Data width40H 010******* bits 7Data width (continued)00H 0000000008Voltage interface01H 00000001LVTTL 9CL = 3 cycle time MC-454AD645F-A8080H 100000008 ns MC-454AD645F-A10A0H 1010000010 nsMC-454AD645F-A12C0H 1100000012 ns 10CL = 3 access time MC-454AD645F-A8060H 011000006 ns MC-454AD645F-A1070H 011100007 ns MC-454AD645F-A1280H 100000008 ns 11DIMM configuration type 00H 00000000None 12Refresh rate / type 80H 10000000Normal 13SDRAMwidth08H 00001000×814Error checking SDRAM width 00H 00000000None 15Minimum clock delay 01H 00000001 1 clock 16Burst length supported8FH 100011111, 2, 4, 8, F 17Number of banks on each SDRAM 02H 00000010 2 banks 18/CAS latency supported 06H 000001102, 319/CS latency supported 01H 00000001020/WE latency supported 01H 00000001021SDRAM module attributes 00H 0000000022SDRAM device attributes : General 0EH 0000111023CL = 2 cycle time MC-454AD645F-A80C0H 1100000012 ns MC-454AD645F-A10D0H 1101000013 ns MC-454AD645F-A12F0H 1111000015 ns 24CL = 2 access time MC-454AD645F-A8070H 011100007 ns MC-454AD645F-A1080H 100000008 ns MC-454AD645F-A1290H 100100009 ns 25-2600H14(2/2)Byte No.Function Described Hex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes 27t RP (MIN.)MC-454AD645F-A8018H0001100024nsMC-454AD645F-A101AH0001101026 nsMC-454AD645F-A121EH0001111030 ns 28t RRD (MIN.)MC-454AD645F-A8010H0001000016nsMC-454AD645F-A1014H0001010020nsMC-454AD645F-A1218H0001100024ns 29t RCD (MIN.)MC-454AD645F-A8018H0001100024nsMC-454AD645F-A101AH0001101026 nsMC-454AD645F-A121EH0001111030 ns 30t RAS (MIN.)MC-454AD645F-A8030H0011000048nsMC-454AD645F-A103CH0011110060 nsMC-454AD645F-A123CH0011110060 ns 31Module bank density04H0000010016M bytes 32-6100H0000000062SPD revision01H000000011 63Checksum for MC-454AD645F-A8098H10011000 bytes 0 - 62MC-454AD645F-A10FCH11111100MC-454AD645F-A1268H0110100064-71Manufacture’s JEDEC ID code72Manufacturing location73-90Manufacture’s P/N91-92Revision code93-94Manufacturing date95-98Assembly serial number99-125Mfg specific126Intel specification frequency66H0110011066 MHz 127Intel specification /CAS latency support06H000001102, 315[MC-454AD645FA](1/2)Byte No.Function DescribedHex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes 0Defines the number of bytes written into serial PD memory80H1128 bytes1Total number of bytes of serial PD memory08H1256 bytes2Fundamental memory type 04H 00000100SDRAM 3Number of rows 0BH 0000101111 rows 4Number of columns 09H 000010019 columns 5Number of banks 02H 00000010 2 banks 6Data width40H 010******* bits7Data width (continued)00H 000000008Voltage interface01H 00000001LVTTL 9CL = 3 cycle time MC-454AD645FA-A10B A0H 1010000010 ns 10CL = 3 access time MC-454AD645FA-A10B 70H 011100007 ns 11DIMM configuration type 00H 00000000None 12Refresh rate / type 80H 10000000Normal 13SDRAM width08H 00001000×814Error checking SDRAM width 00H 00000000None 15Minimum clock delay 01H 00000001 1 clock16Burst length supported8FH 100011111, 2, 4, 8, F 17Number of banks on each SDRAM 02H 00000010 2 banks 18/CAS latency supported 06H 000001102, 319/CS latency supported 01H 00000001020/WE latency supported 01H 00000001021SDRAM module attributes 00H 0000000022SDRAM device attributes : General 0EH 0000111023CL = 2 cycle time MC-454AD645FA-A10B D0H 1101000013 ns 24CL = 2 access time MC-454AD645FA-A10B80H 100000008 ns25-2600H16(2/2)Byte No.Function Described Hex Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Notes 27t RP (MIN.)MC-454AD645FA-A10B1AH0001101026 ns 28t RRD (MIN.)MC-454AD645FA-A10B14H0001010020ns 29t RCD (MIN.)MC-454AD645FA-A10B1AH0001101026 ns 30t RAS (MIN.)MC-454AD645FA-A10B3CH0011110060 ns 31Module bank density04H0000010016M bytes 32-6100H0000000062SPD revision01H00000001163Checksum for MC-454AD645FA-A10B FCH11111100 bytes 0 - 6264-71Manufacture’s JEDEC ID code72Manufacturing location73-90Manufacture’s P/N91-92Revision code93-94Manufacturing date95-98Assembly serial number99-125Mfg specific126Intel specification frequency66H0110011066 MHz 127Intel specification /CAS latency support06H000001102, 3Timing ChartRefer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).17Package Drawing[MC-454AD645F, MC-454AD645FA]168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)ITEM MILLIMETERSA1AC 36.83U 4.0 MIN.B 11.43S T 1.27±0.1D1 6.35D2 2.0X 2.54±0.10133.35133.35±0.13G 6.35E 54.61H 1.27 (T.P.)I 8.893.125J L 17.78K 42.18M 29.21±0.13N 4.0 MAX.24.495R 4.0±0.10Y 3.0 MIN.φM168S-50A65-1Z3.0 MIN.P 1.0Q R2.0V 0.25 MAX.W 1.0±0.05D 3.0M19.43M219.78[MEMO] 1819[MEMO]CAUTION FOR HANDLING MEMORY MODULESWhen handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them.When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based ona customer designated "quality assurance program" for a specific application. The recommended applicationsof a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.M4 96. 5。

Evaluation Board For AD7682/89/99/7949PulSAR ® ADCs Preliminary Technical DataEVAL-AD76MUXEDZRev. PrDInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners.O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.FEATURESConverter and Evaluation Development (EVAL-CED1Z) compatibilityVersatile analog signal conditioning circuitry On-board reference, clock oscillator and buffersPC software for control and data analysis of time and frequency domain Stand alone operationGENERAL DESCRIPTIONThe EV AL-AD76MUXCBZ is an evaluation board for the 20 lead PulSAR AD7682, AD7689, AD7699, and AD7949 14-bit and 16-bit PulSAR analog to digital converter (ADC) family. These low power, successive approximation register (SAR)architect-ture ADCs (see Ordering Guide for product list) offer very high performance with up to 500kSPS throughput rate and 4 – 8 channels. The evaluation board is designed to demonstrate the ADC's performance and to provide an easy to understand interface for a variety of system applications. A full description of the AD7682, AD7689, AD7699, and AD7949 is available in at and should be consulted when utilizing this evaluation board.The evaluation board can be operated as a stand alone or can be used in conjunction with the Analog Devices EV AL-CED1Z (CED) USB based data capture board. Since the ADC’s being evaluated are serial interface only, the EV AL-AD76MUXCBZ contains the necessary logic to perform serial to parallel conversion for this interface using the on board FPGA. On-board components include a high precision band gapreference, (ADR435), reference buffers, 8-signal conditioning circuits with an op amp and an FGPA for digital logic. Also included are separate low drop out regulators for supplyingspecial voltages of 1.2V and 7V which are not available from the EV AL-CED1Z.The board interfaces to the EV AL-CED1Z with a 96-pin DIN connector. J1, J2 SMB connectors are provided for the low noise analog signal source for CH0 and CH1 with the remainingchannels (and CH0/1) available on an IDC connector, P1. J3 can be used for providing an external common (COM) or configured for any input channel.Figure 1.Evaluation BoardAnalog InputsSignal conditioningExternal COM (or Input)Header96-Pin EVAL-CED1Z InterfacePOWERINTERFACEEVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 2 of 26TABLE OF CONTENTSFeatures..............................................................................................1 Revision History...............................................................................2 Overview........................................................................................3 Conversion Control......................................................................3 Analog Inputs................................................................................3 Serial Interface..............................................................................3 Reference.......................................................................................3 Power Supplies and Grounding..................................................3 Schematics/PCB Layout...............................................................4 Hardware Setup............................................................................4 Software Installation.....................................................................4 Running the Evaluation Software..............................................5 Setup Screen...................................................................................5 Configuring the ADC...................................................................5 DC Testing - Histogram...............................................................5 AC Testing......................................................................................5 Software Operation.......................................................................8 ADC Configuration......................................................................9 Evaluation Board Schematics and Artwork............................15 Ordering Guide.. (26)LIST OF FIGURESFigure 1.Evaluation Board...............................................................1 Figure 2. Setup Screen......................................................................8 Figure 3. Default CFG.....................................................................9 Figure 4. CGF Enable/Disable Selection.......................................9 Figure 5. Input Configuration/Channel Selection........................9 Figure 6.BW Select............................................................................9 Figure 7. Reference Selection..........................................................9 Figure 8. Context Help, User Controls.........................................10 Figure 9. Histogram Screen...........................................................11 Figure 10. Summary.......................................................................12 Figure 11. FFT Spectrum...............................................................13 Figure 12 .Oscilloscope..................................................................14 Figure 13. Schematic, ADC + Block Diagram.............................15 Figure 14. Schematic, Supplies......................................................16 Figure 15. Schematic, Reference, Buffer, V CM , V BIAS ....................17 Figure 16. Schematic, AnalogCH0-CH3......................................18 Figure 17. Schematic, AnalogCH4-CH7......................................19 Figure 18. Schematic, FPGA..........................................................20 Figure 19. Schematic, 96-Pin Interface........................................21 Figure 20. Top Side Silk-Screen....................................................22 Figure 21. Inner Layer 1.................................................................22 Figure 22. Ground Plane................................................................23 Figure 23. Inner Layer 2.................................................................23 Figure 24.Inner Layer 3..................................................................24 Figure 25. Bottom Layer................................................................24 Figure 26. Bottom Layer. (25)LIST OF TABLESTable 1. Jumper Description............................................................6 Table 2.Test Points............................................................................7 Table 3. Bill of Materials for the Connectors (7)REVISION HISTORYPreliminary Technical DataEVAL-AD76MUXEDZRev. PrD | Page 3 of 26OVERVIEWFigure 1 shows the EV AL-AD76MUXCBZ evaluation board. When used in conjunction with the EV AL-CED1Z, the FPGA, U6, provides the necessary control signals for conversion and buffers the ADC serial output data into 16-bit wide transfers. The evaluation board is a flexible design that enables the user to choose among many different board configurations, analog signal conditioning, reference, and different interfaces for conversion results.In stand alone operation, the FPGA can be used to buffer the 4-wire interface via. P3, or directly to the 4 digital interface test points SDO, SCK, DIN and CNV . For stand alone mode, supply power to the evaluation board as detailed in the Power Supplies and Grounding section below.For FPGA buffered serial interface, supplying power is all that is necessary. For direct serial connection to the ADC, place a jumper across P3-39 and P3-40 as P3-40 pulled low places the FPGA into high impedance.CONVERSION CONTROLConversion start (CNV) controls the sample rate of the ADC and is the only input needed for conversion; all SAR timing is internally generated on the ADC. CNV is generated by the gate array and the frequency is selected with the software.While the ADC is converting, activity is indicated by the green LED, CR1. Operating the software in Burst mode as opposed to Continuous mode, will only light the LED when conversion is taking place.For stand alone operation, connect a low jitter source to eitherP3-8 or CNV .ANALOG INPUTSSMB connectors, J1 and J2, are provided for the ADC input channels IN0 and IN1 (IN0 only on AD7682). These inputs arealso on the IDC connector P1-2 and P1-4. The remaining inputs are also on P1-6 through P1-16 (even pins only). J3 can be configured for providing a common point (COM) for all input signals or for any analog input IN0-IN7. For using J3 as an external common point, remove the solder pad (bottom of PCB) from “COMS to COM” and solder “EXT_COM to COM” as shown below.To configure J3 to drive any of the analog input channels,remove R35 from the left pads (bottom of PCB) and solder it to the rightmost pads.The analog input amplifier circuitry U13 – U20 (see schematic - Figure 13) allows flexible configuration changes such as positive or negative gain, input range scaling, filtering, addition of a DC component, use of different op-amp and supplies. The analog input amplifiers are set as unity gain buffers at the factory. The supplies are selectable with solder pads VDRV- and VDRV+ and are set for the +7V , -5V range.Note that when using the unipolar configuration, COMS (P8) is set to (P8, 2-3) and for bipolar input configuration set to (P8, 1-2) with pin 1 being the leftmost pin.SERIAL INTERFACEThe 3-wire serial interface DIN, SCK, and SDO along with CNV are present on the digital interface test points and FPGAbuffered versions are on the 40-pin IDC connector, P3-2, -4, -6, -8. When connected to the EVAL-CED1Z and stand alone (without P3-39 to P3-40 jumper), signals are present at both locations. With P3-39 to P3-40 connected, these signals are only present at the test points SDO, SCK DIN and CNV .REFERENCEAll of the ADCs for this evaluation board can use a precision trimmed on-chip band gap reference, an on-board precision ADR435 band gap reference, or an external reference connected to the EXTREF test point (TP17). The on-chip reference is enabled or disabled with the software. The on-chip reference can be set for 2.5V or 4.096V outputs and also includes aninternal buffer, useful for external reference applications. When using the on-chip reference, remove the jumper on TP7 since this will overdrive the on-chip reference with the external one. The default configuration is for on-board ADR435 reference with a buffered output (P5 2-3), (P6 1-2) and (P7 1-2). For using an external reference connect to the EXTREF test point (TP17), select a buffer or not with P6 and select if driving the ADC REF directly or using the ADC’s internal reference buffer. When using the internal reference buffer with gain=1, the maximum output is limited to 4.096V (headroom from 5V supply).The default configuration sets the amplifiers output to be at V REF /2 (mid-scale) from the voltage divider at U1B (V BIAS ).POWER SUPPLIES AND GROUNDINGTo attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths by connecting the planes together directly under the converter. Power is supplied to the board through P3 when using with the EV AL-CED1Z. For stand aloneEVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 4 of 26operation, the evaluation board requires three diffeetn supplies and system ground. Connect a supply (7V to 12V) to the analog supplies tests points +12V and +5V A. Connect -5V to the -5V A test point. Connect a supply (+3.3V to +5.5V max) to the FPGA power test point, VDIG.Connect the power supply GNDs to the GND test point at the power supplies section of test points making certain the both analog and digital GNDs are at the same potential.SCHEMATICS/PCB LAYOUTThe EV AL-AD76MUXCBZ is a 6-layer board carefully laid out and tested to demonstrate the specific high accuracyperformance of the ADC. Figure 13 through Figure 19 shows the schematics of the evaluation board. The silkscreens for the PCB are given in Figure 20 and Figure 22.HARDWARE SETUPSystem Requirements• EV AL-AD7682CBZ, EV AL-AD7689CBZ, EV AL-AD7699CBZ, EV AL-AD7949CBZ• Evaluation Converter Evaluation and Development board, EV AL-CED1Z• Enclosed World compatible 7V DC supply • Enlcosed USB to mini USB cable• DC source (low noise for checking different input ranges) • AC source (low distortion)• Band pass filter suitable for 16 or 18 bit testing (value based on signal frequency)• PC operating Windows XP .Proceed to the Software Installation section to install the software. Note: The EV AL-CED1Z board must not be connected to the PC’s USB port until the Software is installed. The 7V DC supply can be connected however to check the board has power (green LED lit).SOFTWARE INSTALLATIONIt is recommended to close all Windows’ applications prior to installing the software.System Requirements• PC operating Windows XP . • USB 2.0 (for CED board) • Administrator privilegesCD-ROM –Navigate to Software\CED Version x.x, double click on setup.exe and follow the instructions on the screen. Ifanother version of Analog Devices PulSAR Evaluation Software is present, it may be necessary to remove this. To remove, click on the Windows “Start” button, select “Control Panel” and “Add or Remove Programs”. When the list populates, navigate to Analog Devices High Resolution sampling ADC’s Evaluation Software or PulSAR Evaluation Software and select Remove. Website DownloadThe software versions are also available from the Analog Devices PulSAR Analog to Digital Converter Evaluation Kitpage. After downloading the software, it is recommended to use the WinZip “Extract” function to extract all of the necessary components as opposed to just clicking on setup.exe in thezipped file. After extracting, click on seteup.exe in the folder created during the extraction and follow the instructions on the screen. If another version exists, it may be necessary to removeas detailed in the above CD-ROM section.USB DriversThe software will also install the necessary USB drivers. After installing the software, power up the CED board and connect to the PC USB 2.0 port. The Windows “Found New Hardware” Wizard will display. Click on Next to install the drivers automatically.When installed properly, Windows displays the following.On some PCs, the Found New hardware Wizard may show up again and if so follow the same procedure to install it properly. The “Device Manager” can be used to verify that the driver was installed successfully.Preliminary Technical DataEVAL-AD76MUXEDZRev. PrD | Page 5 of 26Troubleshooting the InstallIf the driver was not installed successfully the device manager will display a question mark for “Other devices” as Windows does not recognize the CED1Z board.The “USB Device” can be opened to view it’s uninstalled properties.This is usually the case if the software and drivers were installed by a user without administrator privileges. If so, log on as an administrator with full privileges and reinstall the software.RUNNING THE EVALUATION SOFTWAREThe evaluation board includes software for analyzing theAD7682, AD7689, AD7699 and AD7949. The EV AL-CED1Z is required when using the software. The software is used to perform the following tests:• Histogram for determining code transition noise (DC) • Fast Fourier transforms (FFT) for signal to noise ratio (SNR), SNR and distortion (SINAD), total harmonicdistortion (THD) and spurious free dynamic range (SFDR) • Decimation (digital filtering)The software is located at C:\Program Files\Analog Devices\ PulSAR ADC Evaluation Software\Eval PulSAR CED.exe . A shortcut is also added to the Windows “Start” menu under “Analog Devices PulSAR ADC Evaluation Software”, “Eval PulSAR CED”. To run the software, select the program from either location.SETUP SCREENFigure 2 is the setup screen where ADC device selection, test type, input voltage range, sample rate and number of samples are selected.CONFIGURING THE ADCThese ADCs need to be configured through a dedicated SPI compatible serial port. The included SW configures the part to a default configuration. Each of the different configurable parameters are shown in the ADC Configuration section, detailed in Figure 3 to Figure 7.DC TESTING - HISTOGRAMFigure 9 is the histogram screen, which tests the codedistribution for DC input and computes the mean and standard deviation or transition noise. To perform a histogram test, select “Histogram” from the test selection window and click on the “Start” radio button. Note: a histogram test can be performed without an external source since the evaluation board has a buffered V REF /2 source at the ADC input. To test other DC values, apply a source to the J1/J2/P1-x inputs. It is advised to filter the signal to make the DC source noise compatible with that of the ADC.AC TESTINGFigure 11 is the FFT screen, which performs an FFT on the captured data and computes the SNR, SINAD, THD and SFDR. Figure 12 is the time domain representation of the output. To perform an AC test, apply a sinusoidal signal to the evaluation board at the SMB inputs J1 for CH0 and J2 for CH1. Low distortion, better than 100dB, is required to allow trueevaluation of the part. One possibility is to filter the input signal from the AC source. There is no suggested bandpass filter butEVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 6 of 26consideration should be taken in the choice. Furthermore, if using a low frequency bandpass filter when the full-scale input range is more than a few Vpp, it is recommended to use the on board amplifiers to amplify the signal, thus preventing the filter from distorting the input signal.Table 1. Jumper DescriptionJumper Name Default Position Function P5-REFS Reference source selection.REFS to middle pin: uses ADR435 (A1) 5V, 4.096V or 2.5V output. VDD to middle pin: VDD supply is used as a reference. Open: optional source can be connected to TP17/V REF .P6 -BUF Reference buffer selection.BUF to middle pin: buffer selection from P5 with the AD8032-A (U2). NOBUFF to middle pin: use P5 direct (no buffer).P7 REF/REFINREF ADC REF/REFIN input selection.REF to middle pin: external source drives ADC REF pin.REFIN to middle pin: external source drives REFIN, reference buffer input pin Open: When using the on-chip reference.P8 COMSVCM Common channel select.VCM to middle pin: for bipolar mode, selects V REF /2. GND to middle pin: for unipolar operation, selects GND.JP9 5V 5V External reference selection of 5V. JP10 4.096V Open External reference selection of 4.096V. JP11 2.5VOpen External reference selection of 2.5V. SB0-7 BUF SelectBUF Use on-board analog amplifiers (U13 – U20)BUF: use amplifierNO BUF: bypass amplifier- VDRV- -5V Amplifiers (U13-U20) (-) supply. - VDRV+ 7V Amplifiers (U13-U20) (+) supply. - VCCREF 12V ADR435(A1) (+) supply. - VDDR 5V ADC (U7) VDD supply. Must always be the same as VDD. - VDD 5V ADC (U7) VDD supply. - VIO3.3V ADC (U7) VIO interface supply.Preliminary Technical DataEVAL-AD76MUXEDZRev. PrD | Page 7 of 26Table 2.Test PointsTest Point Available Signal Type Description TP8 GND P FPGA power supply GND. TP9 -5VA 1 P Amplifier negative supply. TP10 +5VA 1 P 5V analog supply. TP11 +12VA 1 P 12V analog supply. TP12 GND P Analog supply GND. TP13 VDD P ADC (U7) VDD supply.TP14 VDDR P ADC (U7) VDD supply. Must always be = AVDD above. TP15 VIO P ADC (U7) VIO interface supply. TP17 VREF AI External reference input.TP18 REFAI/O ADC on-chip reference output or external reference input.TP19 REFIN AI/O ADC on-chip band-gap output or external reference input when using on-chip reference buffer.TP20 IN0 AI Analog input for ADC IN0 on both 4 and 8-channel ADCs. TP21 IN1 AI Analog input for channel 1 on 8-channel ADCs only. TP22 COM AI Sets the level on ADC COM; GND or V REF /2. TP24 SDO DO Serial data output from ADC. TP25 SCK DI Serial clock data input to ADC.TP26 DIN DI Serial data input for part configuration. TP27 CNV DI Conversion input to ADC TP71 GND P Analog supply GND. TP76 VDIG 1PFPGA power supply.Table 3. Bill of Materials for the ConnectorsRef Des Connector Type Manf. Part No. J1, J2, J3 RT Angle SMB MalePasternack PE4177P1 0.100 X 0.100 straight IDC header 2X10 3M 2540-6002UB P2 0.100 X 0.100 straight IDC header 2X20 3M 2540-6002UB P432X3 RT PC MOUNT CONNECTOR ERNI 5334021Supplied by EVAL-CED1Z when connected.EVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 8 of 26Figure 2. Setup ScreenThe following details the operation of the software.1. The arrowis used to start the software. When runningis displayed.2.The part to be evaluated is selected here. 3. The controls are used to set:Sample Frequency – units can be used such as 500k (casesensitive) for 500,000 Hz.Capture Mode – This selects between continuous (Cont.) or burst conversion modes. In continuous mode, the ADC is continuously converting. In Burst mode, the ADC is not converting (sample clock held in inactive state) and the conversions begin once the “Single Capture ” or “Continuous Capture ” buttons have been selected.Interface mode – This selects the digital interface to the on-board FPGA.Input Range – this is used to adjust the LSB size in the data field of the plot window.4. These controls are used for saving, printing, help, etc. and are also accessed in the File menu.Save (F5): type – LabView config, allows the currentconfiguration to be saved to a filename.dat file. Useful when changing many of the default controls. To load the saved configuration, use the Load Previous Configuration. Note the location of the .dat file. It is recommended to place into the Support Files directory in the directory where the software was installed.Type – Html, saves the current screen shot to an Html file. Type – Spreadsheet, saves the current data displayed in the chart in a tab delimited spreadsheet. Raw ADC Data is time domain in V or Code, FFT or Decimated is in dB.5. Stop (F10) is used to stops the software. The can also be used to stop the software. RESET is used to reset the EVAL-CED1Z.Preliminary Technical DataEVAL-AD76MUXEDZRev. PrD | Page 9 of 26ADC CONFIGURATIONThe ADC needs to be configured for input configuration,reference, channel to be converted, temperature sensor, and on-chip low pass (LP) filter (optional) for full bandwidth (BW) or ¼ BW . These next figures show the pull down configurations available. Note the default value when the program is started isindicated by the √; or CFG writing enabled, unipolar INn to GND, CH0, full BW , and external reference. Note that after updating the CFG, the first conversion (when using burst mode) will be of the last configuration since the ADC has a 1-depp delay for the CFG. Figure 3 shows the default values.Figure 3. Default CFGFigure 4 details CFG Write Enabled/Disabled. When enabled, the MSB of the CFG is set high. When disabled the MSB is set low thus the remaining 13 bits are ignored.Figure 4. CGF Enable/Disable SelectionFigure 5 details the inputs (IN0-IN7) configuration and channelselection. Refer to the datasheet for more information about the input configure-ations. Note that in the bipolar mode, the input, IN+ and COM (or IN-) must be centered around VREF/2.Figure 5. Input Configuration/Channel SelectionFigure 6 details the bandwidth selection of the 1-pole low passfilter, which can reduce the noise from the amplifier circuit, if desired. Note that the throughout of the converter must also reduce to ¼ of the maximum when setting to ¼ BW .Figure 6.BW SelectFigure 7 details the reference selection. Note that the TEMP sensor can be used with an external reference. The Temp sensor can be used to monitor the temperature of the ADC and the output is straight binary and referenced to the ADC GND. The displayed results should be in Volts format as opposed to Hex.Figure 7. Reference SelectionEVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 10 of 261. To use the on-screen help. Select Help, Show Context Help or click the Help (F1). An example of the Context Help is shown above for the Sample Frequency. Placing the curser on most screen items displays useful help for the particular control or displayed unit.2. These controls are used for axes and zooming panning.Locks the graph axis to automatically fit the data. Uses last axis set by user. ,rescale the axes to theautomatic values. , are used to set axes properties such as format, precision, color, etc.Displays the cursor.Is used For zooming in and out. Is used for panning.Is used to set various graph properties such as graphtype, colors, lines, etc.Preliminary Technical DataEVAL-AD76MUXEDZRev. PrD | Page 11 of 26Figure 9. Histogram Screen1. These radio buttons are used to perform a Single Capture orContinuous Capture of data set in the # of Samples field. The results are displayed in the chart. Note that the results can be displayed as:AOr an(time domain)2., 3.These display the statistics for the X and Y-axes,respectively.EVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 12 of 26Figure 10. SummaryThe charts can be displayed together when the tab is selected.Rev. PrD | Page 13 of 26Figure 11. FFT Spectrum1. Displays the FFT when the Spectrum chart is selected2.,3. Display the data for the X and Y-axes, respectively.EVAL-AD76MUXEDZPreliminary Technical DataRev. PrD | Page 14 of 26Figure 12 .Oscilloscope1. Time domain data can be viewed with the oscilloscope also.Preliminary Technical Data EVAL-AD76MUXEDZ EVALUATION BOARD SCHEMATICS AND ARTWORKFigure 13. Schematic, ADC + Block DiagramRev. PrD | Page 15 of 26EVAL-AD76MUXEDZ Preliminary Technical DataRev. PrD | Page 16 of 26Preliminary Technical Data EVAL-AD76MUXEDZFigure 15. Schematic, Reference, Buffer, V CM, V BIASRev. PrD | Page 17 of 26EVAL-AD76MUXEDZ Preliminary Technical DataRev. PrD | Page 18 of 26Preliminary Technical Data EVAL-AD76MUXEDZRev. PrD | Page 19 of 26EVAL-AD76MUXEDZ Preliminary Technical DataRev. PrD | Page 20 of 26Preliminary Technical Data EVAL-AD76MUXEDZEVAL-AD76MUXEDZ Preliminary Technical DataFigure 20. Top Side Silk-Screen(Viewed from top side)Figure 21. Inner Layer 1(Viewed from top side)Preliminary Technical Data EVAL-AD76MUXEDZFigure 22. Ground Plane(Viewed from top side)Figure 23. Inner Layer 2(Viewed from top side)EVAL-AD76MUXEDZ Preliminary Technical DataFigure 24.Inner Layer 3(Viewed from top side)Figure 25. Bottom Layer(Viewed from top side)Preliminary Technical Data EVAL-AD76MUXEDZFigure 26. Bottom Layer(Viewed from Bottom Side)。