GRM155R71H102KA01D中文资料

±1°C Remote and Local Temperature Sensor with SMBus Serial InterfaceFeaturesTwo Channels: Measures Both Remote andLocal Temperatures No Calibration RequiredSMBus 2-Wire Serial InterfaceProgrammable Under/Overtemperature Alarms Supports SMBus Alert Response Accuracy:±1°C (+60°C to +100°C, remote) ±3°C (+60°C to + 100°C, local)320µA (typ) Average Supply Current During Conversion+3V to +5.5V Supply Range Small 8-Lead SO PackageApplications Desktop and Notebook Central Office Computers Telecom Equipment Smart Battery Packs Test and Measurement LAN Servers Multi-Chip Modules Industrial Controllers General DescriptionThe G781 is a precise digital thermometer that reports the temperature of both a remote sensor and its own package. The remote sensor is a diode-connected transistor typically a low-cost, easily mounted 2N3904 NPN type that replace conventional thermistors or thermocouples. Remote accuracy is ±1°C with no cali-bration needed. The remote channel can also meas-ure the die temperature of other ICs, such as micro-processors, that contain an on-chip, diode-connected transistor.The 2-wire serial interface accepts standard System Management Bus (SMBus) Write Byte, Read Byte, Send Byte, and Receive Byte commands to program the alarm thresholds and to read temperature data.The data format is 11bits plus sign, with each bit cor-responding to 0.125°C, in two’s-complement format. Measurements can be done automatically and autonomously, with the conversion rate programmed by the user or programmed to operate in a single-shot mode. The adjustable rate allows the user to control the supply current drain.The G781 is available in a small, 8-pin SOP sur-face-mount package.Ordering InformationPART* TEMP. RANGE PIN-PACKAGEG781-20°C to +120°C8-SOPPin ConfigurationTypical Operating Circuit3V TO 5.5VEACHCLOCK DATAINTERRUPT TO µCSMBDATA SMBCLK GNDG781ALERTAbsolute Maximum RatingsVCC to GND………….….……..………….-0.3V to +6V DXP to GND……….……………..…-0.3V to VCC + 0.3V DXN to GND……………..……………..-0.3V to +0.8V SMBCLK, SMBDATA,ALERT to GND..…-0.3V to +6V SMBDATA,ALERT Current………….-1mA to +50mA DXN Current……………………..………………….±1mA ESD Protection (SMBCLK, SMBDATA,ALERT , humanbody model).……………………………………….2000V ESD Protection (other pins, human body model)..2000V Continuous Power Dissipation (T A = +70°C) ..SOP (derate 8.30mW/°C above +70°C)…………......667mW Operating Temperature Range………-20°C to +120°C Junction Temperature………………….………..+150°C Storage temperature Range………….-65°C to +165°C Lead Temperature (soldering, 10sec)……..……...+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the opera-tional sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Electrical Characteristics(VCC = + 3.3V, T A = 0°C to +85°C, unless otherwise noted.)PARAMETER CONDITIONS MIN TYP MAX UNITST R = +60°C to +100°C, VCC = 3.0V to 3.6V-1+1Temperature Error, Remote Di-ode (Note 1)T R = 0°C to +125°C (Note 2)-3 +3 °CT A = +60°C to +100°C-3 +3Temperature Error, Local DiodeT A = 0°C to +85°C (Note 2)-5 +5°CSupply-Voltage Range3.0 5.5 V Undervoltage Lockout Threshold VCC input, disables A/D conversion, rising edge 2.8 V Undervoltage Lockout Hysteresis 50 mV Power-On Reset Threshold VCC, falling edge 1.7 V POR Threshold Hysteresis 50 mVSMBus static3Standby Supply Current Logic inputs forced to VCC or GND Hardware or softwarestandby, SMBCLK at 10kHz4 µA0.5 conv/sec 35Average Operating Supply CurrentAuto-convert mode. Logic inputs forced to VCC or GND 8.0 conv/sec 320 µAConversion Time From stop bit to conversion complete (both channels) 125 ms Conversion Rate Timing Conversion-Rate Control Byte=04h, 1Hz 1 sec High level176Remote-Diode Source CurrentDXP forced to 1.5VLow level11µAElectrical Characteristics (continued)(VCC = + 3.3V, T A = 0 to +85°C, unless otherwise noted.)Note 1: A remote diode is any diode-connected transistor from Table1. T R is the junction temperature of the remote of the remote diode. See Remote Diode Selection for remote diode forward voltage requirements.Note 2: Guaranteed by design but not 100% tested.Pin DescriptionDetailed DescriptionThe G781 is a temperature sensor designed to work in conjunction with an external microcontroller (µC) or other intelligence in thermostatic, process-control, or monitoring applications. The µC is typically a power- management or keyboard controller, generating SMBus serial commands by “bit-banging” general- purpose input-output (GPIO) pins or via a dedicated SMBus interface block.Essentially an serial analog-to digital converter (ADC) with a sophisticated front end, the G781 contains a switched current source, a multiplexer, an ADC, an SMBus interface, and associated control logic (Figure 1). Temperature data from the ADC is loaded into two data registers, where it is automatically compared with data previously stored in several over/under- tem-perature alarm registers.ADC and MultiplexerThe ADC is an averaging type that integrates over a 60ms period (each channel, typical), with excellent noise rejection.The multiplexer automatically steers bias currents through the remote and local diodes, measures their forward voltages, and computes their temperatures. Both channels are automatically converted once the conversion process has started, either in free-running or single-shot mode. If one of the two channels is not used, the device still performs both measurements, and the user can simply ignore the results of the un-used channel. If the remote diode channel is unused, tie DXP to DXN rather than leaving the pins open. The worst-case DXP-DXN differential input voltage range is 0.25V to 0.95V.Excess resistance in series with the remote diode causes about +0.6°C error per ohm. Likewise, 240µV of offset voltage forced on DXP-DXN causes about 1°C error.Figure 1. Functional DiagramSMBDATA SMBCLKA/D Conversion SequenceIf a Start command is written (or generated automati-cally in the free-running auto-convert mode), both channels are converted, and the results of both meas-urements are available after the end of conversion. A BUSY status bit in the status byte shows that the de-vice is actually performing a new conversion; however, even if the ADC is busy, the results of the previous conversion are always available.Remote Diode SelectionTemperature accuracy depends on having a good- quality, diode-connected small-signal transistor. The G781 can also directly measure the die temperature of CPUs and other integrated circuits having on-board temperature-sensing diodes.The transistor must be a small-signal type with a rela-tively high forward voltage; otherwise, the A/D input voltage range can be violated. The forward voltage must be greater than 0.25V at 10µA; check to ensure this is true at the highest expected temperature. The forward voltage must be less than 0.95V at 300µA; check to ensure this is true at the lowest expected temperature. Large power transistors don’t work at all. Also, ensure that the base resistance is less than 100Ω. Tight specifications for forward-current gain (+50 to +150, for example) indicate that the manufac-turer has good process controls and that the devices have consistent V be characteristics.Thermal Mass and Self-HeatingThermal mass can seriously degrade the G781’s ef-fective accuracy. The thermal time constant of the SOP- package is about 140 in still air. For the G781 junction temperature to settle to within +1°C after a sudden +100°C change requires about five time con-stants or 12 minutes. The use of smaller packages for remote sensors, such as SOT23s, improves the situa-tion. Take care to account for thermal gradients be-tween the heat source and the sensor, and ensure that stray air currents across the sensor package do not interfere with measurement accuracy. Self-heating does not significantly affect measurement accuracy. Remote-sensor self-heating due to the diode current source is negligible. For the local diode, the worst-case error occurs when auto-converting at the fastest rate and simultaneously sinking maximum current at the ALERT output. For example, at an 8Hz rate and with ALERT sinking 1mA, the typical power dissipation isVCC x 320µA plus 0.4V x 1mA. Package theta J-A is about 120°C /W, so with VCC = 3.3V and no copper PC board heat-sinking, the resulting temperature rise is:dT =1.45mW x 120°C /W =0.17°CEven with these contrived circumstances, it is difficultto introduce significant self-heating errors.Table 1. Remote-Sensor Transistor Manufacturers MANUFACTURER MODELNUMBER Philips PMBS3904Motorola(USA) MMBT3904 National Semiconductor (USA) MMBT3904Note:Transistors must be diode-connected (baseshorted to collector).ADC Noise FilteringThe ADC is an integrating type with inherently good noise rejection. Micropower operation places con-straints on high-frequency noise rejection; therefore, careful PC board layout and proper external noise fil-tering are required for high-accuracy remote meas-urements in electrically noisy environments.High-frequency EMI is best filtered at DXP and DXNwith an external 2200pF capacitor. This value can be increased to about 3300pF(max), including cable ca-pacitance. Higher capacitance than 3300pF introduces errors due to the rise time of the switched current source.Nearly all noise sources tested cause the ADC meas-urements to be higher than the actual temperature, typically by +1°C to 10°C, depending on the frequencyand amplitude.PC Board LayoutPlace the G781 as close as practical to the remote diode. In a noisy environment, such as a computer motherboard, this distance can be 4 in. to 8 in. (typical)or more as long as the worst noise sources (such as CRTs, clock generators, memory buses, and ISA/PCI buses) are avoided.Do not route the DXP-DXN lines next to the deflection coils of a CRT. Also, do not route the traces across a fast memory bus, which can easily introduce +30°C error, even with good filtering, Otherwise, most noise sources are fairly benign.Route the DXP and DXN traces in parallel and in close proximity to each other, away from any high-voltage traces such as +12V DC. Leakage currents from PC board contamination must be dealt with carefully, since a 10MΩ leakage path from DXP to ground causes about +1°C error.Connect guard traces to GND on either side of the DXP-DXN traces (Figure 2). With guard traces in place, routing near high-voltage traces is no longer an issue.Route through as few vias and crossunders as possible to minimize copper/solder thermocouple ef-fects.When introducing a thermocouple, make sure that both the DXP and the DXN paths have matching thermocouples. In general, PC board-induced ther-mocouples are not a serious problem, A copper-solder thermocouple exhibits 3µV/°C, and it takes about 240µV of voltage error at DXP-DXN to cause a +1°C measurement error. So, most parasitic thermocouple errors are swamped out.Use wide traces. Narrow ones are more inductive and tend to pick up radiated noise. The 10 mil widths and spacing recommended on Figure 2 aren’t absolutely necessary (as they offer only a minor improvement in leakage and noise), but try to use them where practi-cal.Keep in mind that copper can’t be used as an EMI shield, and only ferrous materials such as steel work will. Placing a copper ground plane between the DXP-DXN traces and traces carrying high-frequency noise signals does not help reduce EMI.PC Board Layout ChecklistPlace the G781 close to a remote diode.Keep traces away from high voltages (+12V bus).Keep traces away from fast data buses and CRTs. Use recommended trace widths and spacing.Place a ground plane under the tracesUse guard traces flanking DXP and DXN and con necting to GND.Place the noise filter and the 0.1µF VCC bypass capacitors close to the G781.Figure 2. Recommended DXP/DXN PC Traces Twisted Pair and Shielded CablesFor remote-sensor distances longer than 8 in., or in particularly noisy environments, a twisted pair is rec-ommended. Its practical length is 6 feet to 12feet (typi cal) before noise becomes a problem, as tested in a noisy electronics laboratory. For longer distances, the best solution is a shielded twisted pair like that used for audio microphones. Connect the twisted pair to DXP and DXN and the shield to GND, and leave the shield’s remote end unterminated.Excess capacitance at DX_limits practical remote sen-sor distances (see Typical Operating Characteristics), For very long cable runs, the cable’s parasitic capaci-tance often provides noise filtering, so the 2200pF ca-pacitor can often be removed or reduced in value. Ca-ble resistance also affects remote-sensor accuracy; 1Ωseries resistance introduces about + 0.6°C error.Low-Power Standby ModeStandby mode disables the ADC and reduces the supply-current drain to about 10µA. Enter standby mode by forcing high to the RUN/STOP bit in the con-figuration byte register. Software standby mode be-haves such that all data is retained in memory, and the SMB interface is alive and listening for reads and writes.Software standby mode is not a shutdown mode. With activity on the SMBus, extra supply current is drawn (see Typical Operating Characteristics). In software standby mode, the G781 can be forced to perform A/D conversions via the one-shot command, despite the RUN/STOP bit being high.10 MILSMINIMUM10 MILS10 MILSIf software standby command is received while a con-version is in progress, the conversion cycle is trun-cated, and the data from that conversion is not latched into either temperature reading register. The previous data is not changed and remains available.Supply-current drain during the 125ms conversion period is always about 320µA. Slowing down the con-version rate reduces the average supply current (see Typical Operating Characteristics). In between con-versions, the instantaneous supply current is about 25µA due to the current consumed by the conversion rate timer. In standby mode, supply current drops to about 3µA. At very low supply voltages (under the power-on-reset threshold), the supply current is higher due to the address pin bias currents. It can be as high as 100µA, depending on ADD0 and ADD1 settings. SMBus Digital InterfaceFrom a software perspective, the G781 appears as a set of byte-wide registers that contain temperature data, alarm threshold values, or control bits, A stan-dard SMBus 2-wire serial interface is used to read temperature data and write control bits and alarm threshold data.Each A/D channel within the device responds to the same SMBus slave address for normal reads and writes.The G781 employs four standard SMBus protocols: Write Byte, Read Byte, Send Byte, and Receive Byte (Figure 3). The shorter Receive Byte protocol allows quicker transfers, provided that the correct data regis-ter was previously selected by a Read Byte instruction. Use caution with the shorter protocols in multi-master systems, since a second master could overwrite the command byte without informing the first master.The temperature data format is 11bits plus sign in twos-complement form for remote channel, with each data bit representing 0.125°C (Table 2,Table 3), transmitted MSB first. Table 2. Temperature Data Format(Two’s-Complement)DIGITAL OUTPUTDATA BITSTEMP.(°C)SIGN MSB LSB EXT+127.875 0 111 1111 111+126.375 0 111 1110 011+25.5 0 001 1001 100+1.75 0 000 0001 110+0.5 0 000 0000 100+0.125 0 000 0000 001-0.125 1 111 1111 111-1.125 1 111 1110 111-25.5 1 110 0110 100-55.25 1 100 1000 110-65.000 1 011 1111 000Table 3. Extended Temperature Data FormatEXTENDEDRESOLUTIONDATA BITS0.000°C 000000000.125°C 001000000.250°C 010000000.375°C 011000000.500°C 100000000.625°C 101000000.750°C 110000000.875°C 11100000Slave AddressThe G781 appears to the SMBus as one device hav-ing a common address for both ADC channels. The G781 device address is set to 1001100.The G781 also responds to the SMBus Alert Re-sponse slave address (see the Alert Response Ad-dress section).One-Shot RegisterThe One-shot register is to initiate a single conversion and comparison cycle when the device is in standby mode and auto conversion mode. The write operation to this register causes one-shot conversion and the data written to it is irrelevant and is not stored.Serial Bus Interface ReinitializationWhen SMBCLK are held low for more than 30ms (typical) during an SMBus communication the G781 will reinitiateits bus interface and be ready for a new transmission. Alarm Threshold RegistersFour registers store alarm threshold data, with high-temperature (T HIGH) and low-temperature (T LOW) registers for each A/D channel. If either measured temperature equals or exceeds the corresponding alarm threshold value, an ALERT interrupt is as-serted.The power-on-reset (POR) state of both T HIGH registers is full scale (01010101, or +85°C). The POR state of both T LOW registers is 0°C.Diode Fault AlarmThere is a fault detector at DXP that detects whether the remote diode has an open-circuit condition. At the beginning of each conversion, the diode fault is checked, and the status byte is updated. This fault de-tector is a simple voltage detector. If DXP rises above VCC – 1V (typical) due to the diode current source, a fault is detected and the device alarms through pulling ALERT low while the remote temperature reading doesn’t update in this condition. Note that the diode fault isn’t checked until a conversion is initiated, so im-mediately after power-on reset the status byte indicates no fault is present, even if the diode path is broken.If the remote channel is shorted (DXP to DXN or DXP to GND), the ADC reads 1000 0000(-128°C) so as not to trip either the T HIGH or T LOW alarms at their POR settings. ALERT InterruptsThe ALERT interrupt output signal is latched and canonly be cleared by reading the Alert Response ad-dress. Interrupts are generated in response to T HIGHand T LOW comparisons and when the remote diode is disconnected (for fault detection). The interrupt doesnot halt automatic conversions; new temperature datacontinues to be available over the SMBus interfaceafter ALERT is asserted. The interrupt output pin isopen-drain so that devices can share a common in-terrupt line. The interrupt rate can never exceed theconversion rate.The interface responds to the SMBus Alert Responseaddress, an interrupt pointer return-address feature(see Alert Response Address section). Prior to takingcorrective action, always check to ensure that an in-terrupt is valid by reading the current temperature.Alert Response AddressThe SMBus Alert Response interrupt pointer providesquick fault identification for simple slave devices thatlack the complex, expensive logic needed to be a busmaster. Upon receiving an ALERT interrupt signal,the host master can broadcast a Receive Byte trans-mission to the Alert Response slave address (0001100). Then any slave device that generated an inter-rupt attempts to identify itself by putting its own ad-dress on the bus (Table 4).The Alert Response can activate several differentslave devices simultaneously, similar to the SMBusGeneral Call. If more than one slave attempts to re-spond, bus arbitration rules apply, and the device withthe lower address code wins. The losing device doesnot generate an acknowledge and continues to holdthe ALERT line low until serviced (implies that thehost interrupt input is level-sensitive). Successfulreading of the alert response address clears the inter-rupt latch.Table 4. Read Format for Alert Response Address(0001 100)BIT NAME7(MSB) ADD76 ADD65 ADD54 ADD43 ADD32 ADD21 ADD10(LSB) 1Command Byte FunctionsThe 8-bit command byte register (Table 5) is the mas-ter index that points to the various other registers within the G781. The register’s POR state is 0000 0000, so that a Receive Byte transmission (a protocol that lacks the command byte) that occurs immediately after POR returns the current local temperature data.The one-shot command immediately forces a new conversion cycle to begin. In software standby mode (RUN/STOP bit = high), a new conversion is begun, after which the device returns to standby mode. If a conversion is in progress when a one-shot command is received in auto-convert mode (RUN/STOP bit = low) between conversions, a new conversion begins, the conversion rate timer is reset, and the next auto-matic conversion takes place after a full delay elapses.Configuration Byte FunctionsThe configuration byte register (Table 6) is used to mask interrupts and to put the device in software standby mode. The other bits are empty. Status Byte FunctionsThe status byte register (Table 7) indicates which (if any) temperature thresholds have been exceeded. This byte also indicates whether or not the ADC is converting and whether there is an open circuit in the remote diode DXP-DXN path. After POR, the normal state of all the flag bits is zero, assuming none of the alarm conditions are present. The status byte is cleared by any successful read of the status, unless the fault persists. Note that the ALERT interrupt latch is not automatically cleared when the status flag bit is cleared.When reading the status byte, you must check for in-ternal bus collisions caused by asynchronous ADC timing, or else disable the ADC prior to reading the status byte (via the RUN/STOP bit in the configura-tion byte). In one-shot mode, read the status byte only after the conversion is complete, which is approxi-mately 125ms max after the one-shot conversion is commanded.Table 5. Command-Byte Bit Assignments*If the device is in standby mode at POR, both temperature registers read 0°C.Table 6. Configuration-Byte Bit AssignmentsTable 7. Status-Byte Bit Assignments*These flags stay high until cleared by POR, or until the status byte register is read.Table 8. Conversion-Rate Control ByteDATA CONVERSION RATE (Hz)00h 0.062501h 0.12502h 0.2503h 0.504h 105h 206h 407h 808h 16 09h to FFh RFUTo check for internal bus collisions, read the status byte. If the least significant seven bits are ones, dis-card the data and read the status byte again. The status bits LHIGH, LLOW, RHIGH, and RLOW are refreshed on the SMBus clock edge immediately fol-lowing the stop condition, so there is no danger of los-ing temperature-related status data as a result of an internal bus collision. The OPEN status bit (diode con-tinuity fault) is only refreshed at the beginning of a conversion, so OPEN data is lost. The ALERT inter-rupt latch is independent of the status byte register, so no false alerts are generated by an internal bus colli-sion. When auto-converting, if the THIGH and TLOW limits are close together, it’s possible for both high-temp and low-temp status bits to be set, depending on the amount of time between status read operations (espe-cially when converting at the fastest rate). In these circumstances, it’s best not to rely on the status bits to indicate reversals in long-term temperature changes and instead use a current temperature reading to es-tablish the trend direction.For bit 1 and bit 0, a high indicates a temperature alarm happened for remote and local diode respec-tively. THERM pin also asserts. These two bits wouldn’t be cleared when reading status byte.Conversion Rate ByteThe conversion rate register (Table 8) programs the time interval between conversions in free-running auto-convert mode. This variable rate control reduces the supply current in portable-equipment applications. The conversion rate byte’s POR state is 08h (16Hz). The G781 looks only at the 4 LSB bits of this register, so the upper 4 bits are “don’t care” bits, which should be set to zero. The conversion rate tolerance is ±25% at any rate setting.Valid A/D conversion results for both channels are available one total conversion time (125ms,typical) after initiating a conversion, whether conversion is initiated via the RUN/STOP bit, one-shot command, or initial power-up.POR AND UVLOThe G781 has a volatile memory. To prevent ambiguous power-supply conditions from corrupting the data in memory and causing erratic behavior, a POR voltage detector monitors VCC and clears the memory if VCC falls below 1.7V (typical, see Electrical Characteristics table). When power is first applied and VCC rises above 1.7V (typical), the logic blocks begin operating, although reads and writes at V CC levels below 3V are not recom-mended. A second VCC comparator, the ADC UVLO comparator, prevents the ADC from converting until there is sufficient headroom (VCC= 2.8V typical).ALERT Fault QueueTo suppress unwanted ALERT triggering the G781 em-bedded a fault queue function. The ALERT won’t as-sert until consecutive out of limit measurements have reached the queue number. The mapping of fault queue register (ALERTFQ, 22h) value to fault queue number is shown in the Table 9.Table 9. Alert Fault QueueALERTFQVALUEFAULT QUEUE NUMBER XXXX000X 1XXXX001X 2XXXX010X 3XXXX011X 3XXXX100X 4XXXX101X 4XXXX110X 4XXXX111X 4 Operation of The THERM FunctionA local and remote THERM limit can be programmed into the G781 to set the temperature limit above which the THERM pin asserts low and the bit 1, of status byte will be set to 1 corresponding to remote and local over temperature. These two bits won’t be cleared to 0 by reading status byte it the over temperature condi-tion remain. A hysteresis value is provided by writing the register 21h to set the temperature threshold to release the THERM pin alarm state, The releasing temperature is the value of register 19h, 20h minus the value in register 21h. The format of register 21h is 2’s complement. The THERM signal is open drain and requires a pull-up resistor to power supply.Figure 4. SMBus Write Timing DiagramA = start condition H = LSB of data clocked into slaveB = MSB of address clocked into slave I = slave pulls SMBDATA line lowC = LSB of address clocked into slave J = acknowledge clocked into masterD = R/W bit clocked into slave K = acknowledge clocked pulseE = slave pulls SMBDATA line low L = stop condition data executed by slaveF = acknowledge bit clocked into master M = new start conditionG = MSB of data clocked into slaveFigure 5. SMBus Read Timing DiagramA = start condition G = MSB of data clocked into masterB = MSB of address clocked into slave H = LSB of data clocked into masterC = LSB of address clocked into slave I = acknowledge clocked pulseD = R/W bit clocked into slave J = stop conditionE = slave pulls SMBDATA line low K= new start conditionF =acknowledge bit clocked into master。

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DM8 24 -40 ... +70 DEGREESA&DSE/SIPAD4701,507.97 6AG10551CB002XB0SIPLUS LOGO! DM8 24 MODULAR -25 ... +7A&DSE/SIPAD4701,507.97 6AG10551FB002BY1SIPLUS LOGO! DM8 230R -40 ... +70 DEGREA&DSE/SIPAD4701,547.65 6AG10551FB002XB1SIPLUS LOGO! DM8 230R - MODULAR -25 .A&DSE/SIPAD4701,547.65 6AG10551HB002BY0SIPLUS LOGO! DM8 24R -40 ... +70 DEGREEA&DSE/SIPAD4701,547.65 6AG10551HB002XB0SIPLUS LOGO! DM8 24R -25 ... +70 DGR C BA&DSE/SIPAD4701,547.65 6AG10551MA002BY0SIPLUS LOGO! AM2 - 40 ... +70 DEGREES CA&DSE/SIPAD4701,984.17 6AG10551MA002XB0SIPLUS LOGO! AM2 MODULAR -25 ... +70 D A&DSE/SIPAD4701,984.17 6AG10551MB002BY1SIPLUS LOGO! DM8 12/24R -40 ... +70 DEGRA&DSE/SIPAD4701,547.65 6AG10551MB002XB1SIPLUS LOGO! DM8 12/24R -25 ... +70 DGR A&DSE/SIPAD4701,547.65 6AG10551MM002BY1SIPLUS LOGO! AM2 AQ -40 ... +70 DEGREE A&DSE/SIPAD4701,974.25 6AG10551NB102BA0SIPLUS LOGO! DM16 24R -25 ... +70 DGR C A&DSE/SIPAD4702,182.59 6AG10551PB002BY0SIPLUS LOGO! DM8 12/24 -40 ... +70 DEGREA&DSE/SIPAD4701,567.49 6AG10551PB002XB0SIPLUS LOGO! DM8 12/24 -25 ... +70 DGR CA&DSE/SIPAD4701,726.23 6AG10554MH002BA0SIPLUS LOGO TD -10 ... +60 DEGREES C WA&DSE/SIPAD4701,716.31 6AG10571AA000AA0FRONT PANEL MOUNTING KIT 4 PU FOR L A&DSE/SIPAD470426.60 6AG10571AA000AA1FRONT PANEL MOUNTING KIT 8 PU FOR L A&DSE/SIPAD470724.22 6AG10571AA000AA2FRONT PANEL MOUNTING KIT 8 PU WITH KA&DSE/SIPAD470793.67 6AG10571AA000AA3FRONT PANEL MOUNTING KIT 4PU WITH KA&DSE/SIPAD470466.28 6AG10571AA010BA6LOGO! PROM V6 100...230VAC 50/6 PROGRA&DSE/SIPAD4703,432.61 6AG10571AA030AA0SIPLUS DCF77 TIME RECEIVER A&DSE/SIPAD4721,830.63 6AG1062-1AA12-1AA0S7-1200 CONTROLLER DEMOBOX A&DSE/SIDEM4ZZ51,937.97 6AG1064-1AA04-0AA0TEST BOX F. FUNCTION TESTING OF POW A&DSE/SIDEM4ZZ11,793.05 6AG1064-1AA05-0AA0MEAS. CABLE SET FOR TEST BOX 6AG106A&DSE/SIDEM4ZZ2,533.83 6AG11011BB004AA3SIPLUS NET X101-1 FOR MEDIAL STRESS BA&DSE/SIPAD4718,282.49 6AG11042BB002AA3SIPLUS NET SCALANCE X104-2 -25 ... +60 DA&DSE/SIPAD47115,442.50 6AG11052AA104AA0SIPLUS NET OSM ITP62 FOR MEDIAL STREA&DSE/SIPAD47152,875.25 6AG11052AB104AA0SIPLUS NET OSM TP62 FOR MEDIAL STRE A&DSE/SIPAD47151,939.86 6AG11053AA104AA0SIPLUS NET ESM ITP80 FOR MEDIAL STRE A&DSE/SIPAD47143,878.47 6AG11311BH012XB0SIPLUS ET200L 16DI -25 ... +60 DGR C BAS A&DSE/SIPAD4715,510.32 6AG11314BD012AA0SIPLUS ET200S 4DI (1PU=5PCS) -25...+60 DA&DSE/SIPAD4713,826.61 6AG11314BD017AB0SIPLUS ET200S EM 4DI HF -25...+70 DEGREA&DSE/SIPAD4714,676.97 6AG11314BF007AA0SIPLUS ET200S EM 8 DI -25 ... +70 DEGREEA&DSE/SIPAD4711,122.47 6AG11314BF507AA0SIPLUS ET200S EM 8 DI DC24V -40 ... +70 DA&DSE/SIPAD4711,113.97 6AG11324BB012AB0SIPLUS ET200S 2DO HF (1PU=5PCS) -25...+A&DSE/SIPAD4712,437.69 6AG11324BB317AB0SIPLUS ET200S 2DO HF -25 ... +70 DEGREEA&DSE/SIPAD4714,265.96 6AG11324BD027AA0SIPLUS ET200S EM 4DO STANDARD -25 ... A&DSE/SIPAD4713,642.37 6AG11324BD322AA0SIPLUS ET200S EM 4DO DC24V/2A -25 ... +A&DSE/SIPAD4715,725.74 6AG11324BF007AA0SIPLUS ET200S EM 8 DO -25 ... + 70 DEGREA&DSE/SIPAD4711,048.776AG11324BF507AA0SIPLUS ET200S EM 8 DO DC24V/0.5 -25 ... +A&DSE/SIPAD4711,041.69 6AG11324HB012AB0SIPLUS ET200S EM 2RO DC24V-AC23 -25 ..A&DSE/SIPAD4713,982.51A&DSE/SIPAD4714,634.45 6AG11324HB102AB0SIPLUS ET200S EM 2DO RLY 24-48VDC 2306AG11344FB012AB0SIPLUS ET200S EM 2AI STANDARD U -25 ..A&DSE/SIPAD4713,044.28 6AG11344GB012AB0SIPLUS ET200S EM 2AI STANDRAD I -25 ... A&DSE/SIPAD4712,925.23 6AG11344GB112AB0SIPLUS ET200S EM 2AI I-4DMU -25 ... +60 D A&DSE/SIPAD4712,925.23 6AG11344GB522AB0SIPLUS ET200S EM 2AI HIGH SPEED -25 ...A&DSE/SIPAD4715,986.52 6AG11344GD002AB0SIPLUS ET200S EM 4 AI I 2WIRE -25 ... +60 A&DSE/SIPAD4713,282.38 6AG11344JB517AB0SIPLUS ET200S EM 2AI RTD -25 ... +70 DEGA&DSE/SIPAD4715,204.19A&DSE/SIPAD4713,843.62 6AG11344NB012AB0SIPLUS ET200S EM 2AI TC HF -25 ... +60 DEA&DSE/SIPAD4714,251.79 6AG11344NB512AB0SIPLUS ET200S EM 2AI RTD HF -25 ... +60 D6AG11354FB012AB0SIPLUS ET200S EM 2AO U -25 ... +60 DEGR A&DSE/SIPAD4713,044.28 6AG11354GB012AB0SIPLUS ET200S EM 2AO I STANDARD -25 ..A&DSE/SIPAD4712,959.25 6AG11354LB027AB0SIPLUS ET200S 2AO U HIGH FEATUR -25 ..A&DSE/SIPAD4713,622.52 6AG11384CA012AA0SIPLUS ET200S PM-E DC 24V WITH DIAGN A&DSE/SIPAD471476.20 6AG11384CA502AB0SIPLUS ET200S PM-E 24V-48V -25...+60 DE A&DSE/SIPAD471918.39 6AG11384CB112AB0SIPLUS ET200S PM-E DC/AC -25...+60 DEG A&DSE/SIPAD471799.34 6AG11384DA042AB0SIPLUS ET200S EM 1COUNT 24V/100 -25 ...A&DSE/SIPAD4714,149.75A&DSE/SIPAD4715,187.18 6AG11384DD007AB0SIPLUS ET200S EM 2 PULSE -25 ... +70 DEG6AG11384DF017AB0SIPLUS ET200S EM 1SI -25 ... +70 DEGREE A&DSE/SIPAD4716,173.60A&DSE/SIPAD4716,360.68 6AG11384FA042AB0SIPLUS ET200S F-DI 24V PROFISAF -25 ... +6AG11384FB032AB0SIPLUS ET200S F-DO 24V PROFISAF -25 ...A&DSE/SIPAD4717,313.08 6AG11384HA007AB0SIPLUS ET200S DP-MASTERANSCHALT FO A&DSE/SIPAD47110,119.26 6AG11511AA057AB0SIPLUS ET200S IM151-1 STANDARD -25 ... A&DSE/SIPAD4717,517.16A&DSE/SIPAD4719,251.89 6AG11511BA022AB0SIPLUS ET200S IM151 HF -25 ... +60 DEGRE6AG11513AA222AB0SIPLUS ET200S IM151-3 PROFINET -25 ... +A&DSE/SIPAD4719,115.84 6AG11513AA232AB0SIPLUS ET200S IM151-3 ST -25 ... +60 DEG A&DSE/SIPAD4719,115.84 6AG11517AA207AB0SIPLUS ET200S IM151-7 CPU -25 ... + 70 DE A&DSE/SIPAD47113,180.55A&DSE/SIPAD47318,554.81 6AG11517FA202AB0SIPLUS ET200S IM151-7 F-CPU -25 ... +60 DA&DSE/SIPAD47115,221.41 6AG11518AB004AB0SIPLUS ET200S IM151-8 PN/DP CPU FOR M6AG11518AB007AB0SIPLUS ET200S IM151-8 PN/DP CPU -25 ... A&DSE/SIPAD47116,922.12A&DSE/SIPAD47121,667.12 6AG11518FB002AB0SIPLUS ET200S IM151-8F PN/DP CP -25 ... +6AG11531AA032XB0SIPLUS DP ET200M IM153-1 -25...+70 DGR A&DSE/SIPAD4736,071.56A&DSE/SIPAD47321,429.02 6AG11532AR032XA0SIPLUS ET200M RED-BUNDLE -25 ... +70 DE6AG11532BA022XY0SIPLUS ET200M IM153-2 -25 ... +60 GRAD CA&DSE/SIPAD47110,459.40A&DSE/SIPAD4718,571.61 6AG11532BA024XB0SIPLUS ET200M IM153-2 FOR MEDIAL STRE6AG11532BA027XB0SIPLUS ET200M IM153-2 (*BA02) -25 ... +70 A&DSE/SIPAD4739,387.95A&DSE/SIPAD4738,197.45 6AG11534AA007XB0SIPLUS ET200M IM 153-4 PN IO -25 ... +70 DA&DSE/SIPAD4717,040.96 6AG11534AA017XB0SIPLUS ET200M IM 153-4 PN IO -25 ... +70 DA&DSE/SIPAD4711,309.55 6AG11931CH002XA0SIPLUS ET200L TB 16L -25 ... +60 DGR C BAA&DSE/SIPAD473943.90 6AG11934CA302AA0SIPLUS ET200S TM-E15C24-A1 -40...+70 DG6AG11934CA402AA0SIPLUS ET200S TM-E15S26-A1 -40 ... +70 D A&DSE/SIPAD4711,513.64 6AG11934CA502AA0SIPLUS ET200S TM-E15C26-A1 -40 ... +70 D A&DSE/SIPAD4731,513.64A&DSE/SIPAD4711,054.44 6AG11934CB107AA0SIPLUS ET200S TM-E15C23-0 -40...+70 DEG6AG11934CB302AA0SIPLUS ET200S TM-E15C24-01 -40 ... +70 D A&DSE/SIPAD471952.40A&DSE/SIPAD4711,173.49 6AG11934CB707AA0SIPLUS ET200S TM-E15N24-0 -40...+70 DEG6AG11934CD202AA0SIPLUS ET200S TM-P15S23-A0 -40 ... +70 D A&DSE/SIPAD471195.58 6AG11934CD302AA0SIPLUS ET200S TM-P15C23-A0 -40 ... +70 D A&DSE/SIPAD473195.58 6AG11934CE102AA0SIPLUS ET200S TM-P15C22-01 -40 ... +70 D A&DSE/SIPAD471195.58A&DSE/SIPAD471595.25 6AG11934CF507AA0SIPLUS ET200S TM-E30C46-A1 -40...+70 DE6AG11934CG302AA0SIPLUS ET200S TM-E30C44-01 -40...+70 DE A&DSE/SIPAD471714.30 6AG11934CL302AA0SIPLUS ET200S TM-E15C24-AT -40 ... +70 D A&DSE/SIPAD471544.23 6AG11934JA002AA0SIPLUS ET200S TERMINATING MODULE -2A&DSE/SIPAD471510.21A&DSE/SIPAD4711,326.56 6AG11957HA002XA0SIPLUS ET200M ACTIVE BUS MODULE 1X P6AG11957HB004XA0SIPLUS ET200M BUS MODULE FOR MEDIA A&DSE/SIPAD4712,806.186AG11957HB007XA0SIPLUS ET200M ACTIVE BUSMODULE 2X 4A&DSE/SIPAD4712,959.25A&DSE/SIPAD4712,806.18 6AG11957HC002XA0SIPLUS ET200M ACTIVE BUS MODULE FORA&DSE/SIPAD4713,537.49 6AG11957HD102XA0SIPLUS ET200M ACTIVE BUS MODULE FOR6AG11957HG002XA0SIPLUS ET200M SEPARATOR BUS MOD F; A&DSE/SIPAD4712,483.05A&DSE/SIPAD4733,554.50 6AG11957KF002XA0SIPLUS S7-300 ISOLATION MODULE - 25...+A&DSE/SIPAD47432,551.70 6AG11971LA114XA0SIPLUS S7-400 Y-LINK FOR S7-400 FOR ME6AG11971LB004XA0SIPLUS S7-400 Y-KOPPLER FOR MEDIAL S A&DSE/SIPAD4747,721.25 6AG12022BH002BA3SIPLUS NET SCALANCE X202-2PIRT -25 ... A&DSE/SIPAD47122,908.64 6AG12031AA002AA0SIPLUS UPMITER 2.5A -25 ... + 70 DEGREE A&DSE/SIPAD4727,670.94A&DSE/SIPAD4723,862.04 6AG12031SH312AA0SIPLUS PS203 -25...+70 DEGREES C BASED6AG12042BB107AA3SIPLUS NET SCALANCE X204-2 -25 ... +70 DA&DSE/SIPAD47122,959.66 6AG12042BC102AA3SIPLUS NET SCALANCE X204-2LD -25 ... +6A&DSE/SIPAD47144,048.54A&DSE/SIPAD4723,625.83 6AG12110AA232XB0SIPLUS CPU211 -25...+70 DGR C BASED ONA&DSE/SIPAD4723,802.99 6AG12110BA232XB0SIPLUS CPU221 -25...+70 DGR C BASED ONA&DSE/SIPAD4724,932.08 6AG1211-1AD30-2XB0SIPLUS S7-1200 CPU 1211C DC/DC/ -25 ... +A&DSE/SIPAD4724,932.08 6AG1211-1BD30-2XB0SIPLUS S7-1200 CPU 1211C AC/DC/ -25 ... +A&DSE/SIPAD4724,932.08 6AG1211-1HD30-2XB0SIPLUS S7-1200 CPU 1211C DC/DC/ -25 ... +A&DSE/SIPAD4724,606.11 6AG12121AB232XB0SIPLUS CPU212 -25...+70 DGR C BASED ONA&DSE/SIPAD4725,306.23 6AG1212-1AD30-2XB0SIPLUS S7-1200 CPU 1212C DC/DC/ -25 ... +A&DSE/SIPAD4724,854.13 6AG12121BB232XB0SIPLUS CPU222 -25...+70 DGR C BASED ONA&DSE/SIPAD4725,306.23 6AG1212-1BD30-2XB0SIPLUS S7-1200 CPU 1212C AC/DC/ -25 ... +6AG1212-1HD30-2XB0SIPLUS S7-1200 CPU 1212C DC/DC/ -25 ... +A&DSE/SIPAD4725,306.23A&DSE/SIPAD4726,117.85 6AG12141AD232XB0SIPLUS CPU224 -25...+70 DGR C BASED ONA&DSE/SIPAD4728,027.38 6AG1214-1AE30-2XB0SIPLUS S7-1200 CPU 1214C DC/DC/ -25 ... +A&DSE/SIPAD4726,318.63 6AG12141BD232XB0SIPLUS CPU224 -25...+70 DGR C BASED ONA&DSE/SIPAD4728,027.38 6AG1214-1BE30-2XB0SIPLUS S7-1200 CPU 1214C AC/DC/ -25 ... +A&DSE/SIPAD4728,027.38 6AG1214-1HE30-2XB0SIPLUS S7-1200 CPU 1214C DC/DC/ -25 ... +6AG12142AD232XB0SIPLUS CPU224XP -25...+70 DGR C BASED A&DSE/SIPAD4729,802.74 6AG12142BD232XB0SIPLUS CPU224XP -25...+70 DGR C BASED A&DSE/SIPAD47210,109.81A&DSE/SIPAD47210,546.80 6AG12162AD232XB0SIPLUS CPU226 -25...+70 DGR C BASED ONA&DSE/SIPAD47210,936.55 6AG12162BD232XB0SIPLUS CPU226 -25...+70 DGR C BASED ON6AG12211BF222XB0SIPLUS S7-200 EM221 -25 ... +70 DGR C BA A&DSE/SIPAD4722,846.34 6AG1221-1BF30-2XB0SIPLUS S7-1200 SM1221 8DE -25 ... +70 DE A&DSE/SIPAD4722,312.97 6AG12211BH222XA0SIPLUS S7-200 EM221 -25...+70 DGR C BAS A&DSE/SIPAD4722,586.51A&DSE/SIPAD4723,673.55 6AG1221-1BH30-2XB0SIPLUS S7-1200 SM1221 16 DI -25 ... +70 DE6AG12221BF222XB0SIPLUS S7-200 EM222 -25 ... +70 DGR C BA A&DSE/SIPAD4722,976.25 6AG1222-1BF30-2XB0SIPLUS S7-1200 SM1222 8DO -25 ... +70 DE A&DSE/SIPAD4722,312.97A&DSE/SIPAD4723,673.55 6AG1222-1BH30-2XB0SIPLUS S7-1200 SM1222 16DA -25 ... +70 DE6AG12221HF222XB0SIPLUS EM222 -25 ... +70 DGR C BASED ONA&DSE/SIPAD4723,129.79A&DSE/SIPAD4722,312.97 6AG1222-1HF30-2XB0SIPLUS S7-1200 SM1222 8DA RY 2A -25 ... +A&DSE/SIPAD4723,673.54 6AG1222-1HH30-2XB0SIPLUS S7-1200 SM1222 16DO RY 2 -25 ... +6AG12231BF222XB0SIPLUS S7-200 EM223 -25 ... +70 DGR C BA A&DSE/SIPAD4722,858.15 6AG12231BH222XB0SIPLUS S7-200 EM223 -25 ... +70 DGR C BA A&DSE/SIPAD4723,755.75 6AG12231BL222XB0SIPLUS S7-200 EM223 -25 ... +70 DGR C BA A&DSE/SIPAD4725,113.96 6AG12231HF222XB0SIPLUS S7-200 EM223 -25 ... +70 DGR C BA A&DSE/SIPAD4723,058.93 6AG12231PH222XB0SIPLUS S7-200 EM223 -25 ... +70 DGR C BA A&DSE/SIPAD4723,732.13 6AG12231PL222XB0SIPLUS S7-200 EM223 -25 ... +70 DGR C BA A&DSE/SIPAD4725,373.79 6AG12310HC222XB0SIPLUS S7-200 EM231 -25 ... +70 DGR C BA A&DSE/SIPAD4724,428.95 6AG1231-4HD30-2XB0SIPLUS S7-1200 SM231 AI 4 12BIT -25 ... +7A&DSE/SIPAD4724,762.00 6AG12317PB222XA0SIPLUS S7-200 EM231 -25 ... +70 DGR C BA A&DSE/SIPAD4723,897.47 6AG12317PB222XY0SIPLUS S7-200 EM231 EN50155 CONFORM A&DSE/SIPAD4724,275.41 6AG12320HB222XB0SIPLUS S7-200 EM232 -25 ... +70 DGR C BA A&DSE/SIPAD4724,617.92 6AG1232-4HB30-2XB0SIPLUS S7-1200 SM1232 2AO -25 ... +70 DE A&DSE/SIPAD4725,034.12 6AG1234-4HE30-2XB0SIPLUS S7-1200 SM1234 4AI/2AO -25 ... +70A&DSE/SIPAD4726,938.92 6AG12350KD222XB0SIPLUS S7-200 EM235 -25 ... +70 DGR C BA A&DSE/SIPAD4725,078.53A&DSE/SIPAD4723,401.43 6AG1241-1AH30-2XB0SIPLUS S7-1200 CM1241 RS232 -25 ... +70 DA&DSE/SIPAD4723,401.43 6AG1241-1CH30-2XB0SIPLUS S7-1200 CM1241 RS485 -25 ... +70 D6AG12720AA302YA1SIPLUS S7-200 TD200 FOR MEDIALE STRE A&DSE/SIPAD4724,574.93 6AG12721AA102YA1SIPLUS S7-200 TD200C -25 ... +60 DEGREE A&DSE/SIPAD4723,850.23 6AG12770AA222XA0SIPLUS S7-200 EM277 BASED ON 6ES7277A&DSE/SIPAD4724,842.32 6AG13051AA002AA0SIPLUS UPMITER 4A -25 ... + 70 DEGREES A&DSE/SIPAD4739,123.63 6AG13051BA802AA0SIPLUS S7-300 PS305 -25...+60 DGR C WIT A&DSE/SIPAD4735,261.59 6AG13071EA802AA0SIPLUS S7-300 PS 307 -25 ... +70 DGR C W A&DSE/SIPAD4733,862.04A&DSE/SIPAD4734,641.54 6AG13071KA014AA0SIPLUS S7-300 PS 307 10A FOR MEDIAL STA&DSE/SIPAD47150,443.23 6AG13082FL004AA3SIPLUS NET SCALANCE X308-2 FOR MEDIA6AG13125BE032AB0SIPLUS S7-300 CPU312C (32KB) -25 ... +70 A&DSE/SIPAD4739,541.02 6AG13125BE032AY0SIPLUS S7-300 CPU312C -25 ... +70 DERGR A&DSE/SIPAD47310,510.42 6AG13135BF032AB0SIPLUS S7-300 CPU313C (64KB) -25 ... +70 A&DSE/SIPAD47323,435.86 6AG13135BF032AY0SIPLUS S7-300 CPU313C -25 ... +70 DEGRE A&DSE/SIPAD47325,782.85 6AG13136CF032AB0SIPLUS S7-300 CPU313C-2DP(64KB) -25 ... A&DSE/SIPAD47332,449.66 6AG13136CF032AY0SIPLUS S7-300 CPU313C-2DP -25 ... +70 DEA&DSE/SIPAD47335,681.02 6AG13141AG142AY0SIPLUS S7-300 CPU314 -25 ... +60 DEGREE A&DSE/SIPAD47314,541.12 6AG13141AG147AB0SIPLUS S7-300 CPU314 -25 ... +70 DEGREE A&DSE/SIPAD47313,214.56 6AG13146CG032AB0SIPLUS S7-300 CPU314C-2DP(64KB) -25 ... A&DSE/SIPAD47344,745.83 6AG13146CG032AY0SIPLUS S7-300 CPU314C-2DP -25 ... +70 DEA&DSE/SIPAD47349,235.72A&DSE/SIPAD47332,143.53 6AG13152AG102AB0SIPLUS S7-300 CPU315-2DP -25 ... +70 DGR6AG13152AG104AB0SIPLUS S7-300 CPU 315-2DP FOR MEDIAL A&DSE/SIPAD47330,102.67 6AG13152AH142AY0SIPLUS S7-300 CPU 315-2DP -25 ... +60 DEGA&DSE/SIPAD47335,374.89A&DSE/SIPAD47332,143.53 6AG13152AH147AB0SIPLUS S7-300 CPU 315-2DP -25 ... +70 DEG6AG13152EH132AB0SIPLUS S7-300 CPU315-2 PN/DP (256KB) -2A&DSE/SIPAD47342,960.08 6AG13152EH132AY0SIPLUS S7-300 CPU315-2PN/DP -25 ... +70 DA&DSE/SIPAD47347,245.88 6AG13152FH132AB0SIPLUS S7-300 CPU315F-2PN/DP FOR -25 .A&DSE/SIPAD47350,834.39A&DSE/SIPAD47336,752.47 6AG13156FF042AB0SIPLUS S7-300 CPU 315F-2DP -25 ... +60 DE6AG13156FF042AY0SIPLUS S7-300 CPU 315F-2DP -25 ... +60 DEA&DSE/SIPAD47339,541.64 6AG13172EK132AB0SIPLUS S7-300 CPU317-2PN/DP (1MB), -25 A&DSE/SIPAD47376,192.07A&DSE/SIPAD47383,811.27 6AG13172EK132AY0SIPLUS S7-300 CPU317-2PN/DP -25 ... +60 D6AG13172FK132AB0SIPLUS S7-300 CPU317F-2PN/DP FOR -25 .A&DSE/SIPAD47381,889.47A&DSE/SIPAD47377,960.81 6AG13176FF032AB0SIPLUS S7-300 CPU317F-2DP (1MB) -25 ... +A&DSE/SIPAD47385,784.10 6AG13176FF032AY0SIPLUS S7-300 CPU317F-2DP -25 ... + 60 DG6AG13211BH022AA0SIPLUS S7-300 SM321 - 20-POLE -25 ... +60A&DSE/SIPAD4733,996.68 6AG13211BL002AA0SIPLUS S7-300 SM321 - 40-POLE -25 ... +70A&DSE/SIPAD4737,534.17 6AG13211CH202AA0SIPLUS S7-300 SM321 -25 ... +60 DGR C EN A&DSE/SIPAD4736,870.89 6AG13211FF012AA0SIPLUS S7-300 SM321 - 20-POLE -25 ... +60A&DSE/SIPAD4733,010.27 6AG13211FF107AA0SIPLUS S7-300 SM321 8 DI -25 ... +70 DEGRA&DSE/SIPAD4735,476.30 6AG13211FH007AA0SIPLUS S-7-300 SM321 16DI -40 ... +70 DEG A&DSE/SIPAD4735,578.35 6AG13217BH012AB0SIPLUS S7-300 SM321 - 20-POLE -25 ... +70A&DSE/SIPAD4737,534.17 6AG13217TH004AB0SIPLUS PCS7 SM321 16DE FOR MEDIAL ST A&DSE/SIPAD47316,922.12A&DSE/SIPAD4734,098.73 6AG13221BF012XB0SIPLUS S7-300 SM322 (-1BF01) -25...+60 DEA&DSE/SIPAD4735,289.23 6AG13221BH012AA0SIPLUS S7-300 SM322 - 20-POLE -25...+70 D6AG13221BL002AA0SIPLUS S7-300 SM322 32 DO - 40-POLE -25A&DSE/SIPAD47311,190.71 6AG13221CF007AA0SIPLUS S7-300 SM322 8DA 48-125V -25 ... +A&DSE/SIPAD4739,098.83 6AG13221FF017AA0SIPLUS S7-300 SM322 8DA 120/220 -40 ... +A&DSE/SIPAD4736,207.61 6AG13221FH007AA0SIPLUS S-7-300 SM322 16DO -40 ... +70 DE A&DSE/SIPAD4738,588.61 6AG13221HF102AA0SIPLUS S7-300 SM322 - 40-POLE -25 ... +60A&DSE/SIPAD4734,625.95 6AG13221HH012AA0SIPLUS S7-300 SM322 - 20-POLE -25 ... +60A&DSE/SIPAD4737,772.27A&DSE/SIPAD4737,381.11 6AG13225FF004AB0SIPLUS S7-300 SM322 8DO FOR MEDIAL STA&DSE/SIPAD4734,779.01 6AG13225HF004AB0SIPLUS S7-300 SM322 8RO 40PIN FOR MED6AG13228BF002AB0SIPLUS S7-300 SM322 - 20-POLE -25 ... +60A&DSE/SIPAD4738,758.69A&DSE/SIPAD47319,354.15 6AG13228BH012AB0SIPLUS S7-300 SM322 16DO DC24V -25 ... +6AG13231BH012AA0SIPLUS S7-300 SM323 - 20-POLE -25 ... +60A&DSE/SIPAD4735,697.406AG13261BK022AB0SIPLUS S7-300 SM326F DI24 40PIN -25 ... +A&DSE/SIPAD47324,779.43 6AG13261RF004AB0SIPLUS S7-300 SM326F DI8 NAMUR FOR M A&DSE/SIPAD47321,275.95 6AG13262BF012AB0SIPLUS S7-300 SM326F -25 ... +60 DGR C E A&DSE/SIPAD47326,888.32 6AG13311KF014AB0SIPLUS S7-300 SM331 8AI 40POL FOR MED A&DSE/SIPAD4739,660.07 6AG1331-1KF02-4AB0SIPLUS S7-300 SM331 8AE FOR MEDIAL STA&DSE/SIPAD4739,660.07 6AG13317KB022AB0SIPLUS S7-300 SM331 - 20-POLE -25 ... +70A&DSE/SIPAD4734,727.99A&DSE/SIPAD47314,132.95 6AG13317KF022AB0SIPLUS S7-300 SM331 20-POLE -25 ... +70 DA&DSE/SIPAD47313,282.59 6AG13317NF002AB0SIPLUS S7-300 SM331 40-POLE -25 ... +70 D6AG13317NF102AB0SIPLUS S7-300 SM331 8AI 40-POLE -25 ... +A&DSE/SIPAD47316,020.74 6AG13317PF012AB0SIPLUS S7-300 SM331 8AI - 40-POLE -25...+A&DSE/SIPAD47323,656.96A&DSE/SIPAD47316,684.02 6AG13317PF114AB0SIPLUS S7-300 SM331 8AI 40-POLE FOR ME6AG13317RD002AB0SIPLUS S7-300 SM331 4AI -25 ... +60 DEGR A&DSE/SIPAD47315,561.55A&DSE/SIPAD47315,221.41 6AG13317SF004AB0SIPLUS S7-300 SM331 - 20POLE MEDIAL STA&DSE/SIPAD47312,636.32 6AG13317TB004AB0SIPLUS S7-300 EM321 HART FOR MEDIAL S6AG13317TB007AB0SIPLUS S7-300 SM331 2AE HART -25 ... +70A&DSE/SIPAD47313,180.55 6AG13317TF014AB0SIPLUS SM332 AI 8 X 0/4...20MA FOR MEDI A&DSE/SIPAD47317,585.40 6AG13317TF017AB0SIPLUS SM332 AI 8 X 0/4...20MA -25 ... +70 A&DSE/SIPAD47319,966.40 6AG1332-1SH71-7AA0SIPLUS S7-1200 PM1207 -25 ... +70 DEGRE A&DSE/SIPAD4722,312.97 6AG13325HB012AB0SIPLUS S7-300 SM332 - 20-POLE -25 ... +70A&DSE/SIPAD4737,517.16 6AG13325HD014AB0SIPLUS S7-300 SM332 FOR MEDIAL STRES A&DSE/SIPAD47316,701.03A&DSE/SIPAD47312,789.38 6AG13325HD017AB0SIPLUS S7-300 SM332 4AO U/I -25 ... +70 DEA&DSE/SIPAD47322,534.48 6AG13325HF002AB0SIPLUS S7-300 SM332 40POLE -25...+70 DGA&DSE/SIPAD47321,309.97 6AG13325HF004AB0SIPLUS S7-300 SM332 8AO FOR MEDIAL STA&DSE/SIPAD47314,711.19 6AG13327ND024AB0SIPLUS S7-300 SM332 4AA FOR MEDIAL STA&DSE/SIPAD47326,480.14 6AG13328TF012AB0SIPLUS S7-300 SM332 8AO HART -25 ... +606AG13328TF014AB0SIPLUS S7-300 SM332 8AO HART FOR MEDA&DSE/SIPAD47323,350.83 6AG13340KE002AB0SIPLUS S7-300 SM334 - 20-POLE -25 ... +60A&DSE/SIPAD4738,826.71 6AG13340KE007AB0SIPLUS S7-300 SM334 4AI 2AO -25 ... +70 D A&DSE/SIPAD47310,799.55 6AG13342BA014AA0SIPLUS SMART 10A FOR MEDIAL STRESS A&DSE/SIPAD4715,615.91 6AG13343BA002AA0SIPLUS PS MODULAR 10A -40 ... +60 DEGR A&DSE/SIPAD4715,757.63 6AG13343BA004AA0SIPLUS PS MODULAR 10A FOR MEDIAL ST A&DSE/SIPAD4735,509.61 6AG13363BA007AA0SIPLUS PS MODULAR 20 -40 ... +70 DEGRE A&DSE/SIPAD4716,734.83 6AG13364GE004AB0SIPLUS S7-300 SM336F 6AE HART FOR ME A&DSE/SIPAD47321,088.88A&DSE/SIPAD47112,925.44 6AG13373BA004AA0SIPLUS PS MODULAR 40A IN 120/230VAC O6AG13401AH022AE0SIPLUS S7-300 CP340 RS 232 -25 ... +60 DE A&DSE/SIPAD47311,734.94A&DSE/SIPAD47313,180.55 6AG13401AH022AY0SIPLUS S7-300 CP340 RS232 -25 .. +60 DEG6AG13401CH022AE0SIPLUS S7-300 CP340 RS422/485 -25 ... + 6A&DSE/SIPAD47313,384.63 6AG13411AH027AE0SIPLUS S7-300, CP341 -25 ... +70 DEGREESA&DSE/SIPAD47320,408.59A&DSE/SIPAD47320,833.77 6AG13411CH027AE0SIPLUS S7-300 CP341 RS422/485 -25...+70 D6AG13425DA022XE0SIPLUS NET CP342-5 PROFIBUS -25 ... +60A&DSE/SIPAD47320,476.62 6AG13425DA024XE0SIPLUS NET CP342-5 FOR MEDIAL STRESSA&DSE/SIPAD47317,959.56A&DSE/SIPAD47119,031.01 6AG13431CX102XE0SIPLUS NET CP343-1 LEAN -25 ... +60 DEGRA&DSE/SIPAD47318,197.66 6AG13431CX104XE0SIPLUS NET CP343-1 LEAN FOR MEDIAL ST6AG13431EX304XE0SIPLUS NET CP343-1 FOR MEDIAL STRESSA&DSE/SIPAD47329,507.42 6AG13431EX307XE0SIPLUS NET CP343-1 -25 ... +70 DEGREES A&DSE/SIPAD47131,038.06A&DSE/SIPAD47344,388.68 6AG13431GX307XE0SIPLUS NET CP343-1 ADVANCED 0 ... +70 DA&DSE/SIPAD47310,357.36 6AG13501AH032AE0SIPLUS S7-300 FM350-1 -25 ... +60 DEGREEA&DSE/SIPAD47311,547.86 6AG13501AH032AY0SIPLUS S7-300 FM350-1 -25 ... + 60 GRAD C6AG13502AH014AE0SIPLUS S7-300 FM350-2 8 KANAELE FOR M A&DSE/SIPAD47326,412.12A&DSE/SIPAD4733,792.60 6AG13650BA012AA0SIPLUS S7-300 IM365 -25 ... +60 DGR C EN56AG14001JA014AA0SIPLUS PCS7 BGT UR2 9SLOT 2X RE FOR A&DSE/SIPAD47413,809.81 6AG14001TA012AA0SIPLUS S7-400 UR1 REDUNDANT FOR -25 .A&DSE/SIPAD47419,388.16A&DSE/SIPAD47418,809.92 6AG14002JA004AA0SIPLUS S7-400 RACK UR2-H FOR MEDIAL S6AG14002JA104AA0SIPLUS S7-400 MODULE UR2-H ALU FOR MA&DSE/SIPAD47424,677.39 6AG14050KA022AA0SIPLUS S7-400 PS405 10A -25...+70 DEGRE A&DSE/SIPAD47417,058.186AG14070KA024AA0SIPLUS S7-400 PS407 10A FOR MEDIAL ST A&DSE/SIPAD47413,333.61 6AG14070KR024AA0SIPLUS S7-400 PS407 10A REDUNDANT FO A&DSE/SIPAD47416,003.74 6AG14123HJ144AB0SIPLUS S7-400 CPU 412-3H FOR MEDIAL S A&DSE/SIPAD47457,773.32A&DSE/SIPAD474119,135.14 6AG14144HM144AB0SIPLUS S7-400 CPU414-4H FOR MEDIAL ST6AG14163ER054AB0SIPLUS S7-400 CPU416-3 PN/DP FOR MEDI A&DSE/SIPAD474185,088.90A&DSE/SIPAD474200,157.24 6AG14163XR054AB0SIPLUS S7-400 CPU416-3 FOR MEDIAL STR6AG14174HT144AB0SIPLUS S7-400 CPU417H FOR MEDIAL STR A&DSE/SIPAD474262,420.45A&DSE/SIPAD474233,746.38 6AG14174XT054AB0SIPLUS S7-400 CPU417-4 FOR MEDIAL STR6AG14211BL012AA0SIPLUS S7-400 SM421 32DE -25 ... +60 DEG A&DSE/SIPAD4746,632.79 6AG14221BL002AA0SIPLUS S7-400 SM422 32DA -25 ... +60 DEG A&DSE/SIPAD4749,711.09 6AG14310HH004AB0SIPLUS S7-400 SM431 16AE FOR MEDIAL S A&DSE/SIPAD47418,503.79A&DSE/SIPAD47448,470.40 6AG14311KF204AY0SIPLUS S7-400 SM431 BEG AI6X14 FOR ME6AG14321HF004AB0SIPLUS S7-400 SM432 8AA FOR MEDIAL STA&DSE/SIPAD47421,207.93 6AG14363BA007AA0SIPLUS PS MODULAR 20 3AC -25 ... +70 DE A&DSE/SIPAD4716,598.78A&DSE/SIPAD47113,464.00 6AG14373BA004AA0SIPLUS PS MODULAR 3AC 400-500V DC24VA&DSE/SIPAD47440,664.11 6AG14431EX204XE0SIPLUS NET CP443-1 FOR MEDIAL STRESSA&DSE/SIPAD47453,147.37 6AG14431GX204XE0SIPLUS NET CP443-1 ADVANCED FOR MEDA&DSE/SIPAD47440,664.11 6AG14435DX044XE0SIPLUS NET CP443-5 FOR MEDIAL STRESSA&DSE/SIPAD47415,731.62 6AG14501AP004AE0SIPLUS S7-400 FM450-1 FOR MEDIAL STREA&DSE/SIPAD4749,455.98 6AG14600AA012AB0SIPLUS S7-400 IM460-0 TX FOR -25 ... +60 DA&DSE/SIPAD4749,796.12 6AG14610AA012AA0SIPLUS S7-400 IM461-0 RX FOR -25 ... +60 D6AG15000EA022AA0SIPLUS NET PB CONNECTOR FOR -25 ... +A&DSE/SIPAD4711,479.62A&DSE/SIPAD4719,455.98 6AG15032CA002AA0SIPLUS NET OLM/P11 V4.0 -25 ... +60 DEGRA&DSE/SIPAD47112,415.23 6AG15032CB002AA0SIPLUS NET OLM/G11 V4.0 -25 ... +60 DEGR6AG15032CC004AA0SIPLUS NET OLM/G11-1300 V4.0 FOR MEDI A&DSE/SIPAD47131,429.23 6AG15033CA002AA0SIPLUS NET OLM/P12 V4.0 -25 ... +60 DEGRA&DSE/SIPAD47111,377.79A&DSE/SIPAD47117,976.57 6AG15033CB002AA0SIPLUS NET OLM/G12 V4.0 -25 ... +60 DEGR6AG15033CC004AA0SIPLUS NET OLM/G12-1300 V4.0 FOR MEDI A&DSE/SIPAD47139,116.46A&DSE/SIPAD47140,987.25 6AG15450BC152AX0SIPLUS HMI TP170B COLOR -10 ... +60 DEG6AG16071JC204AX2SIPLUS HMI OP7/DP FOR MEDIAL STRESS A&DSE/SIPAD47116,156.80A&DSE/SIPAD47120,408.59 6AG16071JC304AX2SIPLUS HMI OP7 FOR MEDIAL STRESS BASA&DSE/SIPAD47124,286.22 6AG16131CA024AE3SIPLUS C7-613 FOR MEDIAL STRESS BASE6AG16352EC024AE3SIPLUS C7-635 KEY FOR MEDIAL STRESS A&DSE/SIPAD47151,922.85 6AG16400AA002AX1SIPLUS S7-200 TD400C -10 ... +60 DEGREE A&DSE/SIPAD4728,810.65A&DSE/SIPAD47112,415.23 6AG16410CA014AX1SIPLUS HMI OP77B FOR MEDIAL STRESS B6AG16420BA014AX1SIPLUS HMI TP177B COLOR PN/DP FOR MEA&DSE/SIPAD47123,350.83 6AG16420BC014AX1SIPLUS HMI TP177B MONO DP FOR MEDIA A&DSE/SIPAD47118,707.87A&DSE/SIPAD47116,156.80 6AG16420BD014AX0SIPLUS HMI TP177B 4" COLOR PN/D FOR MA&DSE/SIPAD47125,833.87 6AG16420DA014AX1SIPLUS HMI OP177B TOUCH+KEY COL FOR6AG16420DC014AX1SIPLUS HMI OP177B TOUCH+KEY MON FO A&DSE/SIPAD47124,694.39A&DSE/SIPAD47127,296.49 6AG16420EA014AX0SIPLUS HMI MP177 6" FOR MEDIAL STRESS6AG16430AA014AX0SIPLUS HMI TP277 6" TOUCH FOR MEDIAL A&DSE/SIPAD47339,847.77A&DSE/SIPAD47157,484.19 6AG16430CD014AX1SIPLUS HMI MP277 10INCH TOUCH FOR ME6AG16440AA014AX0SIPLUS HMI MP377 12" TOUCH FOR MEDIA A&DSE/SIPAD47168,589.87 6AG16440AB014AX0SIPLUS HMI MP377 15ZOLL TOUCH FOR M A&DSE/SIPAD47185,954.18 6AG16470AE114AX0SIPLUS HMI KTP1000 BASIC COLOR DP 10A&DSE/SIPAD47147,124.00A&DSE/SIPAD47147,124.00 6AG16470AF114AX0SIPLUS HMI KTP1000 BASIC COLOR FOR MA&DSE/SIPAD47179,721.05 6AG16470AG114AX0SIPLUS HMI TP1500 BASIC COLOR P FOR M6AG16547HY007XA0SIPLUS S7 BUS MODULE FOR Y-COUPLER A&DSE/SIPAD4741,615.68 6AG16715AE104AX0SIPLUS CONNECT. BOX DP PLUS FU MOBI A&DSE/SIPAD47111,496.84 6AG16771DD004BA0SIPLUS S7 MEC EC31 FOR MEDIAL STRES A&DSE/SIPAD47344,881.89 6AG16771DD004BB0SIPLUS S7 MEC EC31-RTX FOR MEDIAL ST A&DSE/SIPAD47362,331.23A&DSE/SIPAD47130,442.81 6AG16883CD134AX0SIPLUS HMI PP17I FOR MEDIAL STRESS BA6AG16883ED134AX0SIPLUS HMI PP17II FOR MEDIAL STRESS B A&DSE/SIPAD47141,837.61A&DSE/SIPAD4722,822.72 6AG19013CB302XA0SIPLUS S7-200 PPI CABLE -25 ... +70 DGR C6AG19311SH022AA0SIPLUS LOGO! PS DC24V/1.3A -25 ... +70 D A&DSE/SIPAD4702,745.95 6AG19312BA003AA0SIPLUS PS 24V/0,375A DEW ALLOWABLE I A&DSE/SIPAD4703,135.69A&DSE/SIPAD4701,381.83 6AG19312BA103AA0SIPLUS PS 24V/0.5A DEW ALLOWABLE BASA&DSE/SIPAD4715,332.45 6AG19312EC212AA0SIPLUS PS DC-USV 24V/15A -25 ... + 60 DEGA&DSE/SIPAD4713,968.34 6AG19333BA002AA0SIPLUS PS MODULAR 5A -25 ... +60 DEGRE6AG19363BA004AA0SIPLUS PS MODULAR 20A FOR MEDIAL ST A&DSE/SIPAD4715,615.91A&DSE/SIPAD47416,071.76 6AG19521AL004AA0SIPLUS S7-400 MEMORY CARD 2MB FOR MA&DSE/SIPAD47425,425.70 6AG19521AM004AA0SIPLUS S7-400 MEMORY CARD 4MB FOR M6AG19521KT004AA0SIPLUS S7-400 MEMORY CARD 32MB FOR A&DSE/SIPAD47441,361.41A&DSE/SIPAD47411,871.00 6AG19601AA044XA0SIPLUS S7-400 SYNC MOD 10M FOR MEDIA6AG19601AB044XA0SIPLUS S7-400 SYNCH MODUL FOR MEDIA A&DSE/SIPAD47423,810.02A&DSE/SIPAD4712,037.32 6AG19613BA106AA0SIPLUS SITOP SIGNAL MODULE (HARD GO6AG19613BA107AA0SIPLUS PS SIGN. MODULE MODULAR -25 .A&DSE/SIPAD4712,072.75 6AG19613BA204AA0SIPLUS PS MODULAR REDUNDANCY MOD A&DSE/SIPAD4713,259.71 6AG19613BA207AA0SIPLUS PS RED. MODULE MODULAR -40 ...A&DSE/SIPAD4714,978.14 6AG19642AA042AB0SIPLUS S7-400 IF964-DP -25 ... +60 DEGRE A&DSE/SIPAD47410,340.35 6AG19720AA014XA0SIPLUS DP RS485-REPEATER FOR MEDIALA&DSE/SIPAD4736,972.93A&DSE/SIPAD4718,979.78 6AG19720AA017XA0SIPLUS DP RS485 REPEATER -25 ... +70 DEA&DSE/SIPAD47117,262.27 6AG19720AB014XA0SIPLUS DP DIAGNOSIS-REPEATER FOR ME6AG19720BA122XA0SIPLUS DP PB CONNECTOR W R - 90 DEG A&DSE/SIPAD4711,105.47 6AG19720BA412XA0SIPLUS DP PB CONNECTOR W R - TILTED A&DSE/SIPAD4711,105.47A&DSE/SIPAD4711,105.47 6AG19720BB122XA0SIPLUS DP PB-CONNECTOR M R - M PG - 96AG19720BB412XA0SIPLUS DP PB-CONNECTOR WITH R - W P A&DSE/SIPAD4711,105.47A&DSE/SIPAD4732,210.93 6AG19720DA002AA0SIPLUS DP TERMINATOR RS485 -25...+60 DIC2020435,100.77 6AG40112CA310XX0SIMATIC RACK PC IL 43 INTERFACES: 1X GIC2020444,044.64 6AG40112DA232KY0SIMATIC RACK PC IL 43 INTERFACES: 1X GIC2020450,791.77 6AG40112DJ222KX0SIMATIC RACK PC IL 43 INTERFACES: 1X G6AV19010BD00PUFFERBATTERIE FUER RAM-CARDS3,0 V ST80E2H1674.47 6AV30171NE300AX0TEXTANZEIGE TD17LC-DISPLAY, LED HINT ST80E2H313,372.48ST80E2H311,523.20 6AV30171NE300AX1TEXT DISPLAY TD17 LC DISPLAY, BACK-LIT6AV35031DB10OPERATOR PANEL OP3MIT KABEL FUER A ST80E2H05,683.30 6AV35732AT00ERSATZHINTERLEUCHTUNGFUER IW30, O ST80E2H04,178.90ST80E2H09,193.58 6AV36071JC000AX1OPERATOR PANEL OP7/PPLC-DISPLAY, LE6AV36071JC200AX1OPERATOR PANEL OP7/DP LC DISPLAY, B ST80E2H06,379.18 6AV36071JC200AX2OPERATOR PANEL OP7/DP LC DISPLAY, B ST80E2H09,203.23 6AV36071JC300AX1OPERATOR PANEL OP7/DP12LC-DISPLAY,ST80E2H011,868.08 6AV36071JC300AX2OPERATOR PANEL OP7/DP12 LC DISPLAY,ST80E2H011,941.39 6AV36075AA000AC0OPERATOR PANEL OP7/PP6AV3607-1JC00ST80E2Y78,885.04 6AV36075BA000AC0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80E2Y78,885.04 6AV36075BA000AK0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80922Y78,885.04 6AV36075BB000AF0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80922Y710,689.82 6AV36075BB000AG0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80XX2Z78,252.78 6AV36075BB000AH0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80922Y78,989.16 6AV36075BB000AL0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80E2Y78,989.16 6AV36075BC001AH0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80922Z78,125.32 6AV36075CA000AD0OPERATOR PANEL OP7/DP126AV3607-1JC ST80E2Y711,314.55 6AV36075CB000AL0OPERATOR PANEL OP7/DP6AV3607-1JC20ST80922Z76,579.92 6AV36171JC000AX1OPERATOR PANEL OP17/PPLC-DISPLAY, L ST80E2H020,894.50 6AV36171JC000AX2OPERATOR PANEL OP17/PP L C DISPLAY, BST80E2H023,973.09 6AV36171JC200AX2OPERATOR PANEL OP17/DP LC DISPLAY, ST80E2H021,829.16 6AV36171JC300AX1OPERATOR PANEL OP17/DP12LC-DISPLAY ST80E2H025,073.40 6AV36171JC300AX2OPERATOR PANEL OP17/DP12 L C DISPLAY ST80E2H026,164.57 6AV36175BA000BC0OPERATOR PANEL OP17/DP6AV3617-1JC2ST80922Y720,251.65 6AV36175BB000AB1OPERATOR PANEL OP17/DP6AV3617-1JC2ST80E2Y720,251.65 6AV36175BB000AJ0OPERATOR PANEL OP17/DP6AV3617-1JC2ST80922Y720,251.65。

3.5
On-State Current (A)
300
102
Tj = 150°C
200
101
Tj = 25°C
100
100 0.5
1.0
1.5
2.0
2.5
3.0
0 100
101
102
On-State Voltage (V)
Conduction Time (Cycles at 50Hz)
Gate Trigger Current (Tj = t°C) × 100 (%) Gate Trigger Current (Tj = 25°C)
30
40
RMS On-State Current (A)
RMS On-State Current (A)
Allowable Ambient Temperature vs. RMS On-State Current
160
160 160 t2.3
Allowable Ambient Temperature vs. RMS On-State Current
0
40
80
120
160
Gate Current (mA)
Junction Temperature (°C)
Gate Trigger Voltage (Tj = t°C) × 100 (%) Gate Trigger Voltage (Tj = 25°C)
Gate Trigger Voltage vs. Junction Temperature
Typical value Ta = 25°C, AC 1 minute, T1 • T2 • G terminal to case

ispXPGA FamilyMarch 2003Preliminary Data SheetTM© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at /legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The speci fications and information herein are subject to change without notice.■Non-volatile, In finitely Recon figurable•Instant-on - Powers up in microseconds via on-chip E 2CMOS ® based memory •No external con figuration memory•Excellent design security , no bit stream to intercept •Recon figure SRAM based logic in milliseconds■High Logic Density for System-levelIntegration•139K to 1.25M system gates •160 to 496 I/O•1.8V , 2.5V , and 3.3V V CC operation•Up to 414Kb sysMEM™ embedded memory■High Performance Programmable FunctionUnit (PFU)•Four LUT -4 per PFU supports wide and narrow functions•Dual flip-flops per LUT -4 for extensive pipelining •Dedicated logic for adders, multipliers, multiplex-ers, and counters■Variable-Length Interconnect RoutingTechnology•Optimum speed, power, and flexibility for logic interconnections■ Flexible Memory Resources•Multiple sysMEM Embedded RAM Blocks–Single port, Dual port, and FIFO operation •64-bit distributed memory in each PFU–Single port, Double port, FIFO, and Shift Register operation■ Eight sysCLOCK™ Phase Locked Loops(PLLs) for Clock Management•T rue PLL technology•10MHz to 320MHz operation •Clock multiplication and division •Phase adjustment•Shift clocks in 250ps steps■ sysIO™ for High System Performance•High speed memory support through SSTL and HSTL•Advanced buses supported through PCI, GTL+, LVDS, BLVDS, and LVPECL•Standard logic supported through LVTTL, LVCMOS 3.3, 2.5, and 1.8•Programmable drive strength for series termination •Programmable bus maintenance■ sysHSI™ Capability for Ultra Fast SerialCommunications•Up to 850Mbps performance •Up to 20 channels per device•Built in Clock Data Recovery (CDR) and Serialization and De-serialization (SERDES)■ Flexible Programming, Recon figuration,and Testing•IEEE 1532 and 1149.1 compliant•Microprocessor con figuration interface•Program E 2 CMOS while operating from SRAMTable 1. ispXPGA Family Selection GuideispXPGA 125ispXPGA 200ispXPGA 500ispXPGA 1200System Gates 139K 210K 476K 1.25M PFUs 48467617643844LUT -4s 19362704705615376Logic FFs 3.8K 5.4K 14.1K 30.7K sysMEM Memory 92K 111K 184K 414K Distributed Memory 30K 43K 112K 246K EBR20244090sysHSI Channels 481220User I/O 160/176160/208336496Packaging256 fpBGA 516 fpBGA 1256 fpBGA 516 fpBGA 1516 fpBGA 1 900 fpBGA680 fpSBGA 1 900 fpBGA1.Thermally enhanced package.Note: LFX1200B/C is preliminary, LFX125/200/500B/C information is advanced.Lattice Semiconductor ispXPGA Family Data SheetispXPGA Family OverviewThe ispXPGA family of devices allows the creation of high-performance logic designs that are both non-volatile andinfinitely re-programmable. Other FPGA solutions force a compromise being either re-programmable or non-vola-tile. This family couples this capability with a mainstream architecture containing the features required for today’ssystem-level design.Electrically Erasable CMOS (E2CMOS) memory cells provide the ispXPGA family with non-volatile capability.These allow logic to be functional microseconds after power is applied, allowing easy interfacing in many applica-tions. This capability also means that expensive external configuration memories are not required and that designs can be secured from unauthorized read back. Internal SRAM cells allow the device to be infinitely reconfigured if desired. Both the SRAM and E2CMOS cells can be programmed and verified through the IEEE 1532 industry stan-dard. Additionally, the SRAM cells can be configured and read-back through the sysCONFIG™ peripheral port.The family spans the density and I/O range required for the majority of today’s logic designs, 139K to 1.25M systemgates and 160 to 496 I/O. The devices are available for operation from 1.8V, 2.5V, and 3.3V power supplies, provid-ing easy integration into the overall system.The system-level needs of designers are met through the incorporation of sysMEM dual-port memory blocks,sysIO advanced I/O support, and sysCLOCK Phase Locked Loops (PLLs). High-speed serial communications aresupported through multiple sysHSI blocks, which provide clock data recovery (CDR) and serialization/de-serializa-tion (SERDES).The ispLEVER™ design tool from Lattice allows designers easy implementation of designs using the ispXPGAproduct. Synthesis library support is available for the major logic synthesis tools. The ispLEVER tool takes the out-put from these common synthesis packages and place and routes the design in the ispXPGA product. The toolallows floor planning and the management of other constraints within the device. The tool also provides outputs tocommon timing analysis tools for timing analysis.T o increase designer productivity, Lattice provides a variety of pre-designed modules referred to as IP cores for theispXPGA product. These IP cores allow designers to concentrate on the unique portions of their design while usingpre-designed block to implement standard functions such as bus-interfaces, standard communication-interfaces,and memory-controllers.Through the use of advanced technology and innovative architecture the ispXPGA FPGA devices provide design-ers with excellent speed performance. Although design dependent, many typical designs can run at over 150MHz.Certain designs can run at over 300MHz. T able 2 details the performance of several building blocks commonlyused by logic designers.Table 2. ispXPGA Speed Performance for Typical Building BlocksFunction Performance8:1 Asynch MUX150 MHz1:32 Asynch Demultiplexer125 MHz8 x 8 2-LL Piped Multiplier225 MHz32-bit Up/Down Counter290 MHz32-bit Shift Register360 MHzLattice Semiconductor ispXPGA Family Data SheetArchitecture OverviewThe ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIOblocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and thesysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-ily implement their designs, since any logic function can be placed in any section of the device.The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They areoptimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registeredquickly to minimize setup times for high-speed designs. They also allow connections directly to the different logicelements for fast access to combinatorial functions.The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-age types. They are designed to facilitate both single and dual-port memory for high-speed applications.These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additionalrouting available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers canbe configured to interface with 16 different I/O standards. This allows ispXPGA to interface with other devices with-out the need for external transceivers.The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to850Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery(CDR) logic.The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increasedperformance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block foreach global clock tree in the device.Lattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice Semiconductor ispXPGA Family Data SheetLattice SemiconductorispXPGA Family Data SheetTable 5. ispXPGA Supported I/O StandardsTable 6. Differential Interface Standard Support 1sysIO StandardV CCO V REF V TT LVTTL 3.3V N/A N/A LVCMOS-3.3 3.3V N/A N/A LVCMOS-2.5 2.5V N/A N/A LVCMOS-1.8 1.8V N/A N/A PCI 3.3V N/A N/A AGP-1X3.3V N/A N/A SSTL3, Class I, II 3.3V 1.5V 1.5V SSTL2, Class I, II 2.5V 1.25V 1.25V HSTL, Class I 1.5V 0.75V 0.75V HSTL, Class III 1.5V 0.9V 1.5V GTL+N/A 1.0V 1.5V LVPECL 3.3V N/A N/A LVDS 1 2.5V N/A N/A BLVDS2.5VN/AN/A1.V CCO must be2.5V for high speed serial operations (sysHSI block).sysIO Buffer Not Using sysHSI BlocksysIO Buffer Using sysHSI Block LVDS Driver Supported with external resistor network SupportedReceiver Supported with standard termination Supported with standard termination BLVDS Driver Supported with external resistor network Not supportedReceiver Supported (may need termination)Supported (may need termination)LVPECLDriver Supported with external resistor network Not supportedReceiverSupported with terminationSupported with termination1.For more information, refer to Lattice technical note TN1000, sysIO Usage Guidelines,available at .Lattice Semiconductor ispXPGA Family Data SheetTable 7. sysHSI Block REFCLK Selections1sysHSI Block Available Global Clock Nets0CLK0, CLK1, CLK2, CLK31CLK0, CLK1, CLK2, CLK42CLK0, CLK1, CLK2, CLK53CLK0, CLK1, CLK3, CLK64CLK0, CLK1, CLK3, CLK75CLK0, CLK3, CLK5, CLK76CLK0, CLK2, CLK5, CLK77CLK0, CLK1, CLK5, CLK68CLK0, CLK5, CLK69CLK0, CLK5, CLK6, CLK71.T able 6 applies to all devices. Ignore sysHSI blocks not availablein a specific device.Configuration and ProgrammingThe ispXPGA family of devices takes a unique approach to FPGA configuration memory. It contains two types of memory, Static RAM and non-volatile E2CMOS cells. The static RAM is used to control the functionality of the device during normal operation and the E2CMOS memory cells are used to load the SRAM. The E2CMOS memory module can be thought of as the hard drive for the ispXPGA configuration and the SRAM as the working configura-tion memory. There is a one-to-one relationship between SRAM memory and the E2CMOS cells. The SRAM can be configured either from the E2CMOS memory or from an external source, as shown in Figure 21.Figure 21 shows the different ports and modes that are used in the configuration and programming of the ispXPGA devices. There are two possible ports that can be used for configuration of the SRAM memory: the ISP port which is compliant to the IEEE 1149.1 T est Access Port (T AP) Std. and the ISP port which accommodates bit-wide config-uration. The sysCONFIG port allows byte-wide configuration of the SRAM configuration memory. When program-ming the E2CMOS memory, only the 1149.1 T AP can be used.Configuration and programming done through the 1149.1 T est Access Port (T AP) are fully compliant to both the IEEE Std. 1149.1 Boundary Scan T AP specification and the IEEE Std. 1532 In-System Configuration specification. T o configure or program the device using the 1149.1 T AP the device must be in the ISP mode. T o configure the SRAM memory using the sysCONFIG Port, the device must be in the sysCONFIG mode. Upon power-up, the device’s SRAM memory can be configured either from the E2CMOS memory or from an external source through the sysCONFIG mode. Additionally, the SRAM can be re-configured from the E2CMOS memory by executing a “REFRESH.” See Lattice technical note number TN1026, is pXP Configuration Us age Guide, for more in depth information on the different programming modes, timing and wake-up, available at .Absolute Maximum Ratings 1, 2, 31.8V2.5V/3.3VSupply Voltage (V CC ). . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V PLL Supply Voltage (V CCP ) . . . . . . . . . . . . . . . . . -0.5 to 2.5V . . . . . . . . . .-0.5 to 5.5V Output Supply Voltage (V CCO ). . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V IEEE 1149.1 T AP Supply Voltage (V CCJ ). . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Input Voltage Applied 4 . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.5V . . . . . . . . . .-0.5 to 4.5V Storage T emperature . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C. . . . . . . . . -65 to 150°C Junction T emperature (T J ) with Power Applied . .-55 to 150°C. . . . . . . . . -55 to 150°C1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci fication is not implied (while programming, following the programming speci fications).2. Compliance with the Lattice Thermal Management technical note is required.3. All voltages referenced to GND.4. Overshoot and undershoot of -2V to (V IH (MAX) + 2) volts is permitted for a duration of <20nsRecommended Operating ConditionsE 2CMOS Erase Reprogram Speci ficationsHot Socketing Characteristics 1, 2, 3, 4SymbolParameterMin Max Units V CCSupply Voltage for 1.8V device1.65 1.95V Supply Voltage for2.5V device 2.3 2.7V Supply Voltage for3.3V device3.0 3.6V V CCPSupply Voltage for PLL block for 1.8V device1.65 1.95V Supply Voltage for PLL block for2.5V device 2.3 2.7V Supply Voltage for PLL block for3.3V device3.0 3.6V V CCJ Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS 1.8V1.65 1.95V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS2.5V 2.3 2.7V Supply Voltage for IEEE 1149.1 T est Access Port for LVCMOS3.3V 3.0 3.6V T J (COM)Junction T emperature Commercial Operation 085C T J (IND)Junction T emperature Industrial Operation-40105CParameterMin Max Units Erase/Reprogram Cycle 11,000—Cycles1.Valid over commercial temperature range.Symbol ParameterConditionMin Typ Max Units I DKInput or I/O Leakage Current0 ≤ V IN ≤ 3.0V—+/-50+/-800µA1. Insensitive to sequence of V CC and V CCO . However, assumes monotonic rise / fall rates for V CC and V CCO .2. LVTTL, LVCMOS only3. 0 < V CC ≤ V CC (MAX), 0 < V CCO ≤ V CCO (MAX)4.I DK is additive to I PU , I PD or I BH . Device defaults to pull-up until fuse circuitry is active.DC Electrical CharacteristicsOver Recommended Operating ConditionsSupply CurrentOver Recommended Operating ConditionsSymbol ParameterConditionMin Typ Max Units I IL , I IH 1Input or I/O Low Leakage 0 ≤ V IN < (V CCO - 0.2V)——10µA (V CCO - 0.2V) ≤ V IN ≤ 3.6V ——40µA I PU I/O Active Pull-up Current 0 ≤ V IN ≤ 0.7 V CCO30—150µA I PD I/O Active Pull-down CurrentV IL (MAX) ≤ V IN ≤ V IH (MAX)30—150µA I BHLS Bus Hold Low Sustaining Current V IN = V IL (MAX)30——µA I BHHS Bus Hold High Sustaining Current V IN = 0.7 V CCO 30——µA I BHLO Bus Hold Low Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA I BHHO Bus Hold High Overdrive Current 0 ≤ V IN ≤ V IH (MAX)——150µA V BHT Bus Hold T rip Points V CCO * 0.35—V CCO * 0.65V C 1I/O Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—8—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 2Clock Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pf V CC = 1.8V , V IO = 0 to V IH (MAX) ——C 3Global Input Capacitance 2V CCO = 3.3V , 2.5V , 1.8V—6—pfV CC = 1.8V , V IO = 0 to V IH (MAX)——1.Input or I/O leakage current is measured with the pin con figured as an input or as an I/O with the output driver tri-stated. It is not measured with the output driver active. Bus maintenance circuits are disabled.2.T A = 25°C, f = 1.0MHz.Symbol ParameterCondition Min Typ Max Units I CC 1, 2Standby Core Operating Power Supply CurrentV CC = 3.3V —220—mA V CC = 2.5V —220—mA V CC = 1.8V —200—mA I CCO 3Standby Output Power Supply CurrentV CCO = 3.3V— 2.0—mA V CCO = 2.5V — 2.0—mA V CCO = 1.8V — 2.0—mA V CCO = 1.5V — 2.0—mA I CCP 4Standby PLL Operating Supply CurrentV CCP = 3.3V—17.0—mA V CCP = 2.5V —17.0—mA V CCP = 1.8V —15.0—mA I CCJ 5Standby IEEE 1149.1 T AP Power Supply CurrentV CCJ = 3.3V— 2.0—mA V CCJ = 2.5V — 1.5—mA V CCJ = 1.8V—1.0—mA1.T A = 25˚C, frequency = 1.0 MHz, device con figured with 16-bit counters.2.I CC varies with speci fic device con figuration and operating frequency. For more accurate power calculation use the ispXPGA Power Estimator.3.T A = 25˚C, per bank, no DC load, frequency = 0 MHz.4.T A = 25˚C, per PLL, frequency = 10 MHz.5.T A = 25˚CsysIO Differential Standards DC Electrical CharacteristicsParameter Description Test Conditions Min.Typ.Max. LVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM RT = 100 Ohm— 1.38V 1.60V V OL Output Low Voltage for V OP or V OM RT = 100 Ohm0.9V 1.03V—V OD Output Voltage Differential|V OP - V OM|, R T = 100 ohm250mV350mV450mV ∆V OD Change in V OD between high and low——50mVV OS Output Voltage Offset|V OP + V OM|/2, R T = 100 ohm 1.125V 1.25V 1.375V ∆V OS Change in V OS between H and L——50mV——24mA I OSD Output short circuit current V OD = 0V Driver outputsshortedBLVDS1V INP, V INM Input voltage 0V— 2.4V V THD Differential input threshold+/-100mV——V CM Input Common Mode voltage Half the sum of the two inputs 0.05V— 2.35V I IN Input current Power on or Power off ——+/-10uA V OH Output High Voltage for V OP or V OM R T = 27Ω— 1.4V 1.80V V OL Output Low Voltage for V OP or V OM R T = 27Ω0.95V 1.1V—V OD Output Voltage Differential|V OP - V OM|, RT = 27Ω240mV300mV460mV ∆V OD Change in V OD Between H and L27mV V OS Output Voltage Offset|V OP + V OM| /2, RT = 27Ω 1.1V 1.3V 1.5V ∆V OS Change in V OS Between H and L27mVI OSD Output Short Circuit Current V OD = 0. Driver Outputs36mA65mAShorted.1.V OP and V OM are the two outputs of the LVDS/BLVDS output buffer.LVPECL1DCParameter Parameter Description Min.Max.Min.Max.Min.Max.Units V CCO 3.0 3.3 3.6V V IH Input Voltage High 1.49 2.72 1.49 2.72 1.49 2.72V V IL Input Voltage Low0.86 2.1250.86 2.1250.86 2.125V V OH Output Voltage High 1.8 2.11 1.92 2.28 2.13 2.41V V OL Output Voltage Low0.96 1.27 1.06 1.43 1.3 1.57V V DIFF Differential Input voltage0.3—0.3—0.3—V 1.These values are valid at the output of the source termination pack as shown above with 100-ohm differential load only (see Figure 22). The V OH levels are 200mV below the standard LVPECL levels and are compatible with devices tolerant of the lower common mode ranges.ispXPGA PFU Timing ParametersOver Recommended Operating ConditionsParameter Description-4-3Units Min.Max.Min.Max.Functional DelaysLUTst LUT44-Input LUT Delay—0.44—0.51ns t LUT55-Input LUT Delay—0.79—0.91ns t LUT66-Input LUT Delay—0.93— 1.07ns Shift Register (LUT)t LSR_S Shift Register Setup Time-0.62—-0.53—ns t LSR_H Shift Register Hold Time0.63—0.72—ns t LSR_CO Shift Register Clock to Output Delay—0.75—0.86ns Arithmetic Functionst LCTHRUR MC (Macro Cell) Carry In to MC Carry Out Delay (Rip-ple)—0.09—0.10ns t LCTHRUL1MC Carry In to MC Carry Out Delay (Look Ahead)—0.05—0.06ns t LSTHRU MC Sum In to MC Sum Out Delay—0.45—0.52ns t LSINCOUT MC Sum In to MC Carry Out Delay—0.31—0.36ns t LCINSOUTR MC Carry In to MC Sum Out Delay (Ripple)—0.39—0.45ns t LCINSOUTL MC Carry In to MC Sum Out Delay (Look Ahead)—0.28—0.32ns Feed-thrut LFT PFU Feed-Thru Delay—0.16—0.18ns Distributed RAMt LRAM_CO Clock to RAM Output— 1.33— 1.53ns t LRAMAD_S Address Setup Time-0.40—-0.34—ns t LRAMD_S Data Setup Time0.22—0.25—ns t LRAMWE_S Write Enable Setup Time0.46—0.53—ns t LRAMAD_H Address Hold Time0.60—0.69—ns t LRAMD_H Data Hold Time0.11—0.13—ns t LRAMWE_H Write Enable Hold Time0.12—0.14—ns t LRAMCPW Clock Pulse Width (High or Low) 3.00— 3.45—ns t LRAMADO Address to Output Delay—0.93— 1.07ns Register/Latch DelaysRegisterst L_CO Register Clock to Output Delay—0.62—0.71ns t L_S Register Setup Time (Data before Clock)0.14—0.16—ns t L_H Register Hold Time (Data after Clock)-0.12—-0.10—ns t LCE_S Register Clock Enable Setup Time-0.11—-0.09—ns t LCE_H Register Clock Enable Hold Time0.11—0.13—ns Latchest L_GO Latch Gate to Output Delay—0.10—0.12ns t LL_S Latch Setup Time0.14—0.16—ns t LL_H Latch Hold Time-0.12—-0.10—ns t LLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12nsispXPGA PIC Timing ParametersReset/Sett LASSRO Asynchronous Set/Reset to Output — 1.17— 1.35ns t LASSRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t LASSRR Asynchronous Set/Reset Recovery —0.55—0.63ns t LSSR_S Synchronous Set/Reset Setup Time -0.03—-0.03—ns t LSSR_HSynchronous Set/Reset Hold Time0.03—0.03—ns1.t LCTHRUL quoted bit by bit.Timing v.2.0Parameter Description -4-3UnitsMin.Max.Min.Max.Register/Latch Delays t IO_CO Register Clock to Output Delay— 1.09— 1.25ns t IO_S Register Setup Time (Data before Clock)0.05—0.06—ns t IO_H Register Hold Time (Data after Clock)0.06—0.07—ns t IOCE_S Register Clock Enable Setup Time -0.03—-0.03—ns t IOCE_H Register Clock Enable Hold Time 0.13—0.15—ns t IO_GO Latch Gate to Output Delay —0.91— 1.05ns t IOL_S Latch Setup Time 0.05—0.06—ns t IOL_H Latch Hold Time0.06—0.07—ns t IOLPD Latch Propagation Delay (T ransparent Mode)—0.10—0.12ns t IOASRO Asynchronous Set/Reset to Output — 1.26— 1.45ns t IOASRPW Asynchronous Set/Reset Pulse Width — 4.50— 5.18ns t IOASRR Asynchronous Set/Reset Recovery Time —0.25—0.29ns Input/Output Delayst IOBUF Output Buffer Delay — 1.06— 1.22ns t IOIN Input Buffer Delay —0.76—0.87ns t IOEN Output Enable Delay —0.56—0.64ns t IODIS Output Disable Delay —-0.10—-0.09ns t IOFTFeed-thru Delay—0.20—0.23nsTiming v.2.0ispXPGA PFU Timing Parameters (Continued)Over Recommended Operating ConditionsParameterDescription-4-3Units Min.Max.Min.Max.ispXPGA EBR Timing ParametersParameter Description-4-3Units Min.Max.Min.Max.Synchronous Writet EBSWAD_S Address Setup Delay0.61—0.70—nst EBSWAD_H Address Hold Delay-0.39—-0.33—nst EBSWCPW Clock Pulse Width— 3.40— 3.91nst EBSWWE_S Write Enable Setup Time-0.12—-0.10—nst EBSWWE_H Write Enable Hold Time0.16—0.18—nst EBSWD_S Data Setup Time0.28—0.32—nst EBSWD_H Data Hold Time-0.26—-0.22—ns Synchronous Readt EBSR_CO Clock to Data Delay— 2.19— 2.52nst EBSRAD_S Address Setup Delay0.10—0.12—nst EBSRAD_H Address Hold Delay-0.07—-0.06—nst EBSRCPW Clock Pulse Width— 3.40— 3.91nst EBSRCE_S Clock Enable Setup Time-1.71—-1.45—nst EBSRCE_H Clock Enable Hold Time 1.69— 1.94—nst EBSRWE_S Write Enable Setup Time-0.17—-0.14—nst EBSRWE_H Write Enable Hold Time0.12—0.14—nst EBSRWEEN Write Enable to Data Enable Time— 1.05— 1.21nst EBSRWEDIS Write Enable to Data Disable Time— 1.02— 1.17nst EBSREN Output Enable to Data Enable Time— 1.05— 1.21nst EBSRDIS Output Enable to Data Disable Time—0.86—0.99ns Asynchronous Readt EBARADO Address to New Valid Data Delay— 2.46— 2.83nst EBARAD_H Address to Previous Valid Data Delay— 2.17— 2.50nst EBARWEEN Write Enable to Data Enable Time— 1.04— 1.20nst EBARWEDIS Write Enable to Data Disable Time— 1.01— 1.16nst EBAREN Output Enable to Data Enable Time— 1.05— 1.21nst EBARDIS Output Enable to Data Disable Time—0.86—0.99nsTiming v.2.0ispXPGA Family Timing AddersParameter DescriptionBaseParameter-4-3Units Min.Max.Min.Max.Optional Adderst INDIO Input Delay—— 6.0— 6.9ns t IOI Input AdjustersLVTTL_in Using 3.3V TTL t IOIN— 0.5—0.5ns LVCMOS_18_in Using 1.8V CMOS t IOIN— 0.0—0.0ns LVCMOS_25_in Using 2.5V CMOS t IOIN— 0.3—0.3ns LVCMOS_33_in Using 3.3V CMOS t IOIN— 0.5—0.5ns AGP_1X_in Using AGP 1x t IOIN— 1.0— 1.0ns CTT25_in Using CTT 2.5V t IOIN— 1.0— 1.0ns CTT33_in Using CTT 3.3V t IOIN— 1.0— 1.0ns GTL+_in Using GTL+t IOIN— 0.5—0.5ns HSTL_I_in Using HSTL 2.5V, Class I t IOIN—0.5—0.5ns HSTL_III_in Using HSTL 2.5V, Class III t IOIN—0.5—0.5ns LVDS_in Using Low VoltageDifferential Signaling (LVDS)t IOIN— 0.8—0.8nsBLVDS_in Using Bus Low VoltageDifferential Signaling (BLVDS)t IOIN—0.8—0.8ns LVPECL_in Using Low Voltage PECL t IOIN— 0.8—0.8ns PCI_in Using PCI t IOIN— 1.0— 1.0ns SSTL2_I_in Using SSTL 2.5V, Class I t IOIN— 0.8—0.8ns SSTL2_II_in Using SSTL 2.5V, Class II t IOIN— 0.5—0.5ns SSTL3_I_in Using SSTL 3.3V, Class I t IOIN— 0.8—0.8ns SSTL3_II_in Using SSTL 3.3V, Class II t IOIN— 0.8—0.8ns t IOO Output AdjustersSlow Slew Using Slow Slew (LVTTL andLVCMOS Outputs only)t IOBUF, t IOEN—0.7—0.7nsLVTTL_out Using 3.3V TTL Drive t IOBUF, t IOEN,t IODIS— 1.0 — 1.0 nsLVCMOS_18_4mA_out Using 1.8V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.8—0.8nsLVCMOS_18_5.33mA_out Using 1.8V CMOS Standard,5.33mA Drive t IOBUF, t IOEN,t IODIS—0.6—0.6nsLVCMOS_18_8mA_out Using 1.8V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.0—0.0nsLVCMOS_18_12mA_out Using 1.8V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.2—0.2nsLVCMOS_25_4mA_out Using 2.5V CMOS Standard,4mA Drive t IOBUF, t IOEN,t IODIS—0.7—0.7nsLVCMOS_25_5.33mA_out Using 2.5V CMOS Standard,5.33 mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_8mA_out Using 2.5V CMOS Standard,8mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_12mA_out Using 2.5V CMOS Standard,12mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_25_16mA_out Using 2.5V CMOS Standard,16mA Drive t IOBUF, t IOEN,t IODIS—0.5—0.5nsLVCMOS_33_4mA_outUsing 3.3V CMOS Standard, 4mA Drive t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns LVCMOS_33_5.33mA_out Using 3.3V CMOS Standard, 5.33mA Drive t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVCMOS_33_8mA_out Using 3.3V CMOS Standard, 8mA Drivet IOBUF , t IOEN, t IODIS —0.7—0.7ns LVCMOS_33_12mA_out Using 3.3V CMOS Standard, 12mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_16mA_out Using 3.3V CMOS Standard, 16mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns LVCMOS_33_24mA_out Using 3.3V CMOS Standard, 24mA Drivet IOBUF , t IOEN, t IODIS —0.5—0.5ns AGP_1X_out Using AGP 1x Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT25_out Using CTT 2.5V t IOBUF , t IOEN, t IODIS—0.5—0.5ns CTT33_out Using CTT 3.3V t IOBUF , t IOEN, t IODIS—0.5—0.5ns GTL+_out Using GTL+t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_I_out Using HSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns HSTL_III_out Using HSTL 2.5V , Class III t IOBUF , t IOEN, t IODIS—0.5—0.5ns LVDS_out Using Low Voltage Differen-tial Signaling (LVDS)t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns BLVDS_out Using Bus Low Voltage Differ-ential Signaling (BLVDS)t IOBUF , t IOEN,t IODIS — 1.0— 1.0ns LVPECL_out Using Low Voltage PECL t IOBUF , t IOEN, t IODIS— 1.0— 1.0ns PCI_out Using PCI Standard t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_I_out Using SSTL 2.5V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL2_II_out Using SSTL 2.5V , Class II t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_I_out Using SSTL 3.3V , Class I t IOBUF , t IOEN, t IODIS—0.5—0.5ns SSTL3_II_outUsing SSTL 3.3V , Class IIt IOBUF , t IOEN, t IODIS—0.5—0.5nsTiming v.2.0ispXPGA Family Timing Adders (Continued)ParameterDescriptionBase Parameter-4-3Units Min.Max.Min.Max.。