DG9415中文资料

description :33% Umgebungstemperatur / temperature:+20°CIt is recommended that the temperature of the part does MST09-02-09MST 04-10-11NameDatum / dateFreigabe erteilt / general release:Kunde / customerWürth Elektronik...............................................................................http://www.we-online.deE Testbedingungen / test conditions :HP 4274 A für/for L und/and Q Ferrit / ferrite 2SFBW 155°C F Werkstoffe & Zulassungen / material & approvals :G Eigenschaften / granted properties :Keramik/ ceramic Luftfeuchtigkeit / humidity:not exceed 100 °C under worst case operating conditionsUmgebungstemp. / ambient temperature: -40°C - + 85°C Basismaterial / base material:Draht / wire:Sockel / BaseDatum / date..............................................................................Unterschrift / signature Kontrolliert / approvedWürth Elektronik eiSos GmbH & Co. KGD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked .............................................................................................................................................................Änderung / modificationEndoberfläche / finishing electrode100% AuBetriebstemp. / operating temperature: -40°C - + 100°C POWER-CHOKE WE-PD 4HP 34401 A für/for I DC und/and R DCD Prüfgeräte / test equipment :Version 1Version 2description :MST09-02-09MST 04-10-11NameDatum / dateDATUM / DATE : 2009-02-09POWER-CHOKE WE-PD 4H Induktivitätskurve / Inductance curve :Freigabe erteilt / general release:Kunde / customer.............................................................................................................................................................Datum / dateUnterschrift / signature Würth Elektronik.............................................................................................................................................................Geprüft / checked Kontrolliert / approvedWürth Elektronik eiSos GmbH & Co. KGD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400http://www.we-online.deVersion 2Änderung / modificationVersion 1description :a 330,0± 0,5mmb 20,20± 0,2mm + 0,5- 1,0d 100,0± 0,2mm MST09-02-09MST 04-10-11NameDatum / datePOWER-CHOKE WE-PD 4.............................................................................................................................................................Version 1Version 2D-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked Kontrolliert / approvedÄnderung / modificationhttp://www.we-online.deFreigabe erteilt / general release:Kunde / customer.............................................................................................................................................................Datum / dateUnterschrift / signature Würth ElektronikWürth Elektronik eiSos GmbH & Co. KGmm 13,00c Rollenspezifikation / Reel specification:The force for tearing off cover tape is 10 to 130 grams in arrow directionThis electronic component has been designed and developed for usage in general electronic equipment. Before incorporating this component into any equipment where higher safety and reliability is especially required or if there is the possibility of direct damage or injury to human body, for example in the range of aerospace, aviation, nuclear control, submarine, transportation, (automotive control, train control, ship control),transportation signal, disaster prevention, medical, public information network etc, Würth Elektronik eiSos GmbH must be informed before the design-in stage. In addition, sufficient reliability evaluation checks for sa must be performed on every electronic component which is used in electrical circuits that require high safety and reliability functions or performance.分销商库存信息: WURTH-ELECTRONICS 74455115。

FEATURESRGY PACKAGE(TOP VIEW)2A119SDA3RESET18SCL4INT017INT5SD016SC36SC015SD37INT114INT38SD113SC29SC112SD2110AGND2011INT2VCCRESETINT0SD0SC0INT1INTSC3SD3INT3SC2RGW PACKAGE(TOP VIEW)SDASCLA1AVCCDGV,DW,OR PW PACKAGE(TOP VIEW)DESCRIPTION/ORDERING INFORMATIONSCPS147C–OCTOBER2005–REVISED OCTOBER2006•1-of-4Bidirectional Translating Switches•No Glitch on Power Up•I2C Bus and SMBus Compatible•Supports Hot Insertion•Four Active-Low Interrupt Inputs•Low Standby Current•Active-Low Interrupt Output•Operating Power-Supply Voltage Range of2.3V to5.5V•Active-Low Reset Input• 5.5-V Tolerant Inputs•Two Address Pins,Allowing up to FourDevices on the I2C Bus•0to400-kHz Clock Frequency•Channel Selection Via I2C Bus,In Any•Latch-Up Performance Exceeds100mA Per Combination JESD78•Power Up With All Switch Channels•ESD Protection Exceeds JESD22 Deselected–2000-V Human-Body Model(A114-A)•Low R ON Switches–200-V Machine Model(A115-A)•Allows Voltage-Level Translation Between–1000-V Charged-Device Model(C101)1.8-V,2.5-V,3.3-V,and5-V BusesThe PCA9545A is a quad bidirectional translating switch controlled via the I2C bus.The SCL/SDA upstream pair fans out to four downstream pairs,or channels.Any individual SCn/SDn channel or combination of channels can be selected,determined by the contents of the programmable control register.Four interrupt inputs(INT3–INT0), one for each of the downstream pairs,are provided.One interrupt(INT)output acts as an AND of the four interrupt inputs.An active-low reset(RESET)input allows the PCA9545A to recover from a situation in which one of the downstream I2C buses is stuck in a low state.Pulling RESET low resets the I2C state machine and causes all the channels to be deselected,as does the internal power-on reset function.The pass gates of the switches are constructed such that the V CC pin can be used to limit the maximum high voltage,which will be passed by the PCA9545A.This allows the use of different bus voltages on each pair,so that1.8-V,2.5-V,or3.3-V parts can communicate with5-V parts,without any additional protection.External pullup resistors pull the bus up to the desired voltage level for each channel.All I/O pins are5.5-V tolerant.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2005–2006,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DESCRIPTION/ORDERING INFORMATION (CONTINUED)GQN OR ZQN PACKAGE(TOP VIEW)1234A B C D ESCPS147C–OCTOBER 2005–REVISED OCTOBER 2006ORDERING INFORMATIONT APACKAGE (1)ORDERABLE PART NUMBER TOP-SIDE MARKING QFN –RGW Reel of 3000PCA9545ARGWR PD545A QFN –RGY Reel of 1000PCA9545ARGYR PD545A Tube of 25PCA9545ADW PCA9545A SOIC –DWReel of 2000PCA9545ADWR Reel of 250PCA9545ADWT PCA9545A PCA9545APW PD545ATube of 70PCA9545APWE4–40°C to 85°CPCA9545APWR PD545ATSSOP –PWReel of 2000PCA9545APWRE4PCA9545APWT PD545A Reel of 250PCA9545APWTE4Reel of 2000PCA9545ADGVR TVSOP –DGV PD545A Reel of 250PCA9545ADGVT VFBGA –GQNReel of 1000PCA9545AGQNR PD545A VFBGA –ZQN (Pb-free)Reel of 1000PCA9545AZQNRPD545A (1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at /sc/package.TERMINAL ASSIGNMENTS1234A A1A0V CC SDA B INT0INT RESET SCL C SC0SD0SD3SC3D SD1SC2INT1INT3EGNDSC1INT2SD22Submit Documentation FeedbackSCPS147C–OCTOBER2005–REVISED OCTOBER2006TERMINAL FUNCTIONSNO.NAME DESCRIPTIONDGV,DW,PW,GQN ANDRGWAND RGY ZQN119A2A0Address input0.Connect directly to V CC or ground.220A1A1Address input1.Connect directly to V CC or ground.Active-low reset input.Connect to V CC through a pullup 31B3RESETresistor,if not used.Active-low interrupt input0.Connect to V CC through a 42B1INT0pullup resistor.53C2SD0Serial data0.Connect to V CC through a pullup resistor.64C1SC0Serial clock0.Connect to V CC through a pullup resistor.Active-low interrupt input1.Connect to V CC through a 75D3INT1pullup resistor.86D1SD1Serial data1.Connect to V CC through a pullup resistor.97E2SC1Serial clock1.Connect to V CC through a pullup resistor.108E1GND GroundActive-low interrupt input2.Connect to V CC through a 119E3INT2pullup resistor.1210E4SD2Serial data2.Connect to V CC through a pullup resistor.1311D2SC2Serial clock2.Connect to V CC through a pullup resistor.Active-low interrupt input3.Connect to V CC through a 1412D4INT3pullup resistor.1513C3SD3Serial data3.Connect to V CC through a pullup resistor.1614C4SC3Serial clock3.Connect to V CC through a pullup resistor.Active-low interrupt output.Connect to V CC through a pullup 1715B2INTresistor.1816B4SCL Serial clock line.Connect to V CC through a pullup resistor.1917A4SDA Serial data line.Connect to V CC through a pullup resistor.2018A3V CC Supply power3Submit Documentation FeedbackSCPS147C–OCTOBER2005–REVISED OCTOBER2006BLOCK DIAGRAMPin numbers shown are for DGV, DW, PW, and RGY packages.4Submit Documentation FeedbackDevice AddressFixedHardware SelectableControl RegisterInterrupt Bits (Read Only)Channel-Selection Bits(Read/Write)Channel 0Channel 1Channel 2Channel 3INT0INT1INT2INT3Control Register DefinitionSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Following a start condition,the bus master must output the address of the slave it is accessing.The address of the PCA9545A is shown in Figure 1.To conserve power,no internal pullup resistors are incorporated on the hardware-selectable address they must be pulled high or low.Figure 1.PCA9545A AddressThe last bit of the slave address defines the operation to be performed.When set to a logic 1,a read is selected,while a logic 0selects a write operation.Following the successful acknowledgment of the slave address,the bus master sends a byte to the PCA9545A,which is stored in the control register (see Figure 2).If multiple bytes are received by the PCA9545A,it saves the last byte received.This register can be written and read via the I 2C bus.Figure 2.Control RegisterOne or several SCn/SDn downstream pairs,or channels,are selected by the contents of the control register (see Table 1).After the PCA9545A has been addressed,the control register is written.The four LSBs of the used to determine which channel or channels are to be selected.When a channel is selected,the channel becomes active after a stop condition has been placed on the I 2C bus.This ensures that all SCn/SDn lines are in a high state when the channel is made active,so that no false conditions are generated at the time of connection.A stop condition must occur always right after the acknowledge cycle.5Submit Documentation FeedbackInterrupt HandlingSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Table 1.Control Register Write (Channel Selection),Control Register Read (Channel Status)(1)INT3INT2INT1INT0D3B2B1B0COMMAND0Channel 0disabled X X X X X X X 1Channel 0enabled 0Channel 1disabled X X X X X X X 1Channel 1enabled 0Channel 2disabled X X X X X X X 1Channel 2enabled 0Channel 3disabled X X X X X X X 1Channel 3enabledNo channel selected,00Xpower-up/reset default state(1)Several channels can be enabled at the same time.For example,B3=0,B2=1,B1=1,B0=0means that channels 0and 3are disabled,and channels 1are 2and enabled.Care should be taken not to exceed the maximum bus capacity.The PCA9545A provides four interrupt inputs (one for each channel)and one open-drain interrupt output (see Table 2).When an interrupt is generated by any device,it is detected by the PCA9545A and the interrupt output low.The channel does not need to be active for detection of the interrupt.A bit also is set in the control register.Bits 4–7of the control register correspond to channels 0–3of the PCA9545A,respectively.Therefore,if an interrupt is generated by any device connected to channel 1,the state of the interrupt inputs is loaded into the control register when a read is accomplished.Likewise,an interrupt on any device connected to channel 0would cause bit 4of the control register to be set on the read.The master then can address the PCA9545A and read the contents of the control register to determine which channel contains the device generating the interrupt.The master then can reconfigure the PCA9545A to select this channel and locate the device generating the interrupt and clear it.It should be noted that more than one device can provide an interrupt on a channel,so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt.The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.If unused,interrupt input(s)must be connected to V CC .Table 2.Control Register Read (Interrupt)(1)INT3INT2INT1INT0D3B2B1B0COMMAND0No interrupt on channel 0X X X X X X X 1Interrupt on channel 00No interrupt on channel 1X X X X X X X 1Interrupt on channel 10No interrupt on channel 2X X X X X X X 1Interrupt on channel 20No interrupt on channel 3XXXXXXX1Interrupt on channel 3(1)Several interrupts can be active at the same time.For example,INT3=0,INT2=1,INT1=1,INT0=0means that there is no interrupt on channels 0and 3,and there is interrupt on channels 1and 2.6Submit Documentation FeedbackRESET InputPower-On ResetVoltage TranslationV CC (V)32.52V p a s s (V )I 2C InterfaceSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006The RESET input can be used to recover the PCA9545A from a bus-fault condition.The registers and the I 2C state machine within this device initialize to their default states if this signal is asserted low for a minimum of t WL .All channels also are deselected in this case.RESET must be connected to V CC through a pullup resistor.When power is applied to V CC ,an internal power-on reset holds the PCA9545A in a reset condition until V CC has reached V POR .At this point,the reset condition is released and the PCA9545A registers and I 2C state machine are initialized to their default states,all zeroes,causing all the channels to be deselected.Thereafter,V CC must be lowered below 0.2V to reset the device.The pass-gate transistors of the PCA9545A are constructed such that the V CC voltage can be used to limit the maximum voltage that is passed from one I 2C bus to another.Figure 3shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using in the electrical characteristics section of this data sheet).In order for the PCA9545A to act as a voltage translator,the V pass voltage must be equal to or lower than the lowest bus voltage.For example,if the main bus is running at 5V and the downstream buses are 3.3V and 2.7V,V pass must be equal to or below 2.7V to effectively clamp the downstream bus voltages.As shown in Figure 3,V pass (max)is at 2.7V when the PCA9545A supply voltage is 3.5V or lower,so the PCA9545A could be set to 3.3V.Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 13).Figure 3.V pass Voltage vs V CCThe I 2C bus is for two-way two-line communication between different ICs or modules.The two lines are a serial data line (SDA)and a serial clock line (SCL).Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device.Data transfer can be initiated only when the bus is not busy.One data bit is transferred during each clock pulse.The data on the SDA line must remain stable during the high period of the clock pulse,as changes in the data line at this time are interpreted as control signals (see Figure 4).7Submit Documentation FeedbackSDASCLData Line Stable;Data ValidChange of Data AllowedSDASCLStart ConditionS Stop ConditionP SCLSDA SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Figure 4.Bit TransferBoth data and clock lines remain high when the bus is not busy.A high-to-low transition of the data line while the clock is high is defined as the start condition (S).A low-to-high transition of the data line while the clock is high is defined as the stop condition (P)(see Figure 5).Figure 5.Definition of Start and Stop ConditionsA device generating a message is a transmitter;a device receiving a message is the receiver.The device that controls the message is the master,and the devices that are controlled by the master are the slaves (see Figure 6).Figure 6.System ConfigurationThe number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited.Each byte of eight bits is followed by one acknowlege (ACK)bit.The transmitter must release the SDA line before the receiver can send an ACK bit.When a slave receiver is addressed,it must generate an ACK after the reception of each byte.Also,a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter.The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7).Setup and hold times must be taken into account.8Submit Documentation FeedbackData Output by TransmitterSCL FromMasterStart ConditionData Output by ReceiverClock Pulse for ACKSDASDA Start Condition R/W ACK From Slave NACK From Master Stop ConditionSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Figure 7.Acknowledgment on the I 2C BusA master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK)after the last byte has been clocked out of the slave.This is done by the master receiver by holding the SDA line high.In this event,the transmitter must release the data line to enable the master to generate a stop condition.Data is transmitted to the PCA9545A control register using the write mode shown in Figure 8.Figure 8.Write Control RegisterData is read from the PCA9545A control register using the read mode shown in Figure 9.Figure 9.Read Control Register9Submit Documentation FeedbackAbsolute Maximum Ratings (1)Recommended Operating Conditions (1)SCPS147C–OCTOBER 2005–REVISED OCTOBER 2006over operating free-air temperature range (unless otherwise noted)MINMAXUNIT V CC Supply voltage range –0.57V V I Input voltage range (2)–0.57V I I Input current ±20mA I OOutput current±25mA Continuous current through V CC ±100mA Continuous current through GND±100mADGV package 92DW package58GQN/ZQN package 78θJAPackage thermal impedance (3)°C/W PW package 83RGW package TBD RGY package47P tot Total power dissipation 400mW T stg Storage temperature range–65150°C T A Operating free-air temperature range–4085°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3)The package thermal impedance is calculated in accordance with JESD 51-7.MINMAX UNIT V CC Supply voltage 2.3 5.5V SCL,SDA0.7×V CC 6V IH High-level input voltage V A1,A0,INT3–INT0,RESET 0.7×V CCV CC +0.5SCL,SDA–0.50.3×V CC V IL Low-level input voltage V A1,A0,INT3–INT0,RESET–0.50.3×V CCT A Operating free-air temperature–4085°C(1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.10Submit Documentation FeedbackElectrical CharacteristicsPCA9545A4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONSSCPS147C–OCTOBER2005–REVISED OCTOBER2006over recommended operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS V CC MIN TYP(1)MAX UNIT V POR Power-on reset voltage(2)No load,V I=V CC or GND V POR 1.6 2.1V5V 3.64.5V to5.5V 2.6 4.53.3V 1.9V pass Switch output voltage V SWin=V CC,I SWout=–100µA V3V to3.6V 1.6 2.82.5V 1.52.3V to2.7V 1.12I OH INT V O=V CC 2.3V to5.5V10µAV OL=0.4V37SCL,SDAI OL V OL=0.6V 2.3V to5.5V610mAINT V OL=0.4V3SCL,SDA±1SC3–SC0,SD3–SD0±1I I A1,A0V I=V CC or GND 2.3V to5.5V±1µAINT3–INT0±1RESET±15.5V312Operating mode f SCL=100kHz V I=V CC or GND,I O=0 3.6V3112.7V3105.5V0.31I CC Low inputs V I=GND,I O=0 3.6V0.11µA2.7V0.11Standby mode5.5V0.31High inputs V I=V CC,I O=0 3.6V0.112.7V0.11One INT3–INT0input at0.6V,815Other inputs at V CC or GNDINT3–INT0One INT3–INT0input at V CC–0.6V,815Other inputs at V CC or GNDSupply-current∆I CC 2.3V to5.5VµA change SCL or SDA input at0.6V,815Other inputs at V CC or GNDSCL,SDASCL or SDA input at V CC–0.6V,815Other inputs at V CC or GNDA1,A0 4.56C i INT3–INT0V I=V CC or GND 2.3V to5.5V 4.56pFRESET 4.5 5.5SCL,SDA1519C io(OFF)(3)V I=V CC or GND,Switch OFF 2.3V to5.5V pFSC3–SC0,SD3–SD0684.5V to5.5V4916V O=0.4V,I O=15mAR ON Switch on-state resistance3V to3.6V51120ΩV O=0.4V,I O=10mA 2.3V to2.7V71645(1)All typical values are at nominal supply voltage(2.5-V,3.3-V,or5-V V CC),T A=25°C.(2)The power-on reset circuit resets the I2C bus logic with V CC<V POR.V CC must be lowered to0.2V to reset the device.(3)C io(ON)depends on the device capacitance and load that is downstream from the device.元器件交易网I 2C Interface Timing RequirementsSwitching CharacteristicsPCA9545A4-CHANNEL I 2C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONSSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006over recommended operating free-air temperature range (unless otherwise noted)(see Figure 10)STANDARD MODEFAST MODE I 2C BUSI 2C BUSUNITMINMAX MIN MAX f scl I 2C clock frequency 01000400kHz t sch I 2C clock high time 40.6µs t scl I 2C clock low time 4.71.3µs t sp I 2C spike time5050ns t sds I 2C serial-data setup time 250100ns t sdh I 2C serial-data hold time 0(1)0(1)µs t icr I 2C input rise time 100020+0.1C b (2)300ns t icf I 2C input fall time 30020+0.1C b (2)300ns t ocf I 2C output fall time10-pF to 400-pF bus30020+0.1C b (2)300ns t buf I 2C bus free time between stop and start 4.7 1.3µs t sts I 2C start or repeated start condition setup 4.70.6µs t sth I 2C start or repeated start condition hold 40.6µs t sps I 2C stop condition setup 40.6µs SCL low to SDA output low t vdL(Data)Valid-data time (high to low)(3)11µs validSCL low to SDA output high t vdH(Data)Valid-data time (low to high)(3)0.60.6µs validACK signal from SCL low t vd(ack)Valid-data time of ACK condition 11µs to SDA output lowC b I 2C bus capacitive load400400pF (1)A device internally must provide a hold time of at least 300ns for the SDA signal (referred to as the V IH min of the SCL signal),in order to bridge the undefined region of the falling edge of SCL.(2)C b =total bus capacitance of one bus line in pF(3)Data taken using a 1-k Ωpullup resistor and 50-pF load (see Figure 10)over recommended operating free-air temperature range,C L ≤100pF (unless otherwise noted)(see Figure 12)FROM TO PARAMETERMINMAX UNIT (INPUT)(OUTPUT)R ON =20Ω,C L =15pF 0.3t pd (1)Propagation delay time SDA or SCLSDn or SCnns R ON =20Ω,C L =50pF1t iv Interrupt valid time (2)INTn INT 4µs t ir Interrupt reset delay time (2)INTnINT2µs(1)The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance,when driven by an ideal voltage source (zero output impedance).(2)Data taken using a 4.7-k Ωpullup resistor and 100-pF load (see Figure 12)元器件交易网Interrupt and Reset Timing RequirementsPCA9545A4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONSSCPS147C–OCTOBER2005–REVISED OCTOBER2006over recommended operating free-air temperature range(unless otherwise noted)(see Figure12)PARAMETER MIN MAX UNIT t PWRL Low-level pulse duration rejection of INTn inputs1µst PWRH High-level pulse duration rejection of INTn inputs0.5µst WL Pulse duration,RESET low6nst rst(1)RESET time(SDA clear)500nst REC(STA)Recovery time from RESET to start0ns(1)t rst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high,signaling a stop condition.It must be a minimum of t WL.元器件交易网PARAMETER MEASUREMENT INFORMATION= 1 k ΩL = 50 pF0.3 × V CCConditionConditionStart ConditionSCLSDAI 2C PORT LOAD CONFIGURATIONVOLTAGE WAVEFORMS0.7 × V CC0.3 × V CC0.7 × V CC PCA9545A4-CHANNEL I 2C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONSSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006A.C L includes probe and jig capacitance.B.All input pulses are supplied by generators having the following characteristics:PRR ≤10MHz,Z O =50Ω,t r /t f =30ns.C.The outputs are measured one at a time,with one transition per measurement.Figure 10.I 2C Interface Load Circuit,Byte Descriptions,and Voltage Waveforms元器件交易网SCLSDALEDxRESETStartACK or Read CycleL = 4.7 k ΩL = 100 pF INTERRUPT LOAD CONFIGURATIONV CCINTn(input)VOLTAGE WAVEFORMS (t iv )VOLTAGE WAVEFORMS (t ir )INT (output)0.5 × V CCINTn (input)INT (output)× V CC0.5 × V CCPCA9545A4-CHANNEL I 2C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONSSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006PARAMETER MEASUREMENT INFORMATION (continued)Figure 11.Reset TimingA.C L includes probe and jig capacitance.B.All input pulses are supplied by generators having the following characteristics:PRR ≤10MHz,Z O =50Ω,t r /t f =30ns.Figure 12.Interrupt Load Circuit and Voltage Waveforms元器件交易网APPLICATION INFORMATIONChannel 0Channel 1Channel 2Channel 3PCA9545A4-CHANNEL I 2C AND SMBus SWITCHWITH INTERRUPT LOGIC AND RESET FUNCTIONSSCPS147C–OCTOBER 2005–REVISED OCTOBER 2006Figure 13shows an application in which the PCA9545A can be used.A.If the device generating the interrupt has an open-drain output structure or can be 3-stated,a pullup resistor is required.If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated,a pullup resistor is not required.The interrupt inputs should not be left floating.B.Pin numbers shown are for DGV,DW,PW,and RGY packages.Figure 13.Typical Application元器件交易网PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)PCA9545ADGVR ACTIVE TVSOP DGV 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ADGVRG4ACTIVE TVSOP DGV202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ADGVT PREVIEW TVSOP DGV 20250TBD Call TI Call TIPCA9545ADW ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ADWG4ACTIVE SOIC DW 2025Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ADWR ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ADWRG4ACTIVE SOIC DW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ADWT PREVIEW SOIC DW 20250TBD Call TI Call TIPCA9545AGQNRNRNDBGA MI CROSTA R JUNI OR GQN201000TBDSNPBLevel-1-240C-UNLIMPCA9545APW ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWE4ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWG4ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWR ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWRE4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWRG4ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWT ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWTE4ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545APWTG4ACTIVE TSSOP PW 20250Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCA9545ARGWR PREVIEW QFN RGW 203000TBDCall TI Call TIPCA9545ARGYR ACTIVE QFN RGY 201000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR PCA9545ARGYRG4ACTIVE QFN RGY 201000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR PCA9545AZQNRACTIVEBGA MI CROSTA R JUNI ORZQN201000Green (RoHS &no Sb/Br)SNAGCULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.。

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EPT069906 第 11 版 2021 年 6 月
溅洒与处置
警告：
易燃材料。火灾风险。
不得让墨水干燥或积累干燥墨水。一些干燥墨水极为易燃。应立刻清理所有溅洒墨 水。
考虑到人员安全，溅洒出的墨水必须尽快用合适溶剂材料清理。必须小心防止溅洒或清理后的残留 物进入下水道或污水系统。
墨水和相关液体可以导电，因此清理溅洒时必须关闭控制器电源。
习惯或动作。 • 必须避免接触眼睛。如果存在溅洒或起雾风险，必须始终佩戴合适的眼睛防护设备。如果墨水
进入眼睛，首先应用盐水(如果没有盐水，则用清水)微净化受影响的眼睛 15 分钟，小心不要让 水流入未受影响的眼睛。必须立刻就医。 • 大多数墨水含有可伤害皮肤的溶剂。必须始终采取良好工作做法，执行风险评估。提供安全数 据表，给出个人防护设备建议。大多数手套提供有限短时接触防护，必须定期以及在任何溅洒 后更换。 • 许多墨水含有容易蒸发并被吸入的的材料。必须提供良好通风。 • 任何用过的清洁材料，如抹布、纸巾，是潜在火灾危险。使用后必须收集进行安全处置。接触 墨水后，必须在最近的清洗设施尽快清洗所有可能的痕迹。
警告：
可导致死亡或受伤的危险。
注意：
可导致设备损坏或环境破坏的危险。
注释：其他重要信息。
符号
本产品手册通过以下符号强调符号下方程序使用的具体警告和注意事项。 警告或注意，阅读并遵守警告或注意文本，避免人员受伤、设备损坏或环境破坏。

7 PIN SIP Package
3rd angle projection
19.65 7.05
14
11
9 8
19.90 10.20
RC-0512D RECOM ****
RD-0505D RECOM ****
0.51 typ.
RD-0505D RECOM ****
10.00
7.62 4.10 0.51 typ.
EC 54
August 2002

元器件交易网
ECONOLINE - DC/DC-Converter
RD and RC Series, 2 Watt, SIP7/DIP14 (Dual Output) Features
● ● ●
Dual Output from a Single Input Rail Power Sharing on Output 1kVDC & 2kVDC Isolation
● ● ●
Custom Solutions Available
UL94V-0 Package Material Efficiee
Part Number SIP7 RD-XX3.3D RD-XX05D RD-XX09D RD-XX12D RD-XX15D RD-XX24D Part Number DIP14 RC-XX05D RC-XX05D RC-XX09D RC-XX12D RC-XX15D RC-XX05D 2kV (H) (H) (H) (H) (H) (H) Input Voltage (VDC) 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 5, 9, 12, 15, 24 Output Voltage (VDC) ±3.3 ±5 ±9 ±12 ±15 ±24 Output Current (mA) ±303 ±200 ±111 ±84 ±66 ±42 Efficiency (%) 70 70-75 75-81 78-83 80-84 80-85