An Innovative Methodology for the Design Automation of Low Power Libraries

An Innovative Methodology for the Design Automation of

Low Power Libraries

Nicola Dragone, Carlo Guardiani, Roberto Zafalon and Pascal Meier+

STMicroelectronics, Central R&D 20041 Agrate - Italy+Carnegie Mellon University, Pittsburgh, Pennsylvania.

Abstract-Anewmethodologyforthedesignoflow-powerstandardcelllibrariesispre-

sented.Theproposedapproachaddressespowerconsumptionatvariousstepsinthe

designflow,applyingnewdesignautomationalgorithmsandincorporatinginnovative

celldesigns.CADtechniquesareusedtospeeddevelopmentofthelibrary,allowingfor

quickanalysisofpoweranddelaycharacteristics,withsubsequentfeedbackforredesign.

Theeffectivenessoftheproposedflowisdemonstratedonseveralbenchmarkcircuits

implementedina0.35µmCMOS,1.8voltstandardcelllibrarydesignedusingthismeth-

odology.

I - Introduction

PowerconsumptionisbecominganincreasinglyimportantfactorinICdesign.While

substantialpowersavingscanbeachievedbyalgorithmicandarchitecturaloptimization,

thecelllibraryfundamentallyestablishesthepowercharacteristicsofthefinaldesign.

Celllibraryoptimizationhastraditionallybeentargetedatminimizingareawhilemeet-

ing delay targets, but power has become a primary design concern.

Webelievethattheneedtoprovideseverallibraries,addressingdifferentkindofapplica-

tions[1],coupledwiththehugedevelopmenttimerequiredforeachofthem,should

induceICmakerstodevelopanefficientautomateddesignflow.Suchaflowcouldpro-

videacompetitiveadvantageby1)reducinglibrarydesigntime,2)achievingoptimized

librariestomeetperformancegoals.Thedesignofacelllibraryaffectspowerdissipation

atseveralstages:atthesystemlevel,gatelevelaswellasthephysicaldesignlevel.The

gatelevelisconcernedwithpowerdissipationofeachindividualcell.Inthiscontext,the

cellisdesignedtomeettimingandareaconstraintswhileminimizinginternalenergy

dissipation.Atthesystemlevelonehastoconsiderhowtheinstantiatedcellsinteract

eachotherandhowindividualmodificationsaffectthetotalpowerconsumptionofthe

design.Thephysicaldesignlevelreliestothecelllayoutstageaswellastheinteraction

withsystemlevelphysicalattributes.Furthermore,wehavetoconsiderthatacelllibrary

providesthosebasiclogicfunctionsextensivelyusedbyautomaticsynthesistools[2].

Aneffectivelowpowerlibrarydesignmethodologymustbeabletogenerateachoiceof

cellssuitableforasuccessfuldesignsynthesismappingontothegiventechnology.The

+P. Meier is funded by ARPA contract DAAL 01-95-K-3527 and NSF contract MIP-9408457.

setoflibraryfunctionsanddrivestrengthscanconsiderablyimpactthequalityofthe

finalimplementation[3],bothinspeedandpowerdissipation.Atthesametime,thelevel

ofroutingporosityandthephysicalstructureofthecellsaffectssystemlevelcharacteris-

ticssuchasareaandlengthofwires,whichalsoimpactpowerdissipation.Thispaper

presentsalow-powercelllibrarydesignflow,spanningalldesignphasesfromthelogic

designdowntolayoutimplementation,enhancingexistingtechniqueswithoriginalCAD

solutions.Thelibraryoptimizationprocessisaddressedtoachievemaximumbenefitat

macro-blocklevelinsteadofjuststackingthefocusatthegatelevel.Inthissense,while

asingle,stand-alonecellmightshowasub-optimalbehaviorintermsofpowerconsump-

tion, this allows a larger power saving of the whole circuit [4].

Theremainderofthepaperisorganizedasfollows.SectionIIdescribesthefulldesign

flowandpresentssomeCADsolutionstotheproblemoflibrarydevelopment.SectionIII

discussesthecircuittechniqueswhichreducepowerconsumption.Particularemphasisis

giventoflip-flopinternalarchitecture,usuallyaverycriticalcellinthelibrary,andopti-

mumtransistorsizing.SectionIVdiscussesphysicalimplementationissuesandauto-

maticlayout.SectionVshowsthesynthesisresultsobtainedbyusingacompletelibrary

developed with this methodology. Final conclusions are presented in Section VI.

II - Low Power Library Design Flow

Thedesignofastandardcellcanbedividedintothree

steps:cellarchitecturedesign,transistorsizingand

physicaldesign.Theobjectiveofagoodmethodology

istooptimizethedesigngoalsandtominimizereloop-

ingthroughthedesignflow.Thelibrarydesignflow

that we used is shown in figure 1.

Thedesignprocessstartswiththedefinitionofthecell

functionalityandarchitecture(i.etransistortopology).

BylookingtoasignificativenumberofASICsinter-

nallydevelopedforseveraldigitalapplications,weselectedthecore’sfunctionsmostfre-

quentlyusedbytheautomaticsynthesizerandidentifiedtheirfanoutstatistics.Theright

choiceofthecellscanleadtoasignificantimprovementofthefinalresults,asreportedin

[6],wheretheimplementationofalargeWallaceTreemultiplierwithbootrecodinghas

beenenhancedofabout25%inspeed,bysimplyretargetingthesynthesizerontoabetter

library,includingalargervarietyoftwobitadders.Clearlynoteachkindofcellcontrib-

utesthesametothetotalpowerconsumption.Forexample,thecellsbelongingtothe