Mamta-Via

Altera Corporation 1AN-344-2.0

PreliminaryApplication NoteASI DemonstrationIntroductionA digital video broadcast asynchronous serial interface (DVB-ASI) is a serial data transmission protocol that transports MPEG-2 packets over copper-based cables or optical networks. DVB-ASI is used as a serial link between equipment in broadcast facilities.The Altera® ASI demonstration demonstrates how to use Cyclone™ devices to transmit and receive packets over an ASI. The demonstration is a two-receiver and transmitter demonstration with loopback and includes a transport stream (TS) generator and TS packet checker.The ASI demonstration uses the Altera® ASI MegaCore® function and the Cyclone video demonstration board.fFor information on the Altera Cyclone Video Demonstration Board, refer to the Cyclone Video Demonstration Board Data Sheet.fFor information on the ASI MegaCore function, refer to the ASI MegaCore Function User Guide.Functional DescriptionFigure1 shows the ASI demonstration block diagram.April 2006, version 2.02 Altera CorporationASI DemonstrationFunctional DescriptionFigure1.Block DiagramNote to Figure1:(1)The LVDS standard copes with a 270-Mbps bit rate and enables better noise integrity than LVTTL/LVCMOS.The design consists of the following elements:■Cyclone low voltage differential signalling (LVDS) inputs and outputs (I/Os) for the receiver and transmitter■ASI receiver■ASI transmitter■ASI buffer■TS generator■TS checker■Two PLLs for frequency multiplication—one for the transmitter, one for the receiver fFor more information on the ASI transmitter and receiver, refer to the ASI MegaCore Function User Guide.The two reference clocks can be either asynchronous to each other or the two PLLs can be driven from the same clock source.ASITransmitterasi_tx1(LVDS)External LoopbackWith Coaxial Cableasi_rx2(LVDS)asi_tx0(LVDS)88ASIReceiverasi_rx1(LVDS)8ASIReceiverasi_rx0(LVDS)8ASIReceiverrx_refclkReceiverPLLtx_refclkTransmitterPLLTS GeneratorTSChecker8ASIBuffer8ASIBufferAltera Corporation 3Getting StartedASI DemonstrationFor the TS check mode, the transmit and receive paths are independent— the design can transmit and receive at the same time. For loopback, the transmit path is coupled to the receive path through a rate matching first-in first-out (FIFO) buffer.The design uses two PLLs. For the receiver logic, the first PLL generates a 5× oversample scheme 337.5-MHz clock (27 MHz × 50/4) and a 337.5-MHz clock phase shifted by 90°. The second PLL generates a transmit serial clock at 270 MHz.ASI BufferThe ASI buffer rate matches between the incoming byte rate and transmit or system clock rate, because of phase and frequency difference between the two rates. The frequency difference can be up to +/- 100 ppm.TS GeneratorThe TS generator generates null TS packets of either 204 or 188 bytes. These packets can be spaced with idle cycles. In this demonstration design, this idle time can be switched between 10 and 1,023 cycles. The packets start with a NULL 47 1F FF 10 header followed by a byte indicating the channel ID, then 4 bytes for the packet count. The rest of packet is filled with values from an incrementing counter. TS CheckerThe TS checker checks for the correct reception of ASI packets. The packets must be of the same format as those generated by the TS generator. This block checks that the packets are of the correct length and that the header, channel ID, packet counts, and payload are correct.Getting StartedThis section involves the following steps:1.System Requirements2.Install the pile the e the DemonstrationSystem RequirementsThe design requires the following hardware and software:4 Altera CorporationASI DemonstrationGetting Started■Cyclone video demonstration board■ASI MegaCore function v1.0.0■Quartus II software version 6.0fTo obtain a Cyclone video demonstration board, contact your local Altera representative.Install the DesignFigure2 shows the directory structure of the demonstration, which is in the example directory of the ASI MegaCore function.Figure2.Directory StructureCompile the DesignQuartus II project files are provided for the demonstration mapped to the Cyclone video demonstration board. The .qsf file defines the pinout and other compilation directives for the design. You must compile the design to produce the device images required for the demonstration.To compile the demonstration design, open the relevant project in the Quartus II software and choose Start Compilation (Tools menu).Use the DemonstrationThe ASI demonstration exercises both the ASI receiver and transmitter. The loopback part of the design uses two receive ports—one with a cable equalizer (BNC J1) and one without (BNC J2). Both ASI inputs are received and decoded. quartus Contains Quartus II projects for the designs. doc Contains the documentation. mc_buildContains the ASI MegaCore function files for the demonstration.asi_bufferContains the ASI buffer files.example sourceContains the source files.topContains the demonstration top-level design files.

VIAVI Solutions

Our network equipment manufacturing (NEM) customers tell us that they are building higher port density into their network elements to meet the need for ever- increasing bandwidth demand, and, therefore, need more test equipment ports at a lower cost. The revolutionary VIAVI Solutions ONT Multiport Test Module (MTM) design provides unparalleled value with support for multiple Layers 1 to 3 protocols at 155 Mbps to 11.3 Gbps rate port rates. These unique benefits reduce CapEx and OpEx because our customers no longer have to purchase, manage, and maintain multiple tests sets to perform these functions.The MTM supports multiport testing with four SFP/SFP+/XFP port banks. Each port bank supports one test, enabling up to four concurrent test sessions. This flexibility enables each user to generate/analyze traffic over a broad range of protocols and line rates.The MTM also provides unparalleled value with comprehensive protocol coverage that includes the optical transport network (OTN), Gigabit Ethernet (GE)/10GE local area network (LAN), Generic Framing Key Benefits yAll-in-one solution tests Layers 1 to 3 at 155 Mbps to 11.3 Gbps rates yReduces CapEx with high port density and a comprehensive feature set yMaximizes efficiency and minimizes test time with multiuser, multiport capability yMaximizes value with broad Ethernet, OTN, GFP, Fibre Channel, CPRI and SONET/SDH protocol coverage yComplex traffic generation, deep analysis, and advanced error/alarm insertion ensures optimal system performance yFor OTN, it supports both Enhanced (ITU-T G.975 I.4 and I.7) and Generic (ITU-T G.709) FEC for complete FEC test coverage yUnframed 600 Mbps and 1.2, 2.4, 3, 4.9, 6.1, 9.8, and 10 Gbps CPRI rates, infiniband 2.5, 5, and 10 Gbps rates and 1.485, 1.484, 2.970, and 2.967 Gbps SDI rates Applications yValidate Carrier Ethernet yPerform system verification testing yGenerate clients to fully load/analyze 40/100 G systems yConduct production testing on network elements yLoad 155 Mbps − 11.3 Gbps trafficCompliance yCE Mark yOTN ITU-T G.709 yLAN/WAN IEEE 802.3 ySONET Telcordia GR-253-Core ySDH ITU-T G.707 ySafety CSA Certificate of ComplianceData SheetVIAVIONT Multiport Test Module (MTM) ONT-601 MTM stand-alone configuration and MTM plug-in module for ONT-600 and ONT-800 CapabilitiesOptical InterfacesThe optical interfaces are based on XFP, tunable XFP, and SFP/SFP+ pluggable optics. I2C debug control of pluggable optics.Unframed TestingAll available rates are offered with unframed pattern and BERT capabilities. yUnframed BERT at 28 different rates: 155.52, 614.40, and 622.08 Mbps and 1.063, 1.229, 1.25, 1.484, 1.485, 2.125, 2.488, 2.5, 2.666, 2.967, 2.970, 3.072, 4.25, 4.915, 5.0, 6.144, 6.250, 8.5, 9.83, 9.953, 10.0, 10.138, 10.313, 10.519, 10.709, 11.049, 11.095, 11.270, and 11.318 Gbps yUnframed patterns: PRBS31, PRBS23, PRBS15, PRBS11, PRBS7 and inverted, PRBS31-IEEE, DW 32 bits, square wave (Tx only), repeating ones/zeros editable 4 to 11 bitsOTN OTU2/OTU1 TestingOTN OTU2/OTU1 testing supports OTU2/OTU1 applications including overclocked OTU2 rates for signal generation and analysis with deep signal manipulation (alarm, error, overhead), generic FEC (GFEC) and enhanced FEC (EFEC) generation and analysis. Also supports comprehensive ODU multiplexing (ODU0, ODUflex, ODU1, and ODU2) with multistage multiplexing as well as ODU multichannel capability. yStandard and overclocked OTU2 rates yGFEC and EFEC I.4 and I.7 yBulk and fully structured clients; LAN, WAN, and SDH/SONET yODU multichannel with parallel generation and analysis of ODU0/1/flex mixed mappings ySupports all TCM layers yOverhead- and payload-based transfer delay yService disruption tests with high-level detail yClient offset stuffing control at each layer yODU0 with GE and SDH/SONET clients yCapture and analyze HDLC frames on GCC bytesProcedure (GFP), Fibre Channel (FC), CPRI (Common Public Radio Interface) and synchronous optical/synchronous digital hierarchy (SONET/SDH Single and Multi Channel) technologies. It enables generating, analyzing, and selectively erroring protocol-based and unframed test traffic. For OTN testing, users can configure OTN framed clients as LAN, GFP, SONET/SDH, ODU0, ODUflex, or bulk payloads. Full client signal features are maintained when wrapped in OTN. Standard connectivity options supported while connected to a device under test are Terminal, Intrusive Through, and Nonintrusive Through modes.The MTM is available as a stand-alone configuration or as a hot-swappable plug-in module. The stand-alone configuration is a compact, stackable 1-RU form factor known as the ONT-601 MTM-B. The plug-in MTM is for use in the ONT-800 and ONT-600 chassis series and enables scalability of up to 48 SFP/SFP+/XFP test ports within an ONT-812 chassis.

samesSA541, SA54L1

FEATURESsSelectable Loop-Disconnect (Pulse)or DTMF (Tone) dialling modess32 Digit Last Number Redial (LNR)sSelectable Interdigit Pause (IDP)500ms or 800mssOperates with inexpensive single con-tact keypadsOn-chip Darlington transistor pair forDTMF tone filteringsLow power CMOS technology enablesdirect operation from Telephone linesOptional use of external capacitor foroscillatorPULSE/DTMF SWITCHABLE DIALLERS

sKeypad switchable Loop-Disconnect toDTMF during a callsSelectable Break:Make Ratios 2:1 or3:2sUses inexpensive 560KHz ceramicresonatorsEarth Loop Recall and Timed BreakRecall (Timed Flash)sLow on-hook Supply Current optionsSA5413 - 5µA @ 2.5VSA5416 - 1µA @ 2.5VSA5419 - 1µA @ 3.0VsCall, barring/locking feature available

on the SA54L1元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网SA541sames元器件交易网South African Micro-Electronic Systems (Pty) LtdP O Box 15888,21 Eland Street,Lynn East,Koedoespoort Industrial Area,0039Pretoria,Republic of South Africa,Republic of South Africa

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1MGate5119系列

1埠DNP3/IEC101/IEC104/Modbus轉IEC61850閘道器

特色與優點

•支援IEC61850MMS伺服器

•支援DNP3串列/TCP主控裝置

•支援IEC60870-5-101主控裝置(平衡/非平衡)

•支援IEC60870-5-104用戶端

•支援ModbusRTU/ASCII/TCP主控裝置/用戶端

•嵌入式流量監控/診斷資訊，便於故障排除

•輕鬆佈線的內建乙太網路串接

•-40°C至75°C操作溫度範圍

•串列內建埠2kV隔離保護

•支援IEC61850MMS和DNP3TCP通訊協定加密

•基於IEC62443/NERCCIP的安全功能

•符合IEC61850-3和IEEE1613

•內建SCL檔案產生器，便於配置認證

簡介

MGate5119是工業乙太網路閘道器，具有2個乙太網路連接埠和1個RS-232/422/485串列埠。若要將Modbus、IEC60870-5-101和IEC60870-5-104裝置與IEC61850MMS網路相整合，請將MGate5119做為Modbus主控裝置/用戶端、IEC60870-5-101/104主控裝置和DNP3串列/TCP主控裝置，藉以收集資料並與IEC61850MMS系統交換資料。

透過SCL產生器輕鬆配置MGate5119做為IEC61850MMS伺服器，通常需要匯入由第3方工具產生的SCL檔案。這可能很耗時，而且會增加成本。為了克服這個難處，MGate5119內建SCL產生器，可以透過Web主控台輕鬆產生SCL檔案並幾乎立即可用，因此節省配置時間和成本。

透過流量監視器輕鬆進行故障排除MGate5119系列閘道器支援ModbusRTU/ASCII/TCP、IEC60870-5-101、IEC60870-5-104和IEC61850MMS通訊協定流量監控，故障排除更容易，特別在安裝階段。值得一提的是，可以在常用的故障排除工具Wireshark中查看流量日誌。使用此項功能可以輕鬆分析流量以確定問題的根本原因。