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Integrating BIST techniques for on-line SoC testing

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Integrating BIST techniques for on-line SoC testing A. Manzone Centro Ricerche Fiat Torino, Italy alberto.manzone@crf.it

P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda Politecnico di Torino Torino, Italy {paolo.bernardi, michelangelo.grosso, maurizio.rebaudengo,edgar.sanchez, matteo.sonzareorda}@polito.it

Abstract* Today’s complex system-on-chip integrated circuits include a wide variety of functional IPs whose correct manufacturing must be guaranteed by IC producers. Infrastructure IPs are increasingly often inserted to achieve this purpose; such blocks, explicitly designed for test, are coupled with functional IPs both to obtain yield improvement during the manufacturing process and to perform volume production test. In some fields (e.g., the automotive one) there is a strong need for flexible and reusable test architectures able to guarantee effective and low-cost solutions for mission-mode fault detection capabilities within complex SoCs. In this paper, we propose to reuse structures inserted to support the manufacturing test to perform non-concurrent on-line test of SoCs. The feasibility of this approach and its costs have been evaluated on a real case of study including processor, memory and user defined logic cores.

1. Introduction Today, the possibility to include several functional modules into the same piece of silicon is a great opportunity for designers. Resorting to small area and achieving low power constraints, even more complex systems-on-chips (SoCs) are manufactured by semiconductor industries for a widespread application scenario. However, the susceptibility of these highly integrated components to static and dynamic faults is dramatically rising due to the continuous reduction of transistor size and the growing number of metalization levels in multilayer circuits, in addition to the very high frequency requirements. Testing SoCs is a well-known problem that involves both the accessibility to each single core and the test application frequency. The effort of test engineers usually concentrates on the definition of test

* Contact author: Paolo Bernardi, Dip.

Automatica e Informatica, Politecnico di Torino, C.so Duca degli Abruzzi 24, 10129, Torino, Italy, Tel: +390115647048, Fax: +390115647099, Email: paolo.bernardi@polito.it

techniques and structures; this allows the test of components, even deeply embedded, resorting to special dedicated circuitries that autonomously apply stimuli at the nominal speed of the device under test. A special family of IP blocks, called Infrastructure IP blocks [1], has been recently proposed to minimize the impact of test over SoC performance. These blocks, included in the SoC in addition to Functional IP cores (F-IPs), aim to ensure the manufacturability of the SOC and to achieve adequate levels of yield and reliability [2]. On-chip Infrastructure IPs are increasingly becoming a viable solution for many IC design issues. Yield and test concerns for very deep-submicron semiconductor technologies have forced chip designers to incorporate Infrastructure IPs into their designs to help with silicon debug, to improve test quality, and to increase manufacturing yield. Examples of application of such Infrastructure IPs include Built-In Self-Test (BIST) for logic and memories, Built-In Self-Repair (BISR) for embedded memories [3], process monitoring [4], and embedded timing [5] analysis circuitry. Even more, Infrastructure IPs can be easily reused in different designs. This reuse minimizes the time IC designers spend manually designing strategies; moreover, design automation has facilitated the use of I-IPs, which significantly reduce the efforts required for a project. Infrastructure IPs are also used to improve in-field reliability that couples with higher performance demand for digital applications. Robustness IPs aim at this scope as they address information integrity, system availability and security. In [6], [7] and [8] solutions implementing detection, analysis and correction of soft errors are given by means of information encoding, behaviour prediction and redundancy. In environments where errors could be very damaging, resulting in system crashes or critical information corruption, the employment of such structures is mandatory. On the contrary, other systems may not require to be continuously monitored and their correct behaviour may be checked only at particular functional phases such as the startup, the shut down or during long idle periods. This is the case of the automotive field: the complexity reached by the electronic components used in the vehicle and the criticality of such environments mandate to guarantee the system integrity. On the other

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在Zynq AP SoC设计中使用HLS IP(二)

在Zynq AP SoC设计中使用HLS IP(二)

在Zynq AP SoC设计中使用HLS IP（二）对于硬件加速模块来说，这些硬件加速模块会消耗源于CPU存储器的数据，并且以streaming方式产生数据。

本文使用Vivado HLS和xfft IP模块（在IP Integrator使用HLS IP那节用过）。

这些模块是连接到HP0的AXI4从端口，使得zynq7处理系统的数据通过AXI DMA IP核。

硬件加速模块是免费的运行，并不需要驱动，只要数据被CPU推送（通常简称为处理系统或PS）。

这里还要强调软件要求避免缓存一致性问题。

在Zynq CPU和HLS加速模块之间Streaming DataStep 1: 产生HLS IP这里会产生两个Vivado HLS文件，即fe_vhls_prj和be_vhls_prj，它们都包含HLS IP。

Step 2: 创建Vivado Project打开Vivado，选择Create New Project，下一步在Project location里选择lab2文件夹，并将project name命名为project_1，然后选择RTL Project和do not specify sources at this time，在Board选择ZYNQ-7 ZC702 Evaluation Board，最后点击Finish。

Step 3: 给IP库里添加HLS IP在Flow Navigator窗口点击IP Catalog，然后选择IP Settings，在IP Settings对话框选中Add Repository，在lab2下Create New Folder，并命名为vivado_ip_repo，然后依次添加lab2/hls_designs/fe_vhls_prj/IPXACTExport/impl/ip和lab2/hls_designs/be_vhls_prj/IPXACTExport/impl/ip，现在在HLS IP中有Hls_real2xfft和 Hls_xfft2real这两个IP。

1HBM静电放电测试系统之二次电性过应力事件的形成与抑制

1HBM静电放电测试系统之二次电性过应力事件的形成与抑制

HBM靜電放電測試系統之二次電性過應力事件的形成與抑制作者Tom Meuse (1), Larry Ting (2), Joe Schichl (2), Robert Barrett (1), David Bennett (1), Roger Cline (2), Charvaka Duvvury (2), Michael Hopkins (1), Hans Kunz (2), JohnLeiserson (1), Robert Steinhoff (2)(1) Thermo Electron Corporation (2) Texas Instruments Inc.譯者何正江訊程實業股份有限公司目錄1.背景介紹2. 元件失效的描述和測試系統間的相互作用3. 異常尾波(trailing pulse)的發現4. 異常尾波(trailing pulse)形成的機制5. 測試系統的修改以抑制異常尾波(trailing pulse)6. 對於HBM測試標準改進之建議以及將來之挑戰7.結論HBM靜電放電測試系統之二次電性過應力事件的形成與抑制前言以往在人體帶電模型(Human Body Model，HBM)靜電放電測試系統中，未被偵測到的異常尾波(trailing pulse)，最近已被證實對於較先進技術下所製造出來的半導體產品，會在其閘極氧化層(gate oxide)部位產生預期之外的破壞。

此第二脈衝是由於放電繼電器以及充電電路寄生特性所共同引起的電性過應力(Electrical Over-Stress，EOS)自然現象。

本文件主要在探討此一重要現象以及建立測試系統如何來抑制異常尾波的機制。

1. 背景介紹自從1979年美國軍方首度制定人體帶電模型(Human Body Model，HBM)耐靜電測試標準MIL-STD-883 Method 3015以來許多商品化的HBM測試系統相繼在半導體工業界被採用。

一种锂离子电池SOH在线检测方法

一种锂离子电池SOH在线检测方法

2023年 / 第9期 物联网技术30 引 言锂离子电池状态直接影响电动汽车的性能提升[1]。

锂离子电池健康状态（State of Health, SOH ）的精确检测对提升电动汽车BMS （Battery Management System ）水平具有重要的意义[2-3]。

目前SOH 检测的方法主要有实验估计法、基于模型的方法和基于数据驱动的方法。

实验估计法是通过电池的容量、电阻等测试实验来估计SOH 。

基于模型的方法多采用卡尔曼滤波、自适应滤波、粒子滤波（Particle Filter, PF ）等算法进行SOH 估计。

基于数据驱动的方法主要采用神经网络方法进行SOH 估计。

由于锂离子电池是一个复杂的时变非线性系统，而粒子滤波更适合处理非线性、非高斯系统，但粒子滤波方法存在粒子退化容易陷入局部最优而导致估计精度降低的问题。

针对这些问题，本文采用莱维飞行策略指导蚁狮更新位置，解决蚁狮算法容易陷入局部最优和算法收敛慢的问题，通过改进蚁狮算法优化粒子分布。

综合应用蚁狮算法和粒子滤波算法进行锂离子电池SOH 估计，通过NASA （National Aeronautics and Space Administration ）数据集实验和实测实验，验证所提出方法的检测精度。

1 SOH 估计模型及参数辨识1.1 SOH 估计模型为了准确估计电池的SOH ，必须建立一个准确的电池容量随充放电周期衰减的退化模型。

文献[4]的研究表明，双指数退化模型能够较好地描述电池退化过程。

双指数退化模 型为：SOH k a b k c d k =××+××exp()exp() （1）式中：a 、b 、c 、d 为模型参数；k 为充放电次数。

将模型离散化并以X k =[a k , b k , c k , d k ]T 作为状态量。

a a wb b wc c wd d wk k a k k k b k k k c k kk d k =+=+=+=+−−−−−−−−11111111,,,,（2）式中，w a 、w b 、w c 、w d 分别为均值等于0的高斯噪声。

Synopsys TestMAX SMS数据手册说明书

Synopsys TestMAX SMS数据手册说明书

DATASHEET Overview TestMAX SMS is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across foundry, process node and memory IP vendors. Its highly automated design implementation and diagnostic flow enables system-on-chip (SoC) designers to achieve quick design closure and significantly improve time-to-market and time-to-yield in volume production.SMS Silicon Browser SMS Yield Accelerator Figure 1: TestMAX SMS Solution Key Benefits • Full RTL integration flow with TestMAX Manager • Hierarchical architecture and automated SoC integration and verification • High-quality test to provide full memory defect coverage with minimum test time • High yield with efficient on-chip repair across multiple operating corners • Superior diagnostics with physical failed bitmaps and XY coordinate identification to quickly determine root cause of failuresA comprehensive,integrated test,repair and diagnosissolution for embeddedmemoriesTestMAX SMS Complete Memory Test, Repair and Diagnostics SolutionKey Features• TestMAX SMS provides all the key elements for embedded memory test and repair utilizing the following components:–SMS wrapper–SMS processor–SMS server and sub-server–MMB Processor for high performance cores• Test algorithm programmability• Tester patterns and diagnostics• Silicon bring-up and characterizationHigh-Performance Core SupportTestMAX SMS allows at-speed test and repair of high-performance processor cores by using a preconfigured test bus, which provides access to the memories inside the core in test mode. TestMAX SMS uses this shared multi-memory bus (MMB) to test memories and add memory test and repair logic outside the IP core to avoid any impact on processor core performance.Test Algorithm ProgrammabilityTestMAX SMS provides full test algorithm programmability. The SMS processor includes a BIST module to execute test algorithms. The default test algorithms in the BIST module can be replaced with new algorithms in the RTL or in silicon, and the user can program either their own custom algorithms or select from the comprehensive library of algorithms provided with TestMAX SMS.Tester Patterns and DiagnosticsThe SMS Yield Accelerator addresses the need to rapidly, cost-effectively and accurately identify, analyze, isolate and classify memory faults as designs are readied for transition from first silicon to volume manufacturing. Leveraging the infrastructure of TestMAX SMS, the Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results. Using this feature, test and product engineers can rapidly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the IP vendoror SoC designer.On-Chip Self-RepairUnlike complex external repair flows, TestMAX SMS’s on-chip repair is fully automated. A built-in self-diagnosis module determines the location of any memory defect and provides error logging by scanning out failure data for silicon debug. When testing memories with redundancies that have failures, a built-in repair and redundancy allocation module identifies available redundant elements and determines the best possible redundancy configuration.Silicon Bring-up and CharacterizationThe SMS Silicon Browser has advanced automation capabilities to interactively communicate through a JTAG port with the system’s infrastructure in a chip for post-silicon bring-up, system debug, diagnosis and characterization of embedded memories. The unique features of the Silicon Browser allow extraction of memory contents, multi-corner and multivoltage characterization, precise physical failure localization, defect classification and redundancy utilization analysis, all from an engineer’s desktop and without the need for expensive automatic test equipment.Additional Memory SupportDesignWare SMS is the customizable version of the TestMAX SMS product, suitable for support of external memories, MRAM, eFlash and content addressable memories (CAM).2Design FormatsTestMAX SMS supports the following data formats:• Design: VHDL, Verilog (RTL or netlist), SystemVerilog• Constraints: SDC and SpyGlass SGDC, Tcl• Power: UPF• Assertion: OVL, SV• Verification: SAIF, VCD, FSDB• Memory description: MASIS©2021 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.09/16/21.CS754112150-TestMAX SMS DS.。