LPC2292_2294_en

1.General descriptionThe LPC2131/32/34/36/38 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine the microcontroller with 32kB, 64kB, 128kB, 256kB and 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate.For critical code size applications,the alternative 16-bit Thumb mode reduces code by more than 30% with minimal performance penalty.Due to their tiny size and low power consumption, these microcontrollers are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM options of 8kB, 16kB, and 32kB, they are very well suited for communication gateways and protocol converters, soft modems, voice recognition and low-end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit 8-channel ADC(s), 10-bit DAC, PWM channels and 47 GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems.2.Features2.1Enhancements brought by LPC213x/01 devicesI Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original LPC213x. They also allow for a port pin to be read at any time regardless of its function.I Dedicated result registers for ADC(s) reduce interrupt overhead.I UART0/1 include fractional baud rate generator, auto-bauding capabilities and handshake flow-control fully implemented in hardware.I Additional BOD control enables further reduction of power consumption.2.2Key features common for LPC213x and LPC213x/01I 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 or HVQFN package.I 8/16/32kB of on-chip static RAM and 32/64/128/256/512kB of on-chip flash program memory. 128-bit wide interface/accelerator enables high-speed 60MHz operation.I In-System Programming/In-Application Programming (ISP/IAP)via on-chip bootloader software.Single flash sector or full chip erase in 400ms and programming of 256B in 1 ms.I EmbeddedICE RT and Embedded T race interfaces offer real-time debugging with the on-chip RealMonitor software and high-speed tracing of instruction execution.LPC2131/32/34/36/38Single-chip 16/32-bit microcontrollers; 32/64/128/256/512kB ISP/IAP flash with 10-bit ADC and DACRev. 04 — 16 October 2007Product data sheetI One (LPC2131/32) or two (LPC2134/36/38) 8-channel 10-bit ADCs provide a total ofup to 16 analog inputs, with conversion times as low as 2.44µs per channel.I Single 10-bit DAC provides variable analog output (LPC2132/34/36/38).I T wo 32-bit timers/external event counters (with four capture and four comparechannels each), PWM unit (six outputs) and watchdog.I Low power Real-time clock with independent power and dedicated 32 kHz clock input.I Multiple serial interfaces including two UARTs(16C550),two Fast I2C-bus(400kbit/s),SPI and SSP with buffering and variable data length capabilities.I Vectored interrupt controller with configurable priorities and vector addresses.I Up to forty-seven 5V tolerant general purpose I/O pins in tiny LQFP64 or HVQFNpackage.I Up to nine edge or level sensitive external interrupt pins available.I60MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100µs.I On-chip integrated oscillator operates with external crystal in range of 1MHz to30MHz and with external oscillator up to 50MHz.I Power saving modes include Idle and Power-down.I Individual enable/disable of peripheral functions as well as peripheral clock scalingdown for additional power optimization.I Processor wake-up from Power-down mode via external interrupt or BOD.I Single power supply chip with POR and BOD circuits:N CPU operating voltage range of 3.0V to 3.6V (3.3V± 10%) with 5V tolerant I/Opads.3.Ordering informationTable 1.Ordering informationType number PackageName Description Version LPC2131FBD64LQFP64plastic low profile quad flat package; 64 leads;SOT314-2body 10×10×1.4mmSOT314-2 LPC2131FBD64/01LQFP64plastic low profile quad flat package; 64 leads;body 10×10×1.4mmSOT314-2 LPC2132FBD64LQFP64plastic low profile quad flat package; 64 leads;body 10×10×1.4mmLPC2132FBD64/01LQFP64plastic low profile quad flat package; 64 leads;SOT314-2body 10×10×1.4mmSOT804-2 LPC2132FHN64HVQFN64plastic thermal enhanced very thin quad flatpackage; no leads; 64 terminals; body9×9×0.85mmSOT804-2 LPC2132FHN64/01HVQFN64plastic thermal enhanced very thin quad flatpackage; no leads; 64 terminals; body9×9×0.85mmSOT314-2 LPC2134FBD64LQFP64plastic low profile quad flat package; 64 leads;body 10×10×1.4mmLPC2134FBD64/01LQFP64plastic low profile quad flat package; 64 leads;SOT314-2body 10×10×1.4mm3.1Ordering optionsLPC2136FBD64LQFP64plastic low profile quad flat package; 64 leads;body 10×10×1.4mmSOT314-2LPC2136FBD64/01LQFP64plastic low profile quad flat package; 64 leads;body 10×10×1.4mmSOT314-2LPC2138FBD64LQFP64plastic low profile quad flat package; 64 leads;body 10× 10×1.4mmSOT314-2LPC2138FBD64/01LQFP64plastic low profile quad flat package; 64 leads;body 10× 10×1.4mmSOT314-2LPC2138FHN64HVQFN64plastic thermal enhanced very thin quad flatpackage; no leads; 64 terminals; body 9×9×0.85mmSOT804-2LPC2138FHN64/01HVQFN64plastic thermal enhanced very thin quad flatpackage; no leads; 64 terminals; body 9×9×0.85mmSOT804-2Table 1.Ordering information …continuedType number Package NameDescriptionVersion Table 2.Ordering optionsType numberFlash memory RAM ADCDACEnhanced UARTs,ADC,Fast I/Os,and BODTemperature range LPC2131FBD6432kB 8kB 1-no −40°C to +85°C LPC2131FBD64/0132kB 8kB1-yes −40°C to +85°C LPC2132FBD6464kB 16kB 11no −40°C to +85°C LPC2132FBD64/0164kB 16kB 11yes −40°C to +85°C LPC2132FHN6464kB 16kB 11no −40°C to +85°C LPC2132FHN64/0164kB 16kB 11yes −40°C to +85°C LPC2134FBD64128kB 16kB 21no −40°C to +85°C LPC2134FBD64/01128kB 16kB 21yes −40°C to +85°C LPC2136FBD64256kB 32kB 21no −40°C to +85°C LPC2136FBD64/01256kB 32kB 21yes −40°C to +85°C LPC2138FBD64512kB 32kB 21no −40°C to +85°C LPC2138FBD64/01512kB 32kB 21yes −40°C to +85°C LPC2138FHN64512kB 32kB 21no −40°C to +85°C LPC2138FHN64/01512kB32kB 21yes−40°C to +85°C4.Block diagram(1)LPC2134/36/38 only.(2)LPC2132/34/36/38 only.(3)Pins shared with GPIO.Fig 1.Block diagramSCL0,1P0[31:0]P1[31:16]P0[31:0]P1[31:16]SDA0,1XTAL2XTAL1SCK0,1MOSI0,1MISO0,1EINT[3:0]AD0[7:0]PWM[6:1]SSEL0,1TXD0,1RXD0,1AHB BRIDGEPLLUART0/UART1REAL TIME CLOCKPWM0ARM7TDMI-SRESET LPC2131, LPC2131/01LPC2132, LPC2132/01LPC2134, LPC2134/01LPC2136, LPC2136/01LPC2138, LPC2138/018 × CAP 8 × MAT AD1[7:0](1)AOUT (2)DSR1(1),CTS1(1)RTS1(1), DTR1(1)DCD1(1), RI1(1)002aab067TRST (3)TMS (3)TCK (3)TDI (3)TDO (3)tracesignalsFAST GENERAL PURPOSE I/OINTERNAL SRAM CONTROLLERINTERNAL FLASH CONTROLLER8/16/32 kB SRAM32/64/128/256/512 kB FLASHEXTERNAL INTERRUPTSCAPTURE/COMPARE TIMER 0/TIMER 1A/D CONVERTERS0 AND 1(1)D/A CONVERTER (2)GENERAL PURPOSE I/OSYSTEM CONTROLWATCHDOG TIMERRTCX2RTCX1SPI AND SSP SERIAL INTERFACESI 2C SERIALINTERFACES 0 AND 1APB (ARM peripheral bus)AHB TO APB BRIDGEAPB DIVIDERAHB DECODERAMBA AHB(Advanced High-performance Bus)VECTORED INTERRUPT CONTROLLERSYSTEM FUNCTIONS system clockE M U L A T I O NT R A C E M O D U L ETEST/DEBUG INTERFACEARM7 local busVBAT5.Pinning information5.1PinningFig 2.LPC2131 LQFP64 pinningLPC2131LPC2131/01P0.21/PWM5/CAP1.3P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0P0.17/CAP1.2/SCK1/MAT1.2RTCX1P0.16/EINT0/MAT0.2/CAP0.2P1.19/TRACEPKT3P0.15/EINT2RTCX2P1.21/PIPESTAT0V SS V DD V DDAV SSP1.18/TRACEPKT2P0.14/EINT1/SDA1P0.25/AD0.4P1.22/PIPESTAT1P0.26/AD0.5P0.13/MAT1.1P0.27/AD0.0/CAP0.1/MAT0.1P0.12/MAT1.0P1.17/TRACEPKT1P0.11/CAP1.1/SCL1P0.28/AD0.1/CAP0.2/MAT0.2P1.23/PIPESTAT2P0.29/AD0.2/CAP0.3/MAT0.3P0.10/CAP1.0P0.30/AD0.3/EINT3/CAP0.0P0.9/RXD1/PWM6/EINT3P1.16/TRACEPKT0P0.8/TXD1/PWM4P 0.31P 1.27/T D OV S S V R E FP 0.0/T X D 0/P W M 1X T A L 1P 1.31/T R S T X T A L 2P 0.1/R X D 0/P W M 3/E I N T 0P 1.28/T D IP 0.2/S C L 0/C A P 0.0V S S AV D D P 0.23P 1.26/R T C K R E S E TV S S P 1.29/T C KP 0.3/S D A 0/M A T 0.0/E I N T 1P 0.20/M A T 1.3/S S E L 1/E I N T 3P 0.4/S C K 0/C A P 0.1/A D 0.6P 0.19/M A T 1.2/M O S I 1/C A P 1.2P 1.25/E X T I N 0P 0.18/C A P 1.3/M I S O 1/M A T 1.3P 0.5/M I S O 0/M A T 0.1/A D 0.7P 1.30/T M SP 0.6/M O S I 0/C A P 0.2V D DP 0.7/S S E L 0/P W M 2/E I N T 2V S SP 1.24/T R A C E C L K V B A T002aab06812345678910111213141516484746454443424140393837363534331718192021222324252627282930313264636261605958575655545352515049Fig 3.LPC2132 LQFP64 pin configurationLPC2132LPC2132/01P0.21/PWM5/CAP1.3P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0P0.17/CAP1.2/SCK1/MAT1.2RTCX1P0.16/EINT0/MAT0.2/CAP0.2P1.19/TRACEPKT3P0.15/EINT2RTCX2P1.21/PIPESTAT0V SS V DD V DDAV SSP1.18/TRACEPKT2P0.14/EINT1/SDA1P0.25/AD0.4/AOUTP1.22/PIPESTAT1P0.26/AD0.5P0.13/MAT1.1P0.27/AD0.0/CAP0.1/MAT0.1P0.12/MAT1.0P1.17/TRACEPKT1P0.11/CAP1.1/SCL1P0.28/AD0.1/CAP0.2/MAT0.2P1.23/PIPESTAT2P0.29/AD0.2/CAP0.3/MAT0.3P0.10/CAP1.0P0.30/AD0.3/EINT3/CAP0.0P0.9/RXD1/PWM6/EINT3P1.16/TRACEPKT0P0.8/TXD1/PWM4P 0.31P 1.27/T D OV S S V R E FP 0.0/T X D 0/P W M 1X T A L 1P 1.31/T R S T X T A L 2P 0.1/R X D 0/P W M 3/E I N T 0P 1.28/T D IP 0.2/S C L 0/C A P 0.0V S S AV D D P 0.23P 1.26/R T C K R E S E TV S S P 1.29/T C KP 0.3/S D A 0/M A T 0.0/E I N T 1P 0.20/M A T 1.3/S S E L 1/E I N T 3P 0.4/S C K 0/C A P 0.1/A D 0.6P 0.19/M A T 1.2/M O S I 1/C A P 1.2P 1.25/E X T I N 0P 0.18/C A P 1.3/M I S O 1/M A T 1.3P 0.5/M I S O 0/M A T 0.1/A D 0.7P 1.30/T M SP 0.6/M O S I 0/C A P 0.2V D DP 0.7/S S E L 0/P W M 2/E I N T 2V S SP 1.24/T R A C E C L K V B A T002aab40612345678910111213141516484746454443424140393837363534331718192021222324252627282930313264636261605958575655545352515049Fig 4.LPC2134/36/38 LQFP64 pin configurationLPC2134, LPC2134/01LPC2136, LPC2136/01LPC2138, LPC2138/01P0.21/PWM5/AD1.6/CAP1.3P1.20/TRACESYNC P0.22/AD1.7/CAP0.0/MAT0.0P0.17/CAP1.2/SCK1/MAT1.2RTCX1P0.16/EINT0/MAT0.2/CAP0.2P1.19/TRACEPKT3P0.15/RI1/EINT2/AD1.5RTCX2P1.21/PIPESTAT0V SS V DD V DDAV SSP1.18/TRACEPKT2P0.14/DCD1/EINT1/SDA1P0.25/AD0.4/AOUTP1.22/PIPESTAT1P0.26/AD0.5P0.13/DTR1/MAT1.1/AD1.4P0.27/AD0.0/CAP0.1/MAT0.1P0.12/DSR1/MAT1.0/AD1.3P1.17/TRACEPKT1P0.11/CTS1/CAP1.1/SCL1P0.28/AD0.1/CAP0.2/MAT0.2P1.23/PIPESTAT2P0.29/AD0.2/CAP0.3/MAT0.3P0.10/RTS1/CAP1.0/AD1.2P0.30/AD0.3/EINT3/CAP0.0P0.9/RXD1/PWM6/EINT3P1.16/TRACEPKT0P0.8/TXD1/PWM4/AD1.1P 0.31P 1.27/T D OV S S V R E FP 0.0/T X D 0/P W M 1X T A L 1P 1.31/T R S T X T A L 2P 0.1/R X D 0/P W M 3/E I N T 0P 1.28/T D IP 0.2/S C L 0/C A P 0.0V S S AV D D P 0.23P 1.26/R T C K R E S E TV S S P 1.29/T C KP 0.3/S D A 0/M A T 0.0/E I N T 1P 0.20/M A T 1.3/S S E L 1/E I N T 3P 0.4/S C K 0/C A P 0.1/A D 0.6P 0.19/M A T 1.2/M O S I 1/C A P 1.2P 1.25/E X T I N 0P 0.18/C A P 1.3/M I S O 1/M A T 1.3P 0.5/M I S O 0/M A T 0.1/A D 0.7P 1.30/T M SP 0.6/M O S I 0/C A P 0.2/A D 1.0V D DP 0.7/S S E L 0/P W M 2/E I N T 2V S SP 1.24/T R A C E C L K V B A T002aab40712345678910111213141516484746454443424140393837363534331718192021222324252627282930313264636261605958575655545352515049AD1.7 to AD1.0 only available on LPC2134/36/38.Fig 5.LPC2132/38 HVQFN64 pin configuration002aab943LPC2132/2138T ransparent top view16331534143513361237113810399408417426435444453462471486463626160595857565554535251504917181920212223242526272829303132terminal 1index areaP0.21/PWM5/AD1.6/CAP1.3P0.22/AD1.7/CAP0.0/MAT0.0RTCX1P1.19/TRACEPKT3RTCX2V SS V DDAP1.18/TRACEPKT2P0.25/AD0.4/AOUTP0.26/AD0.5P0.27/AD0.0/CAP0.1/MAT0.1P1.17/TRACEPKT1P0.28/AD0.1/CAP0.2/MAT0.2P0.29/AD0.2/CAP0.3/MAT0.3P0.30/AD0.3/EINT3/CAP0.0P1.16/TRACEPKT0P 1.27/T D OV R E FX T A L 1X T A L 2P 1.28/T D IV S S AP 0.23R E S E TP 1.29/T C KP 0.20/M A T 1.3/S S E L 1/E I N T 3P 0.19/M A T 1.2/M O S I 1/C A P 1.2P 0.18/C A P 1.3/M I S O 1/M A T 1.3P 1.30/T M SV D DV S SV B A TP1.20/TRACESYNC P0.17/CAP1.2/SCK1/MAT1.2P0.16/EINT0/MAT0.2/CAP0.2P0.15/RI1/EINT2/AD1.5P1.21/PIPESTAT0V DD V SSP0.14/DCD1/EINT1/SDA1P1.22/PIPESTAT1P0.13/DTR1/MAT1.1/AD1.4P0.12/DSR1/MAT1.0/AD1.3P0.11/CTS1/CAP1.1/SCL1P1.23/PIPESTAT2P0.10/RTS1/CAP1.0/AD1.2P0.9/RXD1/PWM6/EINT3P0.8/TXD1/PWM4/AD1.1P 0.31V S S P 0.0/T X D 0/P W M 1P 1.31/T R S T P 0.1/R X D 0/P W M 3/E I N T 0P 0.2/S C L 0/C A P 0.0V D D P 1.26/R T C K V S S P 0.3/S D A 0/M A T 0.0/E I N T 1P 0.4/S C K 0/C A P 0.1/A D 0.6P 1.25/E X T I N 0P 0.5/M I S O 0/M A T 0.1/A D 0.7P 0.6/M O S I 0/C A P 0.2/A D 1.0P 0.7/S S E L 0/P W M 2/E I N T 2P 1.24/T R A C E C L K5.2Pin descriptionTable 3.Pin descriptionSymbol Pin Type DescriptionP0.0 to P0.31I/O Port0:Port0is a32-bit I/O port with individual direction controls for each bit.T otal of 31 pins of the Port 0 can be used as a general purpose bidirectionaldigital I/Os while P0.31 is output only pin. The operation of port 0 pinsdepends upon the pin function selected via the pin connect block.Pin P0.24 is not available.P0.0/TXD0/ PWM119[1]O TXD0 —Transmitter output for UART0.O PWM1 —Pulse Width Modulator output 1.P0.1/RXD0/ PWM3/EINT021[2]I RXD0 —Receiver input for UART0.O PWM3 —Pulse Width Modulator output 3.I EINT0 —External interrupt 0 input.P0.2/SCL0/ CAP0.022[3]I/O SCL0 —I2C0 clock input/output. Open drain output (for I2C-bus compliance).I CAP0.0 —Capture input for Timer0, channel 0.P0.3/SDA0/ MA T0.0/EINT126[3]I/O SDA0 —I2C0 data input/output. Open drain output (for I2C-bus compliance).O MAT0.0 —Match output for Timer0, channel 0.I EINT1 —External interrupt 1 input.P0.4/SCK0/ CAP0.1/AD0.627[4]I/O SCK0 —Serial clock for SPI0.SPI clock output from master or input to slave.I CAP0.1 —Capture input for Timer0, channel 1.I AD0.6 —ADC 0, input 6. This analog input is always connected to its pin.P0.5/MISO0/ MA T0.1/AD0.729[4]I/O MISO0 —Master In Slave V DD = 3.6 V for SPI0. Data input to SPI master ordata output from SPI slave.O MAT0.1 —Match output for Timer0, channel 1.I AD0.7 —ADC 0, input 7. This analog input is always connected to its pin.P0.6/MOSI0/ CAP0.2/AD1.030[4]I/O MOSI0 —Master Out Slave In for SPI0.Data output from SPI master or datainput to SPI slave.I CAP0.2 —Capture input for Timer0, channel 2.I AD1.0 —ADC 1, input 0. This analog input is always connected to its pin.Available in LPC2134/36/38 only.P0.7/SSEL0/ PWM2/EINT231[2]I SSEL0 —Slave Select for SPI0. Selects the SPI interface as a slave.O PWM2 —Pulse Width Modulator output 2.I EINT2 —External interrupt 2 input.P0.8/TXD1/ PWM4/AD1.133[4]O TXD1 —Transmitter output for UART1.O PWM4 —Pulse Width Modulator output 4.I AD1.1 —ADC 1, input 1. This analog input is always connected to its pin.Available in LPC2134/36/38 only.P0.9/RXD1/ PWM6/EINT334[2]I RXD1 —Receiver input for UART1.O PWM6 —Pulse Width Modulator output 6.I EINT3 —External interrupt 3 input.P0.10/RTS1/ CAP1.0/AD1.235[4]O RTS1 —Request to Send output for UART1. Available in LPC2134/36/38.I CAP1.0 —Capture input for Timer1, channel 0.I AD1.2 —ADC 1, input 2. This analog input is always connected to its pin.Available in LPC2134/36/38 only.P0.11/CTS1/ CAP1.1/SCL137[3]I CTS1 —Clear to Send input for UART1. Available in LPC2134/36/38.I CAP1.1 —Capture input for Timer1, channel 1.I/O SCL1 —I2C1 clock input/output. Open drain output (for I2C-bus compliance)P0.12/DSR1/ MA T1.0/AD1.338[4]I DSR1 —Data Set Ready input for UART1. Available in LPC2134/36/38.O MAT1.0 —Match output for Timer1, channel 0.I AD1.3 —ADC 1, input 3. This analog input is always connected to its pin.Available in LPC2134/36/38 only.P0.13/DTR1/ MA T1.1/AD1.439[4]O DTR1 —Data Terminal Ready output for UART1. Available inLPC2134/36/38.O MAT1.1 —Match output for Timer1, channel 1.I AD1.4 —ADC 1, input 4. This analog input is always connected to its pin.Available in LPC2134/36/38 only.P0.14/DCD1/ EINT1/SDA141[3]I DCD1 —Data Carrier Detect input for UART1. Available in LPC2134/36/38.I EINT1 —External interrupt 1 input.I/O SDA1 —I2C1 data input/output. Open drain output (for I2C-bus compliance).P0.15/RI1/ EINT2/AD1.545[4]I RI1 —Ring Indicator input for UART1. Available in LPC2134/36/38.I EINT2 —External interrupt 2 input.I AD1.5 —ADC 1, input 5. This analog input is always connected to its pin.Available in LPC2134/36/38 only.P0.16/EINT0/ MA T0.2/CAP0.246[2]I EINT0 —External interrupt 0 input.O MAT0.2 —Match output for Timer0, channel 2.I CAP0.2 —Capture input for Timer0, channel 2.P0.17/CAP1.2/ SCK1/MA T1.247[1]I CAP1.2 —Capture input for Timer1, channel 2.I/O SCK1 —Serial Clock for SSP. Clock output from master or input to slave.O MAT1.2 —Match output for Timer1, channel 2.P0.18/CAP1.3/ MISO1/MA T1.353[1]I CAP1.3 —Capture input for Timer1, channel 3.I/O MISO1 —Master In Slave Out for SSP. Data input to SPI master or dataoutput from SSP slave.O MAT1.3 —Match output for Timer1, channel 3.P0.19/MA T1.2/ MOSI1/CAP1.254[1]O MAT1.2 —Match output for Timer1, channel 2.I/O MOSI1 —Master Out Slave In for SSP.Data output from SSP master or datainput to SSP slave.I CAP1.2 —Capture input for Timer1, channel 2.P0.20/MA T1.3/ SSEL1/EINT355[2]O MAT1.3 —Match output for Timer1, channel 3.I SSEL1 —Slave Select for SSP. Selects the SSP interface as a slave.I EINT3 —External interrupt 3 input.P0.21/PWM5/ AD1.6/CAP1.31[4]O PWM5 —Pulse Width Modulator output 5.I AD1.6 —ADC 1, input 6. This analog input is always connected to its pin.Available in LPC2134/36/38 only.I CAP1.3 —Capture input for Timer1, channel 3.Table 3.Pin description …continuedSymbol Pin Type DescriptionP0.22/AD1.7/ CAP0.0/MA T0.02[4]I AD1.7 —ADC 1, input 7. This analog input is always connected to its pin.Available in LPC2134/36/38 only.I CAP0.0 —Capture input for Timer0, channel 0.O MAT0.0 —Match output for Timer0, channel 0.P0.2358[1]I/O General purpose digital input/output pin.P0.25/AD0.4/ AOUT 9[5]I AD0.4 —ADC 0, input 4. This analog input is always connected to its pin.O AOUT —DAC output. Not available in LPC2131.P0.26/AD0.510[4]I AD0.5 —ADC 0, input 5. This analog input is always connected to its pin.P0.27/AD0.0/ CAP0.1/MA T0.111[4]I AD0.0 —ADC 0, input 0. This analog input is always connected to its pin.I CAP0.1 —Capture input for Timer0, channel 1.O MAT0.1 —Match output for Timer0, channel 1.P0.28/AD0.1/ CAP0.2/MA T0.213[4]I AD0.1 —ADC 0, input 1. This analog input is always connected to its pin.I CAP0.2 —Capture input for Timer0, channel 2.O MAT0.2 —Match output for Timer0, channel 2.P0.29/AD0.2/ CAP0.3/MA T0.314[4]I AD0.2 —ADC 0, input 2. This analog input is always connected to its pin.I CAP0.3 —Capture input for Timer0, channel 3.O MAT0.3 —Match output for Timer0, channel 3.P0.30/AD0.3/ EINT3/CAP0.015[4]I AD0.3 —ADC 0, input 3. This analog input is always connected to its pin.I EINT3 —External interrupt 3 input.I CAP0.0 —Capture input for Timer0, channel 0.P0.3117[6]O General purpose digital output only pin.Important: This pin MUST NOT be externally pulled LOW when RESET pinis LOW or the JTAG port will be disabled.P1.0 to P1.31I/O Port1:Port1is a32-bit bidirectional I/O port with individual direction controlsfor each bit. The operation of port 1 pins depends upon the pin functionselected via the pin connect block. Pins 0 through 15 of port1 are notavailable.P1.16/TRACEPKT016[6]O TRACEPKT0 —T race Packet, bit 0. Standard I/O port with internal pull-up.P1.17/TRACEPKT112[6]O TRACEPKT1 —T race Packet, bit 1. Standard I/O port with internal pull-up.P1.18/TRACEPKT28[6]O TRACEPKT2 —T race Packet, bit 2. Standard I/O port with internal pull-up.P1.19/TRACEPKT34[6]O TRACEPKT3 —T race Packet, bit 3. Standard I/O port with internal pull-up.P1.20/ TRACESYNC 48[6]O TRACESYNC —Trace Synchronization. Standard I/O port with internalpull-up. LOW on TRACESYNC while RESET is LOW enables pins P1.25:16to operate as Trace port after reset.P1.21/PIPEST A T044[6]O PIPESTAT0 —Pipeline Status, bit 0. Standard I/O port with internal pull-up.P1.22/PIPEST A T140[6]O PIPESTAT1 —Pipeline Status, bit 1. Standard I/O port with internal pull-up.P1.23/ PIPEST A T236[6]O PIPESTAT2 —Pipeline Status, bit 2. Standard I/O port with internal pull-up.Table 3.Pin description …continuedSymbol Pin Type Description[1]5V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control.[2]5V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.[3]Open drain 5V tolerant digital I/O I 2C-bus 400kHz specification compatible pad. It requires external pull-up to provide an output functionality.[4]5V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10ns slew rate control)and analog input function.If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled.[5]5V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10ns slew rate control) and analog output function. When configured as the DAC output, digital section of the pad is disabled.[6]5V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10ns slew rate control.The pull-up resistor’s value ranges from 60 k Ω to 300 k Ω.[7]5V tolerant pad providing digital input (with TTL levels and hysteresis) function only.[8]Pad provides special analog functionality.P1.24/TRACECLK 32[6]O TRACECLK —Trace Clock. Standard I/O port with internal pull-up.P1.25/EXTIN028[6]I EXTIN0 —External T rigger Input. Standard I/O with internal pull-up.P1.26/RTCK24[6]I/ORTCK —Returned Test Clock output. Extra signal added to the JT AG port.Assists debugger synchronization when processor frequency varies.Bidirectional pin with internal pull-up. LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate as Debug port after reset.P1.27/TDO 64[6]O TDO —Test Data out for JTAG interface.P1.28/TDI 60[6]I TDI —Test Data in for JTAG interface.P1.29/TCK 56[6]I TCK —Test Clock for JTAG interface.P1.30/TMS 52[6]I TMS —Test Mode Select for JTAG interface.P1.31/TRST 20[6]I TRST —Test Reset for JTAG interface.RESET57[7]IExternal reset input:A LOW on this pin resets the device,causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5V tolerant.XT AL162[8]I Input to the oscillator circuit and internal clock generator circuits.XT AL261[8]O Output from the oscillator amplifier.RTCX13[8]I Input to the RTC oscillator circuit.RTCX25[8]OOutput from the RTC oscillator circuit.V SS 6,18,25,42,50I Ground: 0V reference.V SSA 59I Analog ground: 0V reference. This should nominally be the same voltage as V SS , but should be isolated to minimize noise and error.V DD 23, 43, 51I 3.3V power supply: This is the power supply voltage for the core and I/O ports.V DDA7IAnalog 3.3V power supply: This should be nominally the same voltage as V DD but should be isolated to minimize noise and error. This voltage is used to power the on-chip PLL.VREF 63IADC reference: This should be nominally the same voltage as V DD butshould be isolated to minimize noise and error. Level on this pin is used as a reference for A/D and D/A convertor(s).VBAT49IRTC power supply: 3.3 V on this pin supplies the power to the RTC.Table 3.Pin description …continuedSymbolPin Type Description6.Functional description6.1Architectural overviewThe ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers highperformance and very low power consumption. The ARM architecture is based onReduced Instruction Set Computer (RISC) principles, and the instruction set and relateddecode mechanism are much simpler than those of microprogrammed ComplexInstruction Set Computers. This simplicity results in a high instruction throughput andimpressive real-time interrupt response from a small and cost-effective processor core.Pipeline techniques are employed so that all parts of the processing and memory systemscan operate continuously. Typically, while one instruction is being executed, its successoris being decoded, and a third instruction is being fetched from memory.The ARM7TDMI-S processor also employs a unique architectural strategy known asThumb, which makes it ideally suited to high-volume applications with memoryrestrictions, or applications where code density is an issue.The key idea behind Thumb is that of a super-reduced instruction set. Essentially, theARM7TDMI-S processor has two instruction sets:•The standard 32-bit ARM set.• A 16-bit Thumb set.The Thumb set’s 16-bit instruction length allows it to approach twice the density ofstandard ARM code while retaining most of the ARM’s performance advantage over atraditional 16-bit processor using 16-bit registers. This is possible because Thumb codeoperates on the same 32-bit register set as ARM code.Thumb code is able to provide up to 65% of the code size of ARM, and 160% of theperformance of an equivalent ARM processor connected to a 16-bit memory system.6.2On-chip flash program memoryThe LPC2131/32/34/36/38 incorporate a 32kB, 64kB, 128kB, 256kB and 512kB flashmemory system respectively. This memory may be used for both code and data storage.Programming of the flash memory may be accomplished in several ways. It may beprogrammed In System via the serial port.The application program may also erase and/orprogram the flash while the application is running, allowing a great degree of flexibility fordata storage field firmware upgrades, etc. When the LPC2131/32/34/36/38 on-chipbootloader is used, 32/64/128/256/500kB of flash memory is available for user code.The LPC2131/32/34/36/38 flash memory provides a minimum of 100000 erase/writecycles and 20 years of data-retention.6.3On-chip static RAMOn-chip static RAM may be used for code and/or data storage. The SRAM may beaccessed as 8-bit, 16-bit, and 32-bit. The LPC2131, LPC2132/34, and LPC2136/38provide 8kB, 16kB and 32kB of static RAM respectively.。

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VDDC DC/DC
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LH75401/LH75411 Preliminary data sheet System-on-ChipDESCRIPTIONThe NXP BlueStreak LH75401/LH75411 family con-sists of two low-cost 16/32-bit System-on-Chip (SoC) devices.•LH75401 — contains the superset of features.•LH75411 — similar to LH75401, without CAN 2.0B.COMMON FEATURES•Highly Integrated System-on-Chip•ARM7TDMI-S™ Core•High Performance (84 MHz CPU Speed)–Internal PLL Driven or External Clock Driven–Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20MHz •32kB On-chip SRAM–16kB Tightly Coupled Memory (TCM) SRAM–16kB Internal SRAM•Clock and Power Management–Low Power Modes: Standby, Sleep, Stop •Eight Channel, 10-bit Analog-to-Digital Converter •Integrated Touch Screen Controller•Serial interfaces–Two 16C550-type UARTs supporting baud rates up to 921,600 baud (requires crystal frequency of14.756 MHz).–One 82510-type UART supporting baud rates up to 3,225,600 baud (requires a system clock of70MHz).•Synchronous Serial Port–Motorola SPI™–National Semiconductor Microwire™–Texas Instruments SSI•Real-Time Clock (RTC)•Three Counter/Timers–Capture/Compare/PWM Compatibility–Watchdog Timer (WDT)•Low-Voltage Detector •JTAG Debug Interface and Boundary Scan •Single 3.3 V Supply• 5 V Tolerant Digital I/O–XTALIN and XTAL32IN inputs are 1.8 V ± 10%•144-pin LQFP Package•−40°C to +85°C Operating TemperatureUnique Features of the LH75401•Color and Grayscale Liquid Crystal Display (LCD) Controller–12-bit (4,096) Direct Mode Color, up to VGA–8-bit (256) Direct or Palettized Color, up to SVGA –4-bit (16) Direct Mode Color/Grayscale, up to XGA –12-bit Video Bus–Supports STN, TF T, HR-TF T, and AD-TF T Displays.•CAN Controller that supports CAN version 2.0B.Unique Features of the LH75411•Color and Grayscale LCD Controller (LCDC)–12-bit (4,096) Direct Mode Color, up to VGA–8-bit (256) Direct or Palettized Color, up to SVGA –4-bit (16) Direct Mode Color/Grayscale, up to XGA –12-bit Video Bus–Supports STN, TF T, HR-TF T, and AD-TF T Displays.元器件交易网Preliminary data sheet 1LH75401/LH75411System-on-Chip2Rev. 01— 16 July 2007Preliminary data sheetNXP SemiconductorsORDERING INFORMATIONTable 1.Ordering informationType number PackageVersionName DescriptionLH75401N0Q100C0LQFP144plastic low profile quad flat package; 144 leads;body 20 x 20 x 1.4 mmSOT486-1LH75411N0Q100C0LQFP144plastic low profile quad flat package; 144 leads;body 20 x 20 x 1.4 mmSOT486-1元器件交易网System-on-ChipLH75401/LH75411Preliminary data sheet Rev. 01 — 16 July 2007 3NXP SemiconductorsLH75401 BLOCK DIAGRAMFigure 1.LH75401 Block Diagram元器件交易网LH75401/LH75411System-on-Chip4Rev. 01— 16 July 2007Preliminary data sheetNXP SemiconductorsLH75411 BLOCK DIAGRAMFigure 2.LH75411 Block Diagram元器件交易网System-on-ChipLH75401/LH75411Preliminary data sheet Rev. 01 — 16 July 2007 5NXP SemiconductorsPIN CONFIGURATIONFigure 3.LH75401/LH75411 pin configuration元器件交易网LH75401/LH75411System-on-Chip6Rev. 01— 16 July 2007Preliminary data sheetNXP SemiconductorsLH75401 Numerical Pin ListingTable 2.LH75401 Numerical Pin ListPIN NO.FUNCTION AT RESETFUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPE BEHAVIOR DURINGRESETNOTES 1PA7D15I/O 8 mA Bidirectional Pull-up 12PA6D14I/O 8 mA Bidirectional Pull-up 13VDD Power None 4PA5D13I/O 8 mA Bidirectional Pull-up 15PA4D12I/O 8 mA Bidirectional Pull-up 16PA3D11I/O 8 mA Bidirectional Pull-up 17PA2D10I/O 8 mA Bidirectional Pull-up 18VSS Ground None 9PA1D9I/O 8 mA Bidirectional Pull-up 110PA0D8I/O 8 mA Bidirectional Pull-up 111VDDC Power None 12D7I/O 8 mA Bidirectional Pull-up 13D6I/O 8 mA Bidirectional Pull-up 14VSSC Ground None 15D5I/O 8 mA Bidirectional Pull-up 16D4I/O 8 mA Bidirectional Pull-up 17VDD Power None 18D3I/O 8 mA Bidirectional Pull-up 19D2I/O 8 mA Bidirectional Pull-up 20D1I/O 8 mA Bidirectional Pull-up 21D0I/O8 mA Bidirectional Pull-up 22nWE 8 mA Output HIGH 323nOE 8 mA Output HIGH 324PB5nWAIT 8 mA Bidirectional Pull-up 1, 325PB4nBLE18 mA Bidirectional Pull-up 1, 326VSS GroundNone 27PB3nBLE08 mA Bidirectional Pull-up 1, 328PB2nCS38 mA Bidirectional Pull-up 1, 329PB1nCS28 mA Bidirectional Pull-up 1, 330PB0nCS18 mA Bidirectional Pull-up 1, 331nCS08 mA Output Pull-up 332PC7A238 mA Bidirectional Pull-down 133PC6A228 mA BidirectionalPull-down134VDD PowerNone 35PC5A218 mA Bidirectional Pull-down 136PC4A208 mA Bidirectional Pull-down 137PC3A198 mA Bidirectional Pull-down 138PC2A188 mABidirectionalPull-down1元器件交易网System-on-ChipLH75401/LH75411Preliminary data sheet Rev. 01 — 16 July 2007 7NXP Semiconductors39PC1A178 mA Bidirectional Pull-down 140PC0A168 mA BidirectionalPull-down141VSS Ground None 42VDD PowerNone 43A158 mA Output LOW 44A148 mA Output LOW 45A138 mA Output LOW 46A128 mA Output LOW 47A118 mA OutputLOW48VSS GroundNone 49A108 mA Output LOW 50A98 mA Output LOW 51A88 mA Output LOW 52A78 mA Output LOW 53A68 mA OutputLOW54VDD Power None 55A58 mA Output LOW 56A48 mA Output LOW 57A38 mA Output LOW 58A28 mA OutputLOW59VSS Ground None 60A18 mA Output LOW 61A08 mA Output LOW 62nRESETIN None Input Pull-up 2, 363TEST2None Input Pull-up 264TEST1None Input Pull-up 265TMS None Input Pull-up266RTCK 8 mA Output 67TCK None Input 68TDI None Input Pull-up269TDO 4 mA Output 70LINREGEN None Input 571nRESETOUT8 mA Output 372PD6INT6DREQ 6 mA Bidirectional Pull-down173PD5INT5DACK 6 mA Bidirectional 1, 274PD4INT4UARTRX18 mA BidirectionalPull-up 175VDDC Power None 76PD3INT3UARTTX18 mA Bidirectional Pull-up 177PD2INT2 2 mA Bidirectional Pull-up178PD1INT1 6 mA Bidirectional 1, 279PD0INT02 mA Bidirectional180VSSCGroundNoneTable 2.LH75401 Numerical Pin List (Cont’d)PIN NO.FUNCTION AT RESETFUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPE BEHAVIOR DURINGRESETNOTES 元器件交易网LH75401/LH75411System-on-Chip8Rev. 01— 16 July 2007Preliminary data sheetNXP Semiconductors81nPOR None Input Pull-up2, 382XTAL32IN None Input 483XTAL32OUT None Output84VSSA_PLL Ground None 85VDDA_PLL PowerNone 86XTALIN None Input 487XTALOUT None Output88VSSA_ADC Ground None 89AN3 (LR/Y-)PJ7None Input 90AN4 (Wiper)PJ6None Input 91AN9PJ5None Input 92AN2 (LL/Y+)PJ4None Input 93AN8PJ3None Input 94AN1 (UR/X-)PJ2None Input 95AN6PJ1None Input 96AN0 (UL/X+)PJ0None Input 97VDDA_ADCPower None 98VDD Power None 99PE7SSPFRM 4 mA Bidirectional Pull-up 1100PE6SSPCLK 4 mA Bidirectional Pull-down 1101PE5SSPRX 4 mA Bidirectional Pull-up 1102PE4SSPTX 4 mA Bidirectional Pull-down 1103PE3CANTX UARTTX08 mA Bidirectional Pull-up 1104PE2CANRX UARTRX02 mA Bidirectional Pull-up 1105PE1UARTTX24 mA BidirectionalPull-up1106VSS GroundNone 107PE0UARTRX2 4 mA Bidirectional Pull-up1108PF6CTCAP2B CTCMP2B 4 mA Bidirectional 2109PF5CTCAP2A CTCMP2A 4 mA Bidirectional 110PF4CTCAP1B CACMP1B 4 mA Bidirectional 2111PF3CTCAP1ACTCMP1A4 mA Bidirectional112VDD PowerNone 113PF2CTCAP0E 4 mA Bidirectional 2114PF1CTCAP0D 4 mA Bidirectional 115PF0CTCAP0C 4 mA Bidirectional 2116PG7CTCAP0B CTCMP0B 4 mA Bidirectional 117PG6CTCAP0A CTCMP0A4 mA Bidirectional 2118PG5CTCLK4 mA Bidirectional119VSS GroundNone 120PG4LCDVEEEN LCDMOD8 mA Bidirectional 121PG3LCDVDDEN 8 mA Bidirectional 122PG2LCDDSPLENLCDREV 8 mABidirectional Table 2.LH75401 Numerical Pin List (Cont’d)PIN NO.FUNCTION AT RESET FUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPE BEHAVIOR DURINGRESETNOTES 元器件交易网System-on-ChipLH75401/LH75411Preliminary data sheet Rev. 01 — 16 July 2007 9NXP SemiconductorsNOTES:1.Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.2.CMOS Schmitt trigger input.3.Signals preceded with ‘n’ are active LOW.4.Crystal Oscillator Inputs should be driven to 1.8 V ±10% (MAX.)5.LINREGEN activation requires a 0 Ω pull-up to VDD.123PG1LCDCLS 8 mA Bidirectional 124PG0LCDPS 8 mA Bidirectional 125PH7LCDDCLK8 mABidirectional126VDD Power None 127VSS GroundNone 128PH6LCDLP LCDHRLP 8 mA Bidirectional 129PH5LCDFP LCDSPS 8 mA Bidirectional 130PH4LCDEN LCDSPL8 mA Bidirectional 131PH3LCDVD118 mA Bidirectional 132PH2LCDVD108 mA Bidirectional 133PH1LCDVD98 mABidirectional 134VDD PowerNone 135PH0LCDVD88 mA Bidirectional 136PI7LCDVD78 mA Bidirectional 137PI6LCDVD68 mA Bidirectional 138PI5LCDVD58 mA Bidirectional 139PI4LCDVD48 mABidirectional 140VSS GroundNone 141PI3LCDVD38 mA Bidirectional 142PI2LCDVD28 mA Bidirectional 143PI1LCDVD18 mA Bidirectional 144PI0LCDVD08 mABidirectionalTable 2.LH75401 Numerical Pin List (Cont’d)PIN NO.FUNCTION AT RESETFUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPE BEHAVIOR DURINGRESETNOTESLH75401/LH75411System-on-Chip10Rev. 01 — 16 July 2007Preliminary data sheetNXP SemiconductorsLH75401 Signal DescriptionsTable 3.LH75401 Signal DescriptionsPIN NO.SIGNAL NAMETYPEDESCRIPTIONNOTESMEMORY INTERFACE (MI)1245679101213151618192021D[15:0]Input/Output Data Input/Output Signals 122nWE Output Static Memory Controller Write Enable 223nOE Output Static Memory Controller Output Enable 224nWAIT Input Static Memory Controller External Wait Control 1, 225nBLE1Output Static Memory Controller Byte Lane Strobe 1, 227nBLE0Output Static Memory Controller Byte Lane Strobe 1, 228nCS3Output Static Memory Controller Chip Select 1, 229nCS2Output Static Memory Controller Chip Select 1, 230nCS1Output Static Memory Controller Chip Select 1, 231nCS0OutputStatic Memory Controller Chip Select23233 35363738394043444546474950515253555657586061A[23:0]Output Address Signals 1DMA CONTROLLER (DMAC)72DREQ Input DMA Request 173DACKOutputDMA Acknowledge1PIN NO.SIGNAL NAME TYPE DESCRIPTION NOTESCOLOR LCD CONTROLLER (CLCDC)120LCDMOD Output Signal Used by the Row Driver (AD-TFT, HR-TFT only)1 120LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal)1 121LCDVDDEN Output Digital Supply Enable1 122LCDDSPLEN Output LCD Panel Power Enable1 122LCDREV Output Reverse Signal (AD-TFT, HR-TFT only)1 123LCDCLS Output Clock to the Row Drivers (AD-TFT, HR-TFT only)1 124LCDPS Output Power Save (AD-TFT, HR-TFT only)1 125LCDDCLK Output LCD Panel Clock1 128LCDLP Output Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT)1 128LCDHRLP Output Latch Pulse (AD-TFT, HR-TFT only)1 129LCDFP Output Frame Pulse (STN), Vertical Synchronization Pulse (TFT)1 129LCDSPS Output Row Driver Counter Reset Signal (AD-TFT, HR-TFT only)1 130LCDEN Output LCD Data Enable1 130LCDSPL Output Start Pulse Left (AD-TFT, HR-TFT only)1 131132133135136137LCDVD[11:0]Output LCD Panel Data bus1 138139141142143144SYNCHRONOUS SERIAL PORT (SSP)99SSPFRM Output SSP Serial Frame1 100SSPCLK Output SSP Clock1 101SSPRX Input SSP RXD1 102SSPTX Output SSP TXD1UART0 (U0)103UARTTX0Output UART0 Transmitted Serial Data Output1 104UARTRX0Input UART0 Received Serial Data Input1UART1 (U1)74UARTRX1Input UART1 Received Serial Data Input1 76UARTTX1Output UART1 Transmitted Serial Data Output1UART2 (U2)105UARTTX2Output UART2 Transmitted Serial Data Output1 107UARTRX2Input UART2 Received Serial Data Input1CONTROLLER AREA NETWORK (CAN)103CANTX Output CAN Transmitted Serial Data Output1 104CANRX Input CAN Received Serial Data Input1ANALOG-TO-DIGITAL CONVERTER (ADC)89 90 91 92 93 94 95 96AN3 (LR/Y-)AN4 (Wiper)AN9AN2 (LL/Y+)AN8AN1 (UR/X-)AN6AN0 (UL/X+)Input ADC Inputs1TIMER 0117116115114113CTCAP0[A:E]Input Timer 0 Capture Inputs1117116CTCMP0[A:B]Output Timer 0 Compare Outputs1 118CTCLK Input Common External Clock1TIMER 1111110CTCAP1[A:B]Input Timer 1 Capture Inputs1 111110CTCMP1[A:B]Output Timer 1 Compare Outputs1 118CTCLK Input Common External Clock1TIMER 2109108CTCAP2[A:B]Input Timer 2 Capture Inputs1 109108CTCMP2[A:B]Input Timer 2 Compare Outputs1 118CTCLK Input Common External Clock1GENERAL PURPOSE INPUT/OUTPUT (GPIO)1 2 4 5 6 7 9 10PA7PA6PA5PA4PA3PA2PA1PA0Input/Output General Purpose I/O Signals - Port A124 25 27 28 29 30PB5PB4PB3PB2PB1PB0Input/Output General Purpose I/O Signals - Port B132 33 35 36 37 38 39 40PC7PC6PC5PC4PC3PC2PC1PC0Input/Output General Purpose I/O Signals - Port C1PIN NO.SIGNAL NAME TYPE DESCRIPTION NOTES72 73 74 76 77 78 79PD6PD5PD4PD3PD2PD1PD0Input/Output General Purpose I/O Signals - Port D189 90 91 92 93 94 95 96PJ7PJ6PJ5PJ4PJ3PJ2PJ1PJ0Input General Purpose I/O Signals - Port J199 100 101 102 103 104 105 107PE7PE6PE5PE4PE3PE2PE1PE0Input/Output General Purpose I/O Signals - Port E1108 109 110 111 113 114 115PF6PF5PF4PF3PF2PF1PF0Input/Output General Purpose I/O Signals - Port F1116 117 118 120 121 122 123 124PG7PG6PG5PG4PG3PG2PG1PG0Input/Output General Purpose I/O Signals - Port G1125 128 129 130 131 132 133 135PH7PH6PH5PH4PH3PH2PH1PH0Input/Output General Purpose I/O Signals - Port H1136 137 138 139 141 142 143 144PI7PI6PI5PI4PI3PI2PI1PI0Input/Output General Purpose I/O Signals - Port I1 RESET, CLOCK, AND POWER CONTROLLER (RCPC)62nRESETIN Input User Reset Input2 71nRESETOUT Output System Reset Output2 72INT6Input External Interrupt Input 61 PIN NO.SIGNAL NAME TYPE DESCRIPTION NOTESNOTES:1.These pin numbers have multiplexed functions.2.Signals preceded with ‘n’ are active LOW.73INT5Input External Interrupt Input 5174INT4Input External Interrupt Input 4176INT3Input External Interrupt Input 3177INT2Input External Interrupt Input 2178INT1Input External Interrupt Input 1179INT0Input External Interrupt Input 0181nPOR Input Power-on Reset Input282XTAL32IN Input 32.768 kHz Crystal Clock Input 83XTAL32OUT Output 32.768 kHz Crystal Clock Output 86XTALIN Input Crystal Clock Input 87XTALOUT Output Crystal Clock OutputTEST INTERFACE63TEST2Input Test Mode Pin 264TEST1Input Test Mode Pin 165TMS Input JTAG Test Mode Select Input 66RTCK Output Returned JTAG Test Clock Output 67TCK Input JTAG Test Clock Input 68TDI Input JTAG Test Serial Data Input 69TDOOutputJTAG Test Data Serial OutputPOWER AND GROUND (GND)31734425498112126134VDD Power I/O Ring VDD826414859106119127140VSS Power I/O Ring VSS1175VDDC Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input)1480VSSC Power Core VSS70LINREGEN Input Linear Regulator Enable 84VSSA_PLL Power PLL Analog VSS 85VDDA_PLL Power PLL Analog VDD Supply 88VSSA_ADC Power A-to-D converter Analog VSS 97VDDA_ADCPowerA-to-D converter Analog VDD SupplyPIN NO.SIGNAL NAME TYPE DESCRIPTIONNOTESLH75411 Numerical Pin ListingTable 4.LH75411 Numerical Pin ListPIN NO.FUNCTIONAT RESETFUNCTION2FUNCTION3FUNCTIONTYPEOUTPUTDRIVEBUFFERTYPEBEHAVIOR DURINGRESET NOTES1PA7D15I/O8 mA Bidirectional Pull-up1 2PA6D14I/O8 mA Bidirectional Pull-up1 3VDD Power None4PA5D13I/O8 mA Bidirectional Pull-up1 5PA4D12I/O8 mA Bidirectional Pull-up1 6PA3D11I/O8 mA Bidirectional Pull-up1 7PA2D10I/O8 mA Bidirectional Pull-up1 8VSS Ground None9PA1D9I/O8 mA Bidirectional Pull-up1 10PA0D8I/O8 mA Bidirectional Pull-up1 11VDDC Power None12D7I/O8 mA Bidirectional Pull-up13D6I/O8 mA Bidirectional Pull-up14VSSC Ground None15D5I/O8 mA Bidirectional Pull-up16D4I/O8 mA Bidirectional Pull-up17VDD Power None18D3I/O8 mA Bidirectional Pull-up19D2I/O8 mA Bidirectional Pull-up20D1I/O8 mA Bidirectional Pull-up21D0I/O8 mA Bidirectional Pull-up22nWE8 mA Output HIGH3 23nOE8 mA Output HIGH3 24PB5nWAIT8 mA Bidirectional Pull-up1, 3 25PB4nBLE18 mA Bidirectional Pull-up1, 3 26VSS Ground None27PB3nBLE08 mA Bidirectional Pull-up1, 3 28PB2nCS38 mA Bidirectional Pull-up1, 3 29PB1nCS28 mA Bidirectional Pull-up1, 3 30PB0nCS18 mA Bidirectional Pull-up1, 3 31nCS08 mA Output Pull-up3 32PC7A238 mA Bidirectional Pull-down1 33PC6A228 mA Bidirectional Pull-down1 34VDD Power None35PC5A218 mA Bidirectional Pull-down1 36PC4A208 mA Bidirectional Pull-down1 37PC3A198 mA Bidirectional Pull-down1 38PC2A188 mA Bidirectional Pull-down1 39PC1A178 mA Bidirectional Pull-down1 40PC0A168 mA Bidirectional Pull-down1 41VSS Ground None42VDD PowerNone 43A158 mA Output LOW 44A148 mA Output LOW 45A138 mA Output LOW 46A128 mA Output LOW 47A118 mA OutputLOW48VSS GroundNone 49A108 mA Output LOW 50A98 mA Output LOW 51A88 mA Output LOW 52A78 mA Output LOW 53A68 mA OutputLOW54VDD Power None 55A58 mA Output LOW 56A48 mA Output LOW 57A38 mA Output LOW 58A28 mA OutputLOW59VSS Ground None 60A18 mA Output LOW 61A08 mA Output LOW 62nRESETIN None Input Pull-up 2, 363TEST2None Input Pull-up 264TEST1None Input Pull-up 265TMS None Input Pull-up266RTCK 8 mA Output 67TCK None Input 68TDI None Input Pull-up269TDO 4 mA Output 70LINREGEN None Input 571nRESETOUT8 mA Output 372PD6INT6DREQ 6 mA Bidirectional Pull-down173PD5INT5DACK 6 mA Bidirectional 1, 274PD4INT4UARTRX18 mA BidirectionalPull-up 175VDDC Power None 76PD3INT3UARTTX18 mA Bidirectional Pull-up 177PD2INT2 2 mA Bidirectional Pull-up178PD1INT1 6 mA Bidirectional 1, 279PD0INT02 mA Bidirectional180VSSC GroundNone 81nPOR None Input Pull-up2, 382XTAL32IN None Input 483XTAL32OUTNoneOutputPIN NO.FUNCTION AT RESETFUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPEBEHAVIOR DURINGRESETNOTES84VSSA_PLL Ground None 85VDDA_PLL PowerNone 86XTALIN None Input 487XTALOUT None Output88VSSA_ADC GroundNone 89AN3 (LR/Y-)PJ7None Input 90AN4 (Wiper)PJ6None Input 91AN9PJ5None Input 92AN2 (LL/Y+)PJ4None Input 93AN8PJ3None Input 94AN1 (UR/X-)PJ2None Input 95AN6PJ1None Input 96AN0 (UL/X+)PJ0None Input 97VDDA_ADCPower None 98VDD Power None 99PE7SSPFRM 4 mA Bidirectional Pull-up 1100PE6SSPCLK 4 mA Bidirectional Pull-down 1101PE5SSPRX 4 mA Bidirectional Pull-up 1102PE4SSPTX 4 mA Bidirectional Pull-down 1103PE3UARTTX08 mA Bidirectional Pull-up 1104PE2UARTRX0 2 mA Bidirectional Pull-up 1105PE1UARTTX24 mA BidirectionalPull-up1106VSS GroundNone 107PE0UARTRX2 4 mA Bidirectional Pull-up1108PF6CTCAP2B CTCMP2B 4 mA Bidirectional 2109PF5CTCAP2A CTCMP2A 4 mA Bidirectional 110PF4CTCAP1B CACMP1B 4 mA Bidirectional 2111PF3CTCAP1ACTCMP1A4 mA Bidirectional112VDD PowerNone 113PF2CTCAP0E 4 mA Bidirectional 2114PF1CTCAP0D 4 mA Bidirectional 115PF0CTCAP0C 4 mA Bidirectional 2116PG7CTCAP0B CTCMP0B 4 mA Bidirectional 117PG6CTCAP0A CTCMP0A4 mA Bidirectional 2118PG5CTCLK4 mA Bidirectional119VSS GroundNone 120PG4LCDVEEEN LCDMOD8 mA Bidirectional 121PG3LCDVDDEN 8 mA Bidirectional 122PG2LCDDSPLEN LCDREV 8 mA Bidirectional 123PG1LCDCLS 8 mA Bidirectional 124PG0LCDPS 8 mA Bidirectional 125PH7LCDDCLK8 mABidirectional PIN NO.FUNCTION AT RESET FUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPEBEHAVIOR DURINGRESETNOTESNOTES:1.Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral.2.CMOS Schmitt trigger input.3.Signals preceded with ‘n’ are active LOW.4.Crystal Oscillator Inputs should be driven to 1.8 V ±10% (MAX.)5.LINREGEN activation requires a 0 Ω pull-up to VDD.126VDD Power None 127VSS GroundNone 128PH6LCDLP LCDHRLP 8 mA Bidirectional 129PH5LCDFP LCDSPS 8 mA Bidirectional 130PH4LCDEN LCDSPL8 mA Bidirectional 131PH3LCDVD118 mA Bidirectional 132PH2LCDVD108 mA Bidirectional 133PH1LCDVD98 mABidirectional 134VDD PowerNone 135PH0LCDVD88 mA Bidirectional 136PI7LCDVD78 mA Bidirectional 137PI6LCDVD68 mA Bidirectional 138PI5LCDVD58 mA Bidirectional 139PI4LCDVD48 mABidirectional 140VSS GroundNone 141PI3LCDVD38 mA Bidirectional 142PI2LCDVD28 mA Bidirectional 143PI1LCDVD18 mA Bidirectional 144PI0LCDVD08 mABidirectionalPIN NO.FUNCTION AT RESETFUNCTION2FUNCTION 3FUNCTION TYPE OUTPUTDRIVEBUFFERTYPE BEHAVIOR DURINGRESETNOTESLH75411 Signal DescriptionsTable 5.LH75411 Signal DescriptionsPIN NO.SIGNAL NAME TYPE DESCRIPTION NOTESMEMORY INTERFACE (MI)124567910D[15:0]Input/Output Data Input/Output Signals1 121315161819202122nWE Output Static Memory Controller Write Enable2 23nOE Output Static Memory Controller Output Enable2 24nWAIT Input Static Memory Controller External Wait Control1, 2 25nBLE1Output Static Memory Controller Byte Lane Strobe1, 2 27nBLE0Output Static Memory Controller Byte Lane Strobe1, 2 28nCS3Output Static Memory Controller Chip Select1, 2 29nCS2Output Static Memory Controller Chip Select1, 2 30nCS1Output Static Memory Controller Chip Select1, 2 31nCS0Output Static Memory Controller Chip Select2 323335363738394043444546A[23:0]Output Address Signals1 474950515253555657586061DMA CONTROLLER (DMAC)72DREQ Input DMA Request1 73DACK Output DMA Acknowledge1COLOR LCD CONTROLLER (CLCDC)120LCDMOD Output Signal Used by the Row Driver (AD-TFT, HR-TFT only)1 120LCDVEEEN Output Analog Supply Enable (AC Bias SIgnal)1 121LCDVDDEN Output Digital Supply Enable1 122LCDDSPLEN Output LCD Panel Power Enable1 122LCDREV Output Reverse Signal (AD-TFT, HR-TFT only)1 123LCDCLS Output Clock to the Row Drivers (AD-TFT, HR-TFT only)1 124LCDPS Output Power Save (AD-TFT, HR-TFT only)1 125LCDDCLK Output LCD Panel Clock1 128LCDLP Output Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT)1 128LCDHRLP Output Latch Pulse (AD-TFT, HR-TFT only)1 129LCDFP Output Frame Pulse (STN), Vertical Synchronization Pulse (TFT)1 129LCDSPS Output Row Driver Counter Reset Signal (AD-TFT, HR-TFT only)1 130LCDEN Output LCD Data Enable1 130LCDSPL Output Start Pulse Left (AD-TFT, HR-TFT only)1 131132133135136137138139141142143144LCDVD[11:0]Output LCD Panel Data bus1SYNCHRONOUS SERIAL PORT (SSP)99SSPFRM Output SSP Serial Frame1 100SSPCLK Output SSP Clock1 101SSPRX Input SSP RXD1 102SSPTX Output SSP TXD1UART0 (U0)104UARTRX0Input UART0 Received Serial Data Input1 103UARTTX0Output UART0 Transmitted Serial Data Output1UART1 (U1)74UARTRX1Input UART1 Received Serial Data Input1 76UARTTX1Output UART1 Transmitted Serial Data Output1UART2 (U2)105UARTTX2Output UART2 Transmitted Serial Data Output1 107UARTRX2Input UART2 Received Serial Data Input1ANALOG-TO-DIGITAL CONVERTER (ADC)89 90 91 92 93 94 95 96AN3 (LR/Y-)AN4 (Wiper)AN9AN2 (LL/Y+)AN8AN1 (UR/X-)AN6AN0 (UL/X+)Input ADC Inputs1Table 5.LH75411 Signal Descriptions (Cont’d)PIN NO.SIGNAL NAME TYPE DESCRIPTION NOTESTIMER 0117116115114113CTCAP0[A:E]Input Timer 0 Capture Inputs1117116CTCMP0[A:B]Output Timer 0 Compare Outputs1 118CTCLK Input Common External Clock1TIMER 1111110CTCAP1[A:B]Input Timer 1 Capture Inputs1 111110CTCMP1[A:B]Output Timer 1 Compare Outputs1 118CTCLK Input Common External Clock1TIMER 2109108CTCAP2[A:B]Input Timer 2 Capture Inputs1 109108CTCMP2[A:B]Input Timer 2 Compare Outputs1 118CTCLK Input Common External Clock1GENERAL PURPOSE INPUT/OUTPUT (GPIO)1 2 4 5 6 7 9 10PA7PA6PA5PA4PA3PA2PA1PA0Input/Output General Purpose I/O Signals - Port A124 25 27 28 29 30PB5PB4PB3PB2PB1PB0Input/Output General Purpose I/O Signals - Port B132 33 35 36 37 38 39 40PC7PC6PC5PC4PC3PC2PC1PC0Input/Output General Purpose I/O Signals - Port C172 73 74 76 77 78 79PD6PD5PD4PD3PD2PD1PD0Input/Output General Purpose I/O Signals - Port D1PIN NO.SIGNAL NAME TYPE DESCRIPTION NOTES89 90 91 92 93 94 95 96PJ7PJ6PJ5PJ4PJ3PJ2PJ1PJ0Input General Purpose I/O Signals - Port J199 100 101 102 103 104 105 107PE7PE6PE5PE4PE3PE2PE1PE0Input/Output General Purpose I/O Signals - Port E1108 109 110 111 113 114 115PF6PF5PF4PF3PF2PF1PF0Input/Output General Purpose I/O Signals - Port F1116 117 118 120 121 122 123 124PG7PG6PG5PG4PG3PG2PG1PG0Input/Output General Purpose I/O Signals - Port G1125 128 129 130 131 132 133 135PH7PH6PH5PH4PH3PH2PH1PH0Input/Output General Purpose I/O Signals - Port H1136 137 138 139 141 142 143 144PI7PI6PI5PI4PI3PI2PI1PI0Input/Output General Purpose I/O Signals - Port I1 RESET, CLOCK, AND POWER CONTROLLER (RCPC)62nRESETIN Input User Reset Input2 71nRESETOUT Output System Reset Output2 72INT6Input External Interrupt Input 61 73INT5Input External Interrupt Input 51 74INT4Input External Interrupt Input 41 76INT3Input External Interrupt Input 31 77INT2Input External Interrupt Input 21 78INT1Input External Interrupt Input 11 79INT0Input External Interrupt Input 01 PIN NO.SIGNAL NAME TYPE DESCRIPTION NOTESNOTES:1.These pin numbers have multiplexed functions.2.Signals preceded with ‘n’ are active LOW.81nPOR Input Power-on Reset Input282XTAL32IN Input 32.768 kHz Crystal Clock Input 83XTAL32OUT Output 32.768 kHz Crystal Clock Output 86XTALIN Input Crystal Clock Input 87XTALOUT Output Crystal Clock OutputTEST INTERFACE63TEST2Input Test Mode Pin 264TEST1Input Test Mode Pin 165TMS Input JTAG Test Mode Select Input 66RTCK Output Returned JTAG Test Clock Output 67TCK Input JTAG Test Clock Input 68TDI Input JTAG Test Serial Data Input 69TDOOutputJTAG Test Data Serial OutputPOWER AND GROUND (GND)31734425498112126134VDD Power I/O Ring VDD826414859106119127140VSS Power I/O Ring VSS1175VDDC Power Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input)1480VSSC Power Core VSS70LINREGEN Input Linear Regulator Enable 84VSSA_PLL Power PLL Analog VSS 85VDDA_PLL Power PLL Analog VDD Supply 88VSSA_ADC Power A-to-D converter Analog VSS 97VDDA_ADCPowerA-to-D converter Analog VDD SupplyPIN NO.SIGNAL NAME TYPE DESCRIPTIONNOTESFUNCTIONAL OVERVIEWARM7TDMI-S ProcessorThe LH75401/LH75411 microcontrollers feature the ARM7TDMI-S core with an Advanced High-Performance Bus (AHB) 2.0 interface. The ARM7TDMI-S is a 16/32-bit embedded RISC processor and a member of the ARM7 Thumb family of processors. For more information, visit the ARM Web site at .Bus ArchitectureThe LH75401/LH75411 microcontrollers use the ARM Advanced Microcontroller Bus Architecture (AMBA) 2.0 internal bus protocol. Three AHB masters control access to external memory and on-chip peripherals:•The ARM processor fetches instructions and trans-fers data•The Direct Memory Access Controller (DMAC) trans-fers from memory to memory, from peripheral to memory, and from memory to peripheral•The LCDC refreshes an LCD panel with data from the external memory or from internal memory if the frame buffer is 16kB or less.The ARM7TDMI-S processor is the default bus mas-ter. An Advanced Peripheral Bus (APB) bridge is pro-vided to access to the various APB peripherals. Generally, APB peripherals are serviced by the ARM core. However, if they are DMA-enabled, they are also serviced by the DMAC to increase system performance while the ARM core runs from local internal memory.Power SuppliesFive-Volt-tolerant 3.3 V I/Os are employed. The LH75401/LH75411 microcontrollers require a single 3.3V supply. The core logic requires 1.8 V, supplied by an on-chip linear regulator. Core logic power may also be supplied externally to achieve higher system speeds. See the Electrical Specifications.Clock SourcesThe LH75401/LH75411 microcontrollers may use two crystal oscillators, or an externally supplied clock. There are two clock trees:•One clock tree drives an internal Phase Lock Loop (PLL) and the three UARTs. It supports a crystal oscillator frequency range from 14 MHz to 20 MHz. •The other is a 32.768 kHz oscillator that generates a 1Hz clock for the RTC. (Use of the 32.768 kHz crys-tal for the Real Time Clock is optional. If not using the crystal, tie XTAL32IN to VSS and allow XTAL32OUT to float.)The 14-to-20 MHz crystal oscillator drives the UART clocks, so an oscillator frequency of 14.7456 MHz is rec-ommended to achieve modem baud rates.The PLL may be bypassed and an external clock supplied at XTALIN; the SoC will operate to DC with the PLL disabled. When doing so, allow XTALOUT to float. The input clock with the PLL bypassed will be twice the desired system operating frequency, and care must be taken not to exceed the maximum input clock voltage. Maximum values for system speeds and input voltages are given in the Electrical Specifications.Figure 4.LH75401 System Application Example。

TDA8920BJ DBS23P plastic DIL-bent-SIL power package; 23 leads (straight lead length 3.2 mm)
Version SOT566-3
SOT411-1
9397 750 13356
Preliminary data sheet
9397 750 13356
Preliminary data sheet
Rev. 01 — 1 October 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
3 of 34
Philips Semiconductors
2 × 100 W class-D power amplifier
4. Quick reference data
Table 1: Quick refere
Conditions
General; VP = ±27 V
VP
supply voltage
Iq(tot)
total quiescent supply current
no load; no filter; no RC-snubber network connected
Stereo single-ended configuration
Po
output power RL = 3 Ω; THD = 10 %; VP = ±27 V
DRIVER LOW
TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION
TDA8920BTH (TDA8920BJ)