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Multipath Execution on Chip Multiprocessors Enabled by Redundant Threads

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Multipath Execution on Chip Multiprocessors Enabled by Redundant ThreadsOctober 23, 20011Multipath Execution on Chip MultiprocessorsEnabled by Redundant Threads

Technical Report CESR-TR-01-2Karthik Sundaramoorthy, Zach Purser, Eric RotenbergCenter for Embedded System Research (CESR)Department of Electrical and Computer EngineeringNorth Carolina State University{ksundar,zrpurser,ericro}@ece.ncsu.edu

AbstractTheperformancepenaltyofmispredictedbranchescanbereducedbyfetching/executingbothpathsofunconfidentbranches.Executingbothpathsofabranchinvolvesforkinganewthreadcontextforthenon-predictedpath.Akeyrequirementistheabilitytoquicklycopyregisterandmemorystate,sothatnewthreadsareinitiatedquickly.Mostmultipatharchitecturesarebuiltontopofsimultaneousmultithreading(SMT),becauseasharedregisterfileandcacheenablesnewthreadstoinheritstatewithoutanyactualdatamovement.Multipathexecutiononchipmulti-processors(CMP)islargelyunexploredbecauseper-threadregisterfilesandlevel-1cachesarephysically separated, making it difficult to quickly copy state.Redundantexecutionisproposedasanenablingmechanismfordual-pathexecutiononaCMPwithtwoprocessingelements(PEs).Byalwaysexecutingtwoprograms,redundantstateismaintainedcontinuouslyinpreparationforforking.Thethreadsredundantlyandindependentlyidentifyunconfidentbranchesandexplorealternativepaths.Whenanunconfidentbranchresolves,oneofthethreadsfallsbehind.Thisisremediedbypassingcontrolflowanddataflowoutcomesfromtheleadingthreadtothelaggingthread.Theseareconsumedasidealbranch/valuepredictions,enablingthelaggingthreadtocatchup,ideallybeforethenextunconfidentbranch.Bybeingpro-activeinsteadofreactive,redundantexecutiondoesnotexhibitasmuchoverheadason-demand state copying.Acompletelydistributed,CMP-basedsolutionwillgenerallyunderperformSMT-basedsolu-tions,yetperformanceimprovementsashighas12%aremeasured.Latencyforcommunicatingpredictions between PEs affects performance significantly, but realistic latencies are tolerable.Multipath Execution on Chip Multiprocessors Enabled by Redundant ThreadsOctober 23, 20012

1. IntroductionMultipathexecutionisatechniqueforreducingtheperformancepenaltyofmispredictedbranches[1,4,8,17,18,19].Aconfidencemechanismdeterminesthelikelihoodthatbranchpredic-tionsarecorrect[5].Ifconfidenceinapredictionislow,amultipathprocessorwillfetchandexe-cutebothpathsfollowingthebranch.Aswithconventionalspeculation,thepredictedpathissquashedifthepredictionwasincorrect.Themispredictionpenaltyisreduced,however,becausepart of the correct path is already processed by the time the misprediction is detected.Multipathexecutiontypicallyrequiressupportforquicklyforkingnewregistercontexts.Simultaneousmultithreadedprocessors(SMT)[16,21]areidealbecausetheyprovidemultipleregistercontextsinasharedregisterfile,managedbyper-threadregistermaptables.Thepre-dictedpathispartofthecurrentthreadandusesthecurrentmaptable.Anewthreadisforkedforthenon-predictedpath,usingthemaptableofafreecontext.Initially,thenewthreadmustinheritregisterstateuptothepointofthebranch.Withasharedregisterfile,inheritingregisterstatedoesnotrequirecopyingregistervalues,onlypointerstothevalues.So,forkingonlyrequiresallocat-inganewmaptableandcopyingcurrentmappingstothenewmaptable.Furthermore,single-cycle copying of map tables is already supported for branch checkpointing (e.g., shadow maps).Thispaperproposesamethodforlimitedmultipathexecutiononchipmultiprocessors(CMP).ACMPhasmultiplethreadcontexts,too,buttheyaredistributedamongprocessingele-ments(PEs)[10].EachPEhasaprivateregisterfileandlevel-1(L1)cache.Physicallyseparatedregisterfilesandcachesmakeitdifficulttoquicklyforkstate.Whenanunconfidentbranchpre-dictionisencountered,thecontentsoftheactiveregisterfilehavetobecopiedtotheregisterfileofafreePE.Copyingisslow,partlybecauseofthedistancebetweenregisterfiles,butmainlybecauseoflimitedbandwidthintoandoutoftheregisterfiles.ForkingmemorystaterequiresasharingmechanismamongdistributedL1caches.Inanycase,theoverheadforcopyingstateissohigh that the non-predicted path may not even begin executing before the branch is resolved.Fortunately,thereisanalternativetocopyingstate.TheprogramcanbeexecutedredundantlyonmultiplePEs.ThisapproachmaintainsredundantcopiesofregisterfilesandL1cachescontin-uously.Inthispaper,multipathexecutionislimitedtotwopaths,sotwocopiesoftheprogramareexecutedredundantlyontwoPEs.Insteady-state,thePEsfetch/executenearlyinlock-stepandtheirstatematchesclosely.Becausetheirstatematches,thePEsarepreparedformultipathexecu-tion ahead of time, and forking is unnecessary.ThetwoPEsredundantlypredictbranchinstructionsandsimultaneouslyestimateconfi-dence.Whenanunconfidentpredictionisencountered,oneofthePEsfollowsthenot-takenpathandtheotherfollowsthetakenpath.WhenthebranchresolvesinbothPEs,thePEthatfollowedthecorrectpathcontinues,whiletheotherPEsquasheswrong-pathinstructionsandre-directsinstruction fetching to the correct path.Atthispoint,thethreadthatfollowedtheincorrectpathlagsbehindtheotherthread.Theleadingthreadpassesallofitscontrolflowanddataflowoutcomestothelaggingthreadviaacommunicationqueue.Outcomesareconsumedbythelaggingthreadasalways-correctbranchandvalue“predictions”[13,15].Assistingthelaggingthreadenablesittocatchupwiththelead-ing thread, materializing some of the performance potential of multipath execution.Communicatingpredictionsseemsequivalenttostatecopying.Whatevertheinterpretation,redundantexecutionassistedbypredictionsismoreeffectivethanon-demandcopying.On-demandcopyingisreactiveandincursahighlatencytostartthenon-predictedpath.Thepro-activeapproachofpassingpredictionstoalaggingthreadeventuallyre-synchronizesthethreads,often before multipath execution is needed again.

合集下载

USB3.0设计资源 cypress芯片程序解读

USB3.0设计资源 cypress芯片程序解读

CYPEESS USB3.0程序解读解读同步FIFO的一个例子。

生产者，消费者首先看DMA的回调函数：typedef void (*CyU3PDmaCallback_t) (CyU3PDmaChannel *handle, /* Handle to the DMA channel. */CyU3PDmaCbType_t type, /* The type of callback notification being generated. */ CyU3PDmaCBInput_t*input /* Union that contains data related to the notification. The input parameter will be a pointer to a CyU3PDmaBuffer_t variable in the cases where the callback type isCY_U3P_DMA_CB_RECV_CPLT or CY_U3P_DMA_CB_PROD_EVENT. */);根据其说明，解读如下：1．对每一个DMA通道，回调函数必须被注册。

如果没有注册或者相应的通知事件没有被注册，则回调函数不会被执行。

2．回调函数不能被阻塞。

即不能用SLEEP（）之类的函数。

如果数据需要处理，必须在回调函数之外。

3．在生产者事件中，应用希望尽可能快地处理输入的数据。

如果缓冲的处理不能在规定的时间内完成，则输入的可能是陈旧的数据。

在自动信号通道中，输入参量指向最新的数据。

如果处理延时，生产者socket可能复盖部分数据。

4．在手动或手动IN通道模式时，输入参量指向第一个缓冲(用于去消费者socket).如果在第二次调用时，这个缓冲仍没有被处理，输入参量中将是被陈旧的数据。

如果数据处理必须在通道中做，CyU3PDmaChannelGetBuffer函数必须被应用，而回调函数必须作为一个通知。

启用eexecute disable bit -回复

启用eexecute disable bit -回复

启用eexecute disable bit -回复什么是执行禁用位（Execute Disable Bit，EDB）？执行禁用位（Execute Disable Bit）是一种硬件技术，旨在提高计算机的安全性和防止恶意软件的攻击。

通过启用EDB功能，计算机的中央处理器（CPU）可以标记某些内存区域，防止恶意代码或病毒从这些区域执行。

为什么需要启用执行禁用位？在许多传统计算机系统中，内存的执行属性是可配置的，这意味着恶意软件可以利用这个漏洞来执行代码，从而对计算机进行攻击。

通过启用执行禁用位，可以将内存执行属性设置为只读或不可执行，从而大大降低恶意软件的攻击风险。

如何启用执行禁用位？启用执行禁用位需要满足以下两个基本条件：1. 支持EDB的CPU：确保计算机的CPU支持执行禁用位技术。

大部分现代的CPU都支持EDB功能，例如英特尔的Pentium 4、Core 2、以及更高版本的处理器，以及AMD的Athlon 64、Opteron和Phenom处理器。

2. 操作系统的支持：确保您的操作系统支持执行禁用位。

大部分现代操作系统，包括Windows 7、Windows 8、Windows 10以及各种Linux发行版，都对EDB提供了支持。

一旦您确认了CPU和操作系统的支持，就可以按照以下步骤启用执行禁用位：1. 进入BIOS设置：重新启动计算机，在开机时按下设定键（通常是Delete 键、F2键或F10键）进入BIOS设置界面。

2. 寻找EDB选项：在BIOS设置界面中，使用方向键导航至“Security”或“Advanced”（可能也称为“CPU”、“Processor”或“System Configuration”）选项。

在这个选项下，您应该能找到一个与执行禁用位相关的设置选项。

具体名称和位置可能会根据不同的BIOS版本而有所不同，请查阅您的计算机或主板的用户手册获取更多信息。

3. 启用EDB：找到所需的设置选项后，将其修改为“Enable”（启用）或类似的选项。

netfilter_conntrack流程详解

netfilter_conntrack流程详解


1
Intel Nehalem
A Research Report
Contents
1 Introduction 1.1 Motivation for this Study . . . . . . . . . . . . . . . . . . 1.2 Overview of Features in the Intel Core Micro-Architecture 1.3 Summary of New Features in the Intel Micro-Architecture The “Intel R 64” Architecture The 3.1 3.2 3.3 Nehalem Processor Instruction and Data Flow in Modern Processors . . . . Overview of the Nehalem Processor Chip . . . . . . . . Nehalem Core Pipeline . . . . . . . . . . . . . . . . . . 3.3.1 Instruction and Data Flow in Nehalem Cores . . 3.3.2 Nehalem Core: Front-End Pipeline . . . . . . . . 3.3.3 Nehalem Core: Out-of-Order Execution Engine . 3.3.4 Execution pipelines of a Nehalem core . . . . . . 3.3.5 Nehalem Core: Load and Store Operations . . . Intel SSE Instructions . . . . . . . . . . . . . . . . . . . 3.4.1 Floating-Point SIMD operations in Nehalem core 3.4.2 Floating-Point Registers in Nehalem core . . . . Floating-Point Processing and Exception Handling . . . Intel Simultaneous Multi-Threading . . . . . . . . . . . 3.6.1 Basic SMT Principles . . . . . . . . . . . . . . . 3.6.2 SMT in Nehalem cores . . . . . . . . . . . . . . 3.6.3 Resource Sharing in SMT . . . . . . . . . . . . . CISC and RISC Processors . . . . . . . . . . . . . . . . 1 2 2 3
freescale kinetis解锁方法

freescale kinetis解锁方法

FreescaleKinetis解锁方法
当使用J-FLASH下载时，显示以下信息：
* JLink Info: Found SWD-DP with ID 0x2BA01477
***JLink Error: Kinetis (connect): Timeout while halting CPU. CPU does not stop.
Error: Flash Erase failed - Target DLL has been cancelled
提示对话框“No Cortex-M SW Device Found”
且JLINK已经没法连接，有可能芯片因操作不当已锁住。

此时可尝试以下方法进行解锁：
1. 接好JLINK，尤其是RESET引脚不要忘了接（一些廉价的4脚的JLINK ARMOB版本没有RESET引脚，不行）
2. 调试到提示有0x2BA01477 的状态。

3. 打开一个Jlink Commander, 输入unlock Kinetis.
4. 如果不奏效，尝试如下：按住RESET，然后电脑上输入unlock Kinetis, 之后再大约0.3 - 0.5S后松开RESET。

因为这个时间和你上一次的程序有关系，又是你手动控制的，需要多试几次（可能需要1-50次左右才能成功，看你运气了）。

root cause 先不跟你说了，和JLINK的RESET引脚驱动能力有关系。

（本人在使用MKV11Z128XXX时，因在KEIL5中不小心选错CPU型号，并执行了DOWN LOAD操作，结果芯片上锁，尝试多种方法，后使用以上方法终于解锁成功！）。