ENT-AN1165Application Note VSC8575/VSC8582/VSC8584 Migration Design GuideMay 2016Contents1Revision History (1)1.1Revision 2.2 (1)1.2Revision 2.1 (1)1.3Revision 2.0 (1)1.4Revision 1.1 (1)1.5Revision 1.0 (1)2Migrating from VSC8574 Family Devices (2)2.1Optional MDIO Voltage Supply Change (3)2.2Pin Changes (3)2.3Family Features not in the VSC8584 Family (4)2.3.11588 Register Access (4)2.3.2RGMII (VSC8552/VSC8572 only) (5)3New Features in the VSC8584 Family (6)3.1Additional IEEE 1588v2 Features (6)3.2MACsec Features (all except VSC8575) (6)3.3Daisy-chained SPI Time Stamping Interface (6)3.4New SPI I/O for Register Access (7)3.5Other Features (8)3.61588 Register Differences (8)3.7MACsec Register Differences (8)3.8Packaging (8)3.9Power Requirements (8)4Design Recommendations (9)4.1API Software (9)4.2Power Considerations (9)4.3Errata Considerations (9)4.4SPI I/O Management Interface (9)4.5Time Stamp Format (10)1Revision HistoryThe revision history describes the changes that were implemented in the document. The changes arelisted by revision, starting with the most current publication.1.1Revision2.2Pin ChangesPHYADD1 pin details were clarified. For more information, see .SPI I/O register access functionality was added. For more information, see New SPI I/O for RegisterAccess.MACsec and 1588 register differences were added. For more information, see 1588 RegisterDifferences MACsec Register Differencesand .1.2Revision2.1In revision 2.1 of this document, 1588_SPI_CLK functionality was clarified. For more information, see Pin .Changes1.3Revision2.0In revision 2.0 of this document, details about the F13 pin were added. For more information, see PinChanges.1.4Revision 1.1There were no changes to the technical content in revision 1.1 of this document.1.5Revision 1.0Revision 1.0 was the first release of this document.2Migrating from VSC8574 Family DevicesThis document highlights issues to consider when migrating from the VSC8574 family of devices(VSC8504, VSC8552, VSC8572, and VSC8574) to the VSC8584 family of devices (VSC8575, VSC8582, andVSC8584). Changes to pins, registers, and other features are listed, along with design recommendations.Customers migrating systems from revision C or earlier of the VSC8574 family of devices should refer toeither the "VSC8572/VSC8574 Transition Design Guide" or the "VSC8504/VSC8552 Transition DesignGuide,” for additional considerations.The following figure shows the block diagram for the superset device within the VSC8574 family.Figure 1 • VSC8574 Block DiagramThe following figure shows the block diagram for the superset devices within the VSC8584 family thatincludes a new MACsec engine and dual MACs with flow control buffers to handle bandwidth expansionduring packet processing.Figure 2 • VSC8584 Block Diagram2.1Optional MDIO Voltage Supply ChangeExcept for designs that require 1.2 V operation on the MDC/MDIO interface, the VSC8584 family isvoltage compatible with the VSC8574 family by utilizing the same two primary voltage rails (1.0 V and2.5 V). For VSC8584 family operation that uses 1.2 V on the MDC/MDIO interface, the design requiressupplying 1.2 V as well.2.2Pin ChangesThe VSC8584 family is backward pin-compatible with revision D of the VSC8574 family (such asVSC8574XKS-01 and VSC8574XKS-04) for all VSC8574 family functions except RGMII functionality for thedual-port PHY. The RGMII interface is not included in the VSC8582 dual-port device.Any changes between the families to optional pins are related to new functionalities associated withenhanced SPI I/O support, alternative SPI time stamping daisy-chaining, 1588_PPS_RI pin access, PHYaddress offset of 0x2 for VSC8582, and the VDD change for supporting 1.2 V MDC/MDIO operation.Table 1These pin differences are summarized in . In other words, VSC8584 may be populated in anexisting VSC8574 design, but the new SPI and MDC/MDIO 1.2 V mode will not be available in thatconfiguration.VSC8574 family designs that accepted revision B or revision C devices and made use of the truncatedtime stamp erratum that used a workaround to reconfigure the SPI bus to use the 1588_PPS_0 pin asSPI_CLK (1588_SPI_CLK) must revert to the intended pin functions. This erratum was fixed in theVSC8574 family revision D devices, but the ability to use either pin was left in the revision D design fortransition purposes. This flexibility is not offered in the VSC8584 family of devices, thus 1588_SPI_CLK isonly available on the 1588_SPI_CLK pin in VSC8584 family devices.The following table details the differences in pins between the VSC8574 and VSC8584 families.Table 1 • VSC8574 and VSC8584 Family Pin DifferencesVSC8574 Family Pin Name VSC8584 Family Pin Name Pin LocationP3VDD25_4VDD_MDIO (1.2 V/2.5 V depending uponMDIO interface voltage level)VSS_721588_PPS_RI [VSC8582/VSC8584/VSC8575E14only]VSC8574 Family Pin Name VSC8584 Family Pin NamePin Location 1588_PPS_1 [VSC8572/VSC8574 only]1588_PPS_1 [VSC8582/VSC8584/VSC8575 only] (or 1588_SPI_IN_CLK for SPI daisy-chain feature)N31588_PPS_2 [VSC8572/VSC8574 only]1588_PPS_2 [VSC8582/VSC8584/VSC8575 only] (or 1588_SPI_IN_CS for SPI daisy-chain feature)N41588_PPS_3 [VSC8572/VSC8574 only]1588_PPS_3 [VSC8582/VSC8584/VSC8575 only] (or 1588_SPI_IN_DI for SPI daisy-chain feature)L2VSS_74SPI_IO_D0F15VSS_75SPI_IO_DI G15VSS_76SPI_IO_CLK H15VSS_78SPI_IO_CS J13VSS_73/RGMII0_TXD1PHYADD1F13Pin F13, named VSS_73 in the VSC8574 family quad-port devices and RGMII0_TXD1 in the VSC8574 family dual-port devices, is used as PHYADD1 in the VSC8584 family devices, which have a weak internal PU. Therefore, quad-port designs from the VSC8574 family must connect this pin to VSS to support forward compatibility with the VSC8584 family. For VSC8582 dual-port design, it can be pulled up if an address offset of 0x2 is desired.The following table described the pins used in the VSC8584 family.Table 2 • VSC8584 Pin DescriptionsVSC8584 Pin Name Pin Location DescriptionType VDD_MDIO P3VDD Power supply (1.2 V or 2.5 V)I 1588_PPS_RI E141588_PSS_RI inputI 1588_PPS_1(1588_SPI_IN_CLK)N31588 SPI clock or 1588_PPS_1I/O 1588_PPS_2 (1588_SPI_IN_CS)N41588 SPI input or 1588_PPS_2I/O 1588_PPS_3 (1588_SPI_IN_DI)L21588 SPI data input or 1588_PPS_3I/O SPI_IO_D0F15SPI data output, for register accessO SPI_IO_DI G15SPI data input for register accessI SPI_IO_CLK H15SPI clock for register access I SPI_IO_CS J13SPI select for register access I PHYADD1F13Normally tied to VSS unless an addr offset of 0x2is desired for 2 port designI2.3Family Features not in the VSC8584 Family2.3.11588 Register AccessBroadcast writes to the two 1588 engines are supported.An RGMII interface is not included in the VSC8582 dual-port design.3New Features in the VSC8584 FamilyThe following sections contain features new to the VSC8584 family of devices that were not included inthe VSC8574 family.3.1Additional IEEE 1588v2 FeaturesThe VSC8582 and VSC8584 devices include additional 1588v2 features, as follows:Improved accuracy for ingress and egress (the family offers accuracy options better than 10 nS PDV)Separate bypass bits for egress and ingress pathsGeneral PBB support supporting four encapsulations across three encapsulation enginesMPLS-TP OAM support in the third encapsulation engineETH1 comparator bypass for time stamping all packetsFull 48-bit arithmetic to time stampImproved resolution of local time counter (LTC) load with programmable offset registerAuto-clear load/save signal for more deterministic software writes to LTCAlong with pulse per second, which occurs only every second, the LTC block can output a clockbased on LTC timer. Duty cycle is programmable to enable use of the synthesis pulse to synchronizetwo different devices that are out of sync.Ability to serially load/read ToD informationImproved time-precision for PPS output including external cable delay measurement for PPSInterrupt when data in reserved fieldAdditional loopback modes for various 1588 pinsIP frame signature offset width to address any bytes of IPv6IEEE 1588v2 through MACsec supportAbility to store frame signature from all the engines3.2MACsec Features (all except VSC8575)MACsec and VLAN header parsingFully IEEE 802.1AE-2006 compliant, supporting GCM-AES-128Updated for IEEE 802.1AEbn-2011, supporting GCM-AES-256Fixed latency for accurate 1588 time stamp supportSupports full-duplex operation at all speedsPatent-pending architecture to allow use with 1588 with minimal and predictable delaysIncludes host and line MACs and Flow-Control (FC) buffers around 1588 and MACsec blocks to allowfor bandwidth expansion due to MACsec operation inserting SecTAG and ICV16 SAs per port with and without confidentiality offset per-SAPause reaction time met with 1588 when integrated MACs are enabled3.3Daisy-chained SPI Time Stamping InterfaceThis new feature enables designers to reduce the number of pins required to transmit egress timestamping information from multiple VSC8584 family devices on a PCB board to system ASICs gathering1588 time stamps.In this mode, the device captures TS frames on the 1588_SPI_IN signals and arbitrates with the internal1588 SPI outputs for the chip SPI output, and outputs the frames.The following figure shows a high-level block diagram of the SPI daisy-chain logic.Figure 3 • Daisy-chained SPI Connectivity for Time StampsEach device output behaves as a SPI master and the input behaves as a SPI slave. The SPI bus can daisy-chain up to eight devices and is specified to operate up to 62.5 MHz.The following table shows the SPI bus utilization.Table 3 • Example SPI Bus UtilizationFrequency (of daisy-chained SPI bus)Maximum Time stamps per Second perPort in chain of 32 PortsTheoretical Maximum SPI bus Utilization31.25 MHz256 5.69%31.25 MHz160.71%3.4New SPI I/O for Register AccessThe VSC8584 family adds a new optional/additional management interface, SPI slave for register accessto handle both IEEE 1588 and MACsec communication to the device. The device targets a 25 MHz SPIoperating rate. The 22-bit address (SI_ADDR) is composed of a 2-bit reserved field that must be set to'00', an 8-bit Target ID, and a 12-bit register address. This register address represents a word addresswhere a word is 32 bits. The SPI data is 32 bits and is consistent with the SI_ADDR mapping. The deviceuses one slave select (SS) per slave for a simple slave design and shares SCLK, MOSI and MISO signals.The following figure shows the described signal sharing.Figure 4 • SPI Connectivity for Register AccessRefer to the appropriate VSC8584 family datasheet for information on how to access 1588 and MACsecRefer to the appropriate VSC8584 family datasheet for information on how to access 1588 and MACsecregisters through the new SPI slave interface.Note:This interface cannot be used to access basic PHY registers and SerDes registers.3.5Other FeaturesAutonomous Far End Fault Indication (FEFI) generation and detection due to either LOS/LOCS, or underregister control1.2 V MDIO/MDC support for Clause 45 MDIO electrical supportNote: This feature does not support direct Clause 45 register access because the registers are stillaccessed through the Clause 22 method.Full Rx/Tx packet checkers for both MAC and media (copper and fiber) paths3.61588 Register DifferencesIn the VSC8574 family, the broadcast write control (Register 22.0) allowed 1588 register writes to bebroadcast to both internal 1588 engines, enabling simultaneous writing of settings for ports 0/2 and 1/3.This is no longer possible due to the use of a shared register access mechanism for all 1588 and MACsecregisters.Software teams should review the auto-clear load/save signal for more deterministic software writes toLTC. To clarify, the VSC8584 family can be configured to write to the LTC using the same approach asthe VSC8574 family.As with the VSC8574 family, use of the Microsemi software API is required to implement 1588functionality (rather than using direct register level access).3.7MACsec Register DifferencesThe MACsec functionality is a new addition in the VSC8584 family, except for the VSC8575 device. Dueto the proprietary nature of the MACsec feature as well as its complexity, Microsemi requires the use ofthe Microsemi software API to implement MACsec functionality rather than using direct register levelaccess.3.8PackagingThe VSC8584 family uses a similar package as the VSC8574 family. Refer to the VSC8574 familydatasheet for packaging details.The following table shows package thermal resistances for the VSC8584 family.Table 4 • VSC8584 Thermal ResistancesSymbol o C/W ParameterθJCtop 5.1Die junction to package case topθJB10.5Die junction to printed circuit boardθJA19.6Die junction to ambientθJMA at 1 m/s15.2Die junction to moving air measured atan air speed of 1 m/sθJMA at 2 m/s14.2Die junction to moving air measured atan air speed of 2 m/s3.9Power RequirementsThe maximum power consumption for VSC8584 (with the IEEE 1588 and MACsec functionalities enabledwith full 1000BASE-T traffic) is estimated to be 3.68 W. This is approximately 1.15 W more than thequad-port VSC8574. For customers running a different operating mode, budget an extra 1.15 Wmaximum power for VSC8584 family operation relative to VSC8574 family operation when using theMACsec feature and 1588 feature. The additional power is mainly due to the additional leakage currenton VDD1 (core) supply with the addition of MACsec circuit.4Design RecommendationsThe following sections provide recommendations for designs moving from the VSC8574 family to theVSC8584 family of devices.4.1API SoftwareDesigns using the VSC8584 family require Microsemi's API with support for the VSC8584 family.Beginning with version 4.3, Microsemi’s Unified API includes initialization scripts required by theVSC8584 family. Due to the proprietary nature of the IEEE 1588v2 and MACcsec features (as well astheir complexity), Microsemi requires the use of the Microsemi software API to implement IEEE 1588v2and MACsec functionalities rather than direct register level access.Microsemi may introduce improved initialization scripts in the future and recommends that customersuse the latest production version of the API in their applications.4.2Power ConsiderationsSystem designers must evaluate the impact of higher VSC8584 family power consumption on systemPackaging Power Requirementsthermal performance. For more information, see and .4.3Errata ConsiderationsThe VSC8574 family errata may not apply to the VSC8584 family devices.The errata for VSC8584 family devices have been incorporated into the Design Considerations of thedatasheets.4.4SPI I/O Management InterfaceDepending on the application requirements and the number of supported slaves, use of the SPI I/Omanagement interface is recommended to avoid throughput issues on MDIO bus. The SPI I/O interfacecan operate up to 25 MHz with 32 bits wide data field to improve the interface throughput.The following figure shows the format for SPI I/O Write.Figure 5 • SPI I/O Write FormatThe following figure shows the format for SPI I/O Read.Figure 6 • SPI I/O Read Format4.5Time Stamp FormatThe SPI Time Stamp format for the VSC8584 family is the same as for the VSC8574 family.The following figure shows the format for clock polarity and phase.Figure 7 • SPI Time Stamp FormatMicrosemi HeadquartersOne Enterprise, Aliso Viejo,CA 92656 USAWithin the USA: +1 (800) 713-4113Outside the USA: +1 (949) 380-6100Sales: +1 (949) 380-6136Fax: +1 (949) 215-4996Email:***************************© 2016 Microsemi. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice.Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at www. .VPPD-03043。
