简易中文规格书LT768x_BFDS_V23_CH

Chapter 2: XPHY Architecture Figure 2: Relationship Between a Single XPHY Nibble, XP IOL, and IOBX21592-042319The following figure shows an XPHY NIBBLESLICE.Figure 3: XPHY NIBBLESLICE with TX and RX DatapathsTristateControlLogicBidirectionalPinXPHY NIBBLESLICE Data fromProgrammableLogic Data toProgrammableLogic X21593-121219TX DatapathThe TX datapath is composed of the following:•Serializer: The serializer supports 8:1, 4:1, and 2:1 serialization. This is set by theTX_DATA_WIDTH attribute.•Output Delay: Output delays can delay outgoing serialized data up to 512 taps (0–511 taps),with a minimum of 625 ps of available delay.Refer to the Controlling Tristate Control section for latencies with and without the TX datapath using tristate control.Related InformationControlling DelaysControlling Tristate ControlRX DatapathThe RX datapath is composed of:•Input delay: Input delays can delay incoming serialized data up to 512 taps (0–511 taps), witha minimum of 625 ps of available delay. Input delays can be increased to 1024 taps (0–1023taps) for a minimum of 1250 ps of available delay by cascading the output delay of an XPHY NIBBLESLICE to the end of its input delay. For more information on cascading, see theCASCADE_<0–5> attribute.•Deserializer: The deserializer supports 1:8, 1:4, and 1:2 deserialization. This is determined by the RX_DATA_WIDTH attribute.•FIFO: The receiver of an XPHY NIBBLESLICE has an 8-deep FIFO. The parallel data written to the FIFO is synchronized to the programmable logic clock domain of choice before passing to the programmable logic.RX datapath latency changes depending on the data width (RX_DATA_WIDTH) andFIFO_MODE_x attribute. Refer to Controlling FIFO Modes for RX datapath latencies.IMPORTANT! Because each NIBBLESLICE routes to a specific pin, receiving a differential signal(regardless of whether clock or data) consumes the pins and RX datapaths of both NIBBLESLICEs.IMPORTANT! If receiving a strobe and RX_GATING = ENABLE, bitslip is not needed. For all other cases,bitslip is needed for word alignment.Related InformationFIFOBidirectional DatapathThe TX and RX datapaths within each XPHY NIBBLESLICE can be used together to form a bidirectional datapath. As shown in Figure 3, each TX datapath drives both to the pad and the RX datapath. As such, care must be taken when using the bidirectional datapath so as to tristate the buffer or gate the datapaths without data loss.The XPHY offers transmit gating, receive gating, and tristating as mechanisms to control the bidirectional datapath. See the table below for a summary of how to enable these controls through the XPHY attributes.。

Chapter 4: Designing with the SubsystemRS-FEC Functional DescriptionThe RS-FEC feature of the 10G/25G Subsystem provides error correction capability according to IEEE 802.3 Clause 108 or Schedule 3 of the 25G Ethernet Consortium.The feature requires the insertion of PCS alignment markers as defined in IEEE 802.3 Table 82-2. Inputs are provided for the alignment markers and also for the value of words between alignment markers.It is possible to bypass the RS-FEC function by means of the enable signals. This will bypass the RS-FEC function and connect the PCS directly to the transceiver, with the benefit of reduced latency. Refer to 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registration required) for the latest latency performance data in the various bypass modes, defined as follows:•FEC Bypass Correction: The decoder performs error detection without correction, (see IEEE Std 802.3by section 108.5.3.2. The latency is reduced in this mode (see 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registrationrequired) for latency figures).Additionally, you can optionally generate a 64-bit standalone version of the MAC for 10 Gb/s operation. The block diagram is shown in the following figure.Figure 4: 64-bit Standalone Version of the MAC for 10 Gb/s OperationAXI4-Streaming AXI4-StreamingClocks and Resets XGMII RX XGMII TX X20136-120417StandardsThe 10G/25G Ethernet Subsystem is designed to the standard specified in the 25G and 50G Ethernet Consortium and the IEEE Std 802.3.Performance and Resource UtilizationFor full details about performance and resource utilization, visit the Performance and Resource Utilization web page .Chapter 3: Product SpecificationChapter 3: Product SpecificationCONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008CTable 82: CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008CBits Default Type Signal31:00RW ctl_tx_sa_ppp[31:0]CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090Table 83: CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090Bits Default Type Signal15:00RW ctl_tx_sa_ppp[47:32]CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094Table 84: CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094Bits Default Type Signal8:00RW ctl_rx_pause_enable90RW ctl_rx_forward_control100RW ctl_rx_enable_gcp110RW ctl_rx_enable_pcp120RW ctl_rx_enable_gpp130RW ctl_rx_enable_ppp140RW ctl_rx_check_ackCONFIGURATION_RX_FLOW_CONTROL_REG2: 0098Table 85: CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098Bits Default Type Signal00RW ctl_rx_check_mcast_gcp10RW ctl_rx_check_ucast_gcp20RW ctl_rx_check_sa_gcp30RW ctl_rx_check_etype_gcp40RW ctl_rx_check_opcode_gcp50RW ctl_rx_check_mcast_pcp60RW ctl_rx_check_ucast_pcp70RW ctl_rx_check_sa_pcp80RW ctl_rx_check_etype_pcp90RW ctl_rx_check_opcode_pcp100RW ctl_rx_check_mcast_gpp。

Table 65: GTY Transceiver Dynamic Reconfiguration Port (DRP) Switching CharacteristicsSymbol Description All Speed Grades Units F GTYDRPCLK GTYDRPCLK maximum frequency250MHzTable 66: GTY Transceiver Reference Clock Switching CharacteristicsSymbol Description ConditionsAll Speed GradesUnits Min Typ MaxF GCLK Reference clock frequency range60–820MHzT RCLK Reference clock rise time20% – 80%–200–psT FCLK Reference clock fall time80% – 20%–200–psT DCREF Reference clock duty cycle Transceiver PLL only405060%Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching CharacteristicsDS922 (v1.17) February 16, 2021Product SpecificationTable 67: GTY Transceiver Reference Clock Oscillator Selection Phase Noise MaskSymbol Description1, 2OffsetFrequency Min Typ Max UnitsQPLL REFCLKMASK QPLL0/QPLL1 reference clock select phase noisemask at REFCLK frequency = 156.25 MHz 10 kHz–––112dBc/Hz 100 kHz–––1281 MHz–––145QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz–––103dBc/Hz 100 kHz–––1231 MHz–––143QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz–––98dBc/Hz 100 kHz–––1171 MHz–––140CPLL REFCLKMASK CPLL reference clock select phase noise mask atREFCLK frequency = 156.25 MHz 10 kHz–––112dBc/Hz 100 kHz–––1281 MHz–––14550 MHz–––145CPLL reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz–––103dBc/Hz 100 kHz–––1231 MHz–––14350 MHz–––145CPLL reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz–––98dBc/Hz 100 kHz–––1171 MHz–––14050 MHz–––144Notes:1.For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.2.This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol,e.g., PCIe.Table 68: GTY Transceiver PLL/Lock Time AdaptationSymbol Description ConditionsAll Speed GradesUnits Min Typ MaxT LOCK Initial PLL lock.––1msT DLOCK Clock recovery phase acquisition andadaptation time for decision feedbackequalizer (DFE)After the PLL is locked to thereference clock, this is thetime it takes to lock the clockdata recovery (CDR) to thedata present at the input.–50,00037 x 106UIClock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled –50,000 2.3 x 106UIKintex UltraScale+ FPGAs Data Sheet: DC and AC Switching CharacteristicsDS922 (v1.17) February 16, 2021Product Specification。

'---------[Program begins here.]----------------------------------------------PAUSE 3000 FOR i = 1 TO 5 Counter(LEFT) = 0 DO WHILE (Counter(LEFT) < 50) PULSOUT MotorL, 850 PULSOUT MotorR, 650 GOSUB Update PAUSE 20 LOOP PAUSE 500 Counter(RIGHT) = 0 DO WHILE (Counter(RIGHT) < 20) PULSOUT MotorR, 650 GOSUB Update PAUSE 20 LOOP PAUSE 500 NEXT END 'Time to remove finger from reset button... 'Initialize LEFT counter. 'Pulse the servos to go straight 'by 50 pulse edges (about 25"). 'Update the encoder counts. '20 ms pulse gap. 'Wait 1/2 second before turn. 'Initialize RIGHT counter. 'Pulse the RIGHT servo to turn a 40% circle. 'Update the encoder counts. '20 ms pulse gap. 'Wait 1/2 second before next side.
5
2 ea. #4-40 x 1/4" Panhead Machine Screw 2 ea. #4-40 Hex Nut 2 ea. 10K 1/4W Resistor