A Note on Export Subsidies and Exchange RateBenan Zeki Orbay*, Hakan Orbay**AbstractThis note investigates effects of exchange rate uncertainty on optimal trade policies and market prices within a standard export subsidy model. As exchange rate changes, relative efficiencies of firms in different countries change. In accordance with the conventional result, we show that changes in expected exchange rate effects optimal subsidies through relative costs. In particular, increase in expected depreciation of own currency increases subsidy levels when marginal cost is constant. Introducing import dependency, however, violates this uniform relation, and subsidy levels may decrease with increasing depreciation. Subsidy levels always decrease in import dependency when depreciation is expected. We also show that market price is less sensitive to exchange rates, compared to the free trade case (no subsidies).JEL Classifications: F12Key Words: Subsidies, exchange rate uncertainty, cost asymmetry, demand asymmetry.* Istanbul Technical University, Department of Management Engineering, Macka, 80680, Istanbul, e-mail:*************.tr**SabanciUniversity,Orhanli,34956,Istanbul,e-mail:**********************1.IntroductionThis note introduces exchange rate uncertainty into a standard export subsidy model. While optimal trade intervention policies have been analyzed under various market structures in the existing international trade literature, effects of exchange rates on optimal policies and resulting market structures have not been considered.Starting from leading studies of Brander and Spencer (1985) and Eaton and Grossman (1986) in the area, many studies focused on the models analyzing trade and trade policies in countries with oligopolistic markets. The main result of this line of literature is that the optimal trade policies heavily depend on the market structure. Focusing on export subsidies, Meza (1986) and Neary (1994) showed that when subsidies are the optimal policies they should be higher for the more efficient firms. In other words, governments should subsidize the winners more. On the other hand, Bandyopadhyay (1997) found that demand elasticity is also a major determinant of the subsidy level and this result can be reversed for the inelastic demand case. Later, Bandyopadhyay et al. (2004) determined that the optimal subsidy level is higher with higher level of cost heterogeneity. There are various other papers looking at the trade policy issues under uncertainty on either demand or cost sides1. The results again vary depending on the environment modeled.In this paper, we aim to fill a gap by investigating effects of exchange rate uncertainty on optimal subsidy policies and relative price levels with cost and demand asymmetries. Consider a two-country environment, referred to as domestic and foreign, where one firm is located in each country and these firms compete in both countries. In our model, governments set subsidy policies before observing the actual exchange rate, but taking into account its expected value, e. Firms compete after exchange rate is realized.With constant marginal costs, we find that the optimal subsidy level of domestic country increases and foreign developed country decreases with e, where exchange is measured in domestic currency per foreign currency. This result is in accordance with conventional results of the existing literature which states that higher cost firms gets less subsidy, as higher e corresponds to a lower relative cost for the domestic1 For example, see Cooper and Riezman (1989), Qui (1994), Shikumavar (1993), Maggi (1996), Brainard and Martimort (1997), Caglayan and Usman (2004).country’s firm. However, when import dependency for the domestic firm is considered, where the marginal cost may partially depend on exchange rate, subsidy level could go either way as expected exchange rate increases. Subsidy level is always decreasing in the import dependency parameter if currency value depreciation is expected.We show that higher cost firm may receive a higher subsidy in equilibrium, which is reminiscent of Bandyopadhyay (1994)’s result . We also show that domestic market price may be decreasing in exchange rate, if intensity of subsidy by the foreign government is high. Otherwise, sensitivity of market price to exchange rate is less compared to the free trade (no subsidy) regime.2. The ModelConsider a two-country world, where there is one firm in each country. Following the literature, one of these countries is a developing country and the other is a developed one. The developing country is referred to as domestic country (d ) and the other as foreign country (f ). Both domestic and foreign firms produce the same good, which is sold in both countries, however, domestic firm has higher costs due to inferior technology.We consider a two stage game. In the first stage, governments choose subsidy levels, facing exchange rate uncertainty. In the second stage, exchange rate is realized and firms enter a Cournot competition in both domestic and foreign markets.Let e~ denote the exchange rate in the second stage of the game, representing value of unit foreign currency in domestic currency. In the first stage, probabilitydistribution of e~ is known, and expected exchange rate is denoted by e . For discussion purposes, assume that actual exchange rate in the first stage is 1; hence expected devaluation of domestic currency is represented by 1e .Linear demand functions are assumed for both developing and developed countries as follows,f d j q q Q Q b a p j j j j j j j ,,,21 (1)where d p and f p are domestic and foreign market prices in each country’s own currency. We refer to the firm residing in the domestic country as firm 1, and the other as firm 2. Thus, 1d q and 1f q denote quantities sold by the domestic firm indomestic and foreign markets, respectively. We assume constant marginal costs for both firms,2,1,,)(i q q q q c q C fi di i i i i i . (2) Following the developing country theme, we will assume that domestic firm remains inefficient even with expected devaluation, or e c c 21.Under these assumptions for both supply and demand sides, the profit functions of domestic and foreign firms can be written as follows;22222221111111)( )( d f f d f f d d f d f d f f d d q s q q c q p e q p πq s q q c q p e q p π (3)where d s and f s are thesubsidies given bythe domestic and foreign countries respectively, and e is the realization of the exchange rate in stage 2. Note that both profit functions are given in own currencies.Social welfare in each country is given by the sum of consumer surplus and the profit of its firm net of subsidy transfers,2211CS SW CS SW d f f f f d d dq s q s (4)In the first stage, governments set the subsidy level that maximizes expected social welfare in stage 2.3. Exchange Rate and Subsidy LevelsSolving the last stage of the game, we obtain Cournot-Nash equilibrium quantity levels as follows:,3~)(2,3~)(2212211d f d d d f d d b e s c c a q b e s c c a q e b s c e c a q e b s c e c a q fd f f f d f f ~3~)2(~322~)(122121 (5) In the first stage, governments maximize expected social welfare. We note that derivative of social welfare functions with respect to subsidy levels are as follows,,9~)42(and ,9~)42(2112d f d f f f f d f ddb e sc c a sd W S d be s c c a s d W Sd (6) where ee f ~/1~is the exchange rate expressed in foreign currency per domestic currency. Therefore, the first order conditions 0SW E j j ds d yield, 42)(12c e c a s f d and ee c c a s df 4221. (7) as the optimal subsidy levels. In order obtain (7), one needs to assume congruence of expected values of the two versions of the exchange rate, i.e., e e f/1, which iscertainly suggested by common sense.We now turn to the effects of exchange rate expectations on subsidy levels. The following proposition immediately follows from (7).Proposition 1. The subsidy level of the domestic country increases and that of the foreign country decreases as expected exchange rate, e , increases. Intuitively, export subsidies increase welfare through grabbing welfare from the foreign country. Potential welfare to be grabbed increases as the foreign market gets larger, or own firm becomes more efficient. Thus, subsidy levels intensify as the size of the foreign market increases and marginal cost of own firm decreases. The latter is the conventional result in this literature that the higher cost firm gets lower subsidy. From the perspective of the domestic country, devaluation of domestic currency makes both the foreign market relatively larger (f a e ), and the domestic firm relatively more efficient as its cost is given by e c /1in local currency at the foreign market. Consequently, subsidy level of the domestic country increases as expected exchange rate increases. The argument for the foreign country is symmetric.It is, however, unrealistic to assume that marginal cost of the domestic firm remains constant while domestic currency depreciates. We will therefore extend the model to include possible dependency of the marginal cost to exchange rate sensitivity. In order to avoid confusion, let us re-label domestic firm’s marginal cost as d c , and assume that11)1(~c αc e αc d . (8) Here, ]1,0[α represents the fraction of the cost that is procured from world markets, and can be thought as import dependency of the domestic firm. Remainder of the cost (α1) does not depend exchange rates hence represents local inputs such as labor.Setting 0α obtains the original model. Also, let 11)1(c c e c d be the expected value of d c .With this assumption, as exchange rate increases, marginal cost of the domestic firm increases in local currency, and decreases in foreign currency. The countervailing effect may invalidate Proposition 1 as stated in the next proposition. Note that, the new assumption does not affect maximization problems 2. In particular,(7) still holds with d c substituted for 1c . Proposition 2. If 212c a c f and 122c c a αf , then domestic country’s subsidy leveld s is decreasing ine . Otherwise, d s is increasing in e but its sensitivity is lesscompared to the case with 0α. Proof. Note that 4/)2(12c αc a e d s d f d, from which the proposition follows.If depreciation of domestic currency is expected, increasing α makes domestic firm less efficient in either currency. Therefore, it is expected that subsidy level decreases in α.Proposition 3. Domestic country’s subsidy level is decreasing (increasing) in α if domestic currency is expected to depreciate (appreciate).Proof. Follows from 2/)1(1e c αd s d d.It is clear that subsidy levels are decreasing in respective firms’ marginal costs. However, high cost (domestic) firm may end up receiving a higher subsidy is foreign market sufficiently large, or expected devaluation is sufficiently high.Proposition 4. d d f f d c a c a e s s 3)3( iff 22 Note that first derivatives of social welfare functions given in (6) are still linear in exchange rate.It is interesting to note that optimal subsidy level may exceed marginal cost even in the standard model if the marginal cost is sufficiently low. In this model, over- (under-) subsidy occurs if the exchange rate realization is lower (higher) than the expected rate. Thus, low realizations of exchange may also cause subsidy level to exceed marginal cost. Algebraic manipulation of d d c s yields the following result. Proposition 5. Domestic country’s subsidy exceeds marginal cost of domestic firm if(i)0and 6)(21ca ec f , or (ii) 0and 212)1(3412e c c a e e fProof is omitted.4. Effects of Subsidies and Exchange Rates on Relative Prices In this section, we investigate comparative statics of market prices in both countries. Equilibrium prices are as follows 3,3)()(3)(122d f f f d d ds c c a e p s c e c a p (9)where d s and f s are given in (7), and e is again the realized exchange rate. Let f d p pˆ and ˆdenote free-trade prices, which can be obtained by setting both subsidies to zero above.As exchange rate increases, marginal cost of foreign firm in the domestic market increases. Therefore, under free trade, domestic market price increases with exchange rate. Thisrelationship can reverse with intense subsidies as shown in the next proposition.Proposition 6. Domestic market price is decreasing in e iff 12c c s f . When domestic price is increasing, its sensitivity to the exchange rate is less compared to the free trade case.3 Both prices are stated in domestic currency unit.Proof. Since f s is independent of the realized exchange rate, we have )(3121f ds c c ed p d . Under free trade, we have )(31ˆ21c c e d p d d . Since0f s , ed p de d p d d d ˆ. When foreign subsidy level exceeds 2c , foreign firms effective marginal cost is negative. Hence, increasing exchange rate decreases effective marginal cost, resultingin a decrease of the market price. With 0, an increase in exchange rate also increases domestic firm’s marginal cost, forcing prices upwards. A large enough foreign subsidy overcomes this additional effect.For completeness, we state the corresponding result for foreign market price. Proposition 7. Foreign market price, measured in domestic currency, is always increasing in e . Furthermore, its sensitivity to the exchange rate is same under both free trade and subsidy regime.The asymmetry between domestic and foreign prices is purely an artifact of currency translation. When translated to domestic currency, subsidy of the domestic firm becomes independent of exchange rate, hence derivatives are identical whether there is subsidy or not.5. Concluding RemarksIntroducing exchange rate uncertainty in an export subsidy model, this note essentially recasts some of the earlier results. Consider conventional finding that optimal subsidy levels depend on relative costs and foreign market size. Since movements in exchange rate changes relative costs of a firm in the foreign market as well as relative size of the foreign market, both of these relationships can be translated to a relationship with exchange rates. In this sense, comparative statics of subsidy levels and exchange rates are not surprising. Introduction of exchange rates leads to some new results, such as inverse relationship of subsidy levels with import dependency of own firm and reduced exchange rate sensitivity of market prices under subsidy regime. Hopefully, this modeling innovation will open research possibilities.ReferencesBandyopadhyay, S., 1997, “Demand Elasticities, asymmetry and Strategic Trade Policy”, Journal of International Economics,42, 167-177. Bandyopadhyay, S, Park, Eun-Soo and Wall, H. J., 2004, “Endogeneous Export Subsidies and Welfare under Domestic Cost Heterogeneity”Economics and Politics, 16, No:3, 347-366.Brainard, S.L. and Martimort D., 1997, “Strategic Tr ade Policy with Incompletely Informed Policymakers” Journal of International Economics, 42, 33-65. Brander, J.A. and Spencer, B. J., 1985, “Export Subsidies and International Market Rivalry” Journal of International Economics, 31, 83-100.Caglayan, M. and Usman, M., 2004, “Incompletely Informed Policymakers and Trade Policy in Oligopolistic Industries”, The Manchester School, 72, 3, 283-297. Cooper, R. and Riezman, R., 1989, “ Uncertainty, and Choice of Trade Policy in Oligopolistic Industries” Review of Ec onomic Studies, 56, 129-140.Eaton, J. and Grossman, G.M., 1986, “Optimal Trade and Industrial Policy under Oligopoly”, Quarterly Journal of Economics, 101, 383-406.Maggi, G., 1996, “Strategic Trade Policies with Endogeneous Mode of Competition”, American Economic Review, 86, 237-258.De Mezza, D., 1986, “Export Subsidies and High Productivity: Cause or Effect?”Canadian Journal of International Economics, 19, 347-350.Neary, P.J., 1994, “Cost asymmetries in international Subsidy Games: Should Governments help winners or losers? Journal of International Economics, 37, 197-218.Qui, L.D., 1994, “Strategic Trade Policy under Uncertainty”Review of Economic Studies, 36, 333-354.Shivakumar, R., 1993, “Strategic Trade Policy: Choosing between Export Subsidies and Export Quotas under Uncertainty” Journal of International Economics, 35, 169-183.。
BurrĆBrown Productsfrom TexasInstrumentsFEATURES DESCRIPTIONAPPLICATIONSOUTFBDAC8550SLAS476C–MARCH2006–REVISED MARCH2006 16-BIT,ULTRA-LOW GLITCH,VOLTAGE OUTPUTDIGITAL-TO-ANALOG CONVERTER•Relative Accuracy:8LSB(Max)The DAC8550is a small,low-power,voltage output,16-bit digital-to-analog converter(DAC).It is •Glitch Energy:0.1nV-smonotonic,provides good linearity,and minimizes •Settling Time:10µs to±0.003%FSRundesired code to code transient voltages.The •Power Supply:+2.7V to+5.5V DAC8550uses a versatile3-wire serial interface that •16-Bit Monotonic Over Temperature operates at clock rates of up to30MHz and iscompatible with standard SPI™,QSPI™,•Micro Power Operation:200µA at5VMicrowire™,and digital signal processor(DSP)•Rail-to-Rail Output Amplifier interfaces.•Power-On Reset to MidscaleThe DAC8550requires an external reference voltage •Power-Down Capability to set its output range.The DAC8550incorporates a •Schmitt-Triggered Digital Inputs power-on reset circuit that ensures that the DACoutput powers up at midscale and remain there until a •SYNC Interrupt Facilityvalid write takes place to the device.The DAC8550•2's Complement Input and Reset to Midscale contains a power-down feature,accessed over the•Operating Temperature Range:-40°C to105°C serial interface,that reduces the current consumptionof the device to200nA at5V.•Available Packages:–3mm×5mm MSOP-8The low-power consumption of this device in normaloperation makes it ideal for portable battery-operatedequipment.Power consumption is1mW at5V,reducing to1µW in power-down mode.•Process ControlThe DAC8550is available in a MSOP-8package.•Data Acquisition Systems•Closed-Loop Servo-Control Also see the DAC8551binary coded counterpart of •PC Peripherals the DAC8550.•Portable Instrumentation•Programmable AttenuationFUNCTIONAL BLOCK DIAGRAMPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.SPI,QSPI are trademarks of Motorola.Microwire is a trademark of National Semiconductor.PRODUCTION DATA information is current as of publication date.Copyright©2006,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGS (1)ELECTRICAL CHARACTERISTICSDAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.PACKAGING/ORDERING INFORMATIONRELATIVE DIFFERENTIAL SPECIFICATION TRANSPORT PACKAGE PACKAGE PACKAGE ORDERING PRODUCTACCURACYNONLINEARITYTEMPERATUREMEDIA,LEAD DESIGNATOR (1)MARKINGNUMBER (LSB)(LSB)RANGE QUANTITY DAC8550IDGKT Tape and Reel,250DAC8550±12±1MSOP-8DGK–40°C TO 105°CD80DAC8550IDGKR Tape and Reel,2500DAC8550IBDGKT Tape and Reel,250DAC8550B ±8±1MSOP-8DGK –40°C TO 105°C D80DAC8550IBDGKRTape and Reel,2500(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document or see the TI website at .UNITSupply voltage,V DD to GND–0.3V to 6V Digital input voltage range,V I to GND –0.3V to +V DD +0.3V Output voltage,V OUT to GND–0.3V to +V DD +0.3VOperating free-air temperature range,T A –40°C to 105°C Storage temperature range,T STG –65°C to 150°CJunction temperature range,T J(max)150°C Power dissipation (DGK package)(T J max –T A )/θJAThermal impedance,θJA 206°C/W Thermal impedance,θJC44°C/W(1)Stresses above those listed under absolute maximum ratings may cause permanent damage to the device.Exposure to absolute maximum conditions for extended periods may affect device reliability.V DD =2.7V to 5.5V,–40°C to 105°C range (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYPMAXUNITSTATIC PERFORMANCE (1)Resolution16Bits Measured by line passing DAC8550±5±12LSB E L Relative accuracy through codes -32283and ±3±8LSB DAC8550B32063E D Differential nonlinearity 16-bit Monotonic±0.25±1LSB E O Zero-code error ±2±12mV Measured by line passing through codes -32283E FS Full-scale error ±0.05±0.5%of FSR and 32063.E GGain error±0.02±0.2%of FSR Zero-code error drift ±5µV/°C Gain temperature coefficient±1ppm of FSR/°C PSRR Power supply rejection ratio R L =2k Ω,C L =200pF0.75mV/V OUTPUT CHARACTERISTICS (2)V OOutput voltage rangeV REF V(1)Linearity calculated using a reduced code range of -32283to 32063;output unloaded.(2)Specified by design and characterization,not production tested.2Submit Documentation FeedbackDAC8550 SLAS476C–MARCH2006–REVISED MARCH2006ELECTRICAL CHARACTERISTICS(continued)V DD=2.7V to5.5V,–40°C to105°C range(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITTo±0.003%FSR,1200H to8D00H,R L=2kΩ,0810µspF<C L<200pFt sd Output voltage settling timeR L=2kΩ,C L=500pF12µsSR Slew rate 1.8V/µsR L=∞470pF Capacitive load stabilityR L=2kΩ1000pFCode change glitch impulse1LSB change around major carry0.1nV-s Digital feedthrough SCLK toggling,FSYNC high0.1z o DC output impedance At mid-code input1ΩV DD=5V50I OS Short-circuit current mAV DD=3V20Coming out of power-down mode V DD=5V 2.5t on Power-up timeµsComing out of power-down mode V DD=3V5AC PERFORMANCESignal-to-noise ratio(1st1995SNRharmonics removed)THD Total harmonic distortion85BW=20kHz,V DD=5V,f OUT=1kHz dBSFDR Spurious-free dynamic range87SINAD Signal-to-noise and distortion84REFERENCE INPUTV ref Reference voltage0V DD VV REF=V DD=5V5075µAI I(ref)Reference current input rangeV REF=V DD=3.6V3045µAz I(ref)Reference input impedance125kΩLOGIC INPUTS(3)Input current±1µAV DD=5V0.8V IL Low-level input voltage VV DD=3V0.6V DD=5V 2.4V IH High-level input voltage VV DD=3V 2.1Pin capacitance3pF POWER REQUIREMENTSV DD 2.7 5.5VI DD(normal mode)Input code equals mid-scale,reference currentincluded,no loadV DD=3.6V to5.5V200250V IH=V DD and V IL=GNDµA V DD=2.7V to3.6V180240I DD(all power-down modes)V DD=3.6V to5.5V V IH=V DD and V IL=GND0.22µA V DD=2.7V to3.6V0.052POWER EFFICIENCYI OUT/I DD I LOAD=2mA,V DD=5V89%TEMPERATURE RANGESpecified performance–40105°C(3)Specified by design and characterization,not production tested.3Submit Documentation Feedback PIN CONFIGURATIONVDDVREFVFBVOUTGNDDINSCLKSYNC 12348765DAC8550DAC8550SLAS476C–MARCH2006–REVISED MARCH2006MSOP-8(Top View)PIN DESCRIPTIONSPIN NAME DESCRIPTION1V DD Power supply input,2.7V to5.5V.2V REF Reference voltage input.3V FB Feedback connection for the output amplifier.4V OUT Analog output voltage from DAC.The output amplifier has rail-to-rail operation.Level-triggered control input(active LOW).This is the frame synchronization signal for the input data.When SYNC goesLOW,it enables the input shift register and data is transferred in on the falling edges of the following clocks.The DAC is 5SYNCupdated following the24th clock(unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC actsas an interrupt and the write sequence is ignored by the DAC8550).6SCLK Serial clock input.Data can be transferred at rates up to30MHz.7D IN Serial data input.Data is clocked into the24-bit input shift register on each falling edge of the serial clock input.8GND Ground reference point for all circuitry on the part.4Submit Documentation FeedbackTIMING REQUIREMENTS(1)(2)SERIAL WRITE OPERATION SYNCDINDAC8550 SLAS476C–MARCH2006–REVISED MARCH2006VDD=2.7V to5.5V,all specifications–40°C to105°C(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITV DD=2.7V to3.6V20t c(3)SCLK cycle time nsV DD=3.6V to5.5V20V DD=2.7V to3.6V13t1SCLK HIGH time nsV DD=3.6V to5.5V13V DD=2.7V to3.6V22.5t2SCLK LOW time nsV DD=3.6V to5.5V13V DD=2.7V to3.6V0t su1SYNC to SCLK rising edge setup time nsV DD=3.6V to5.5V0V DD=2.7V to3.6V5t su2Data setup time nsV DD=3.6V to5.5V5V DD=2.7V to3.6V 4.5t h Data hold time nsV DD=3.6V to5.5V 4.5V DD=2.7V to3.6V0t f SCLK falling edge to SYNC rising edge nsV DD=3.6V to5.5V0V DD=2.7V to3.6V50t3Minimum SYNC HIGH time nsV DD=3.6V to5.5V33(1)All input signals are specified with t R=t F=3ns(10%to90%of V DD)and timed from a voltage level of(V IL+V IH)/2.(2)See Serial Write Operation timing diagram.(3)Maximum SCLK frequency is30MHz at V DD=3.6V to5.5V and20MHz at V DD=2.7V to3.6V.5Submit Documentation FeedbackTYPICAL CHARACTERISTICS:V DD =5VL E − (L S B )Digital Input CodeD LE − (L S B )L E − (L S B )819216384245763276840960491525734465536Digital Input CodeD LE − (L S B )−6−4−20246L E − (L S B )−1−0.500.510819216384245763276840960491525734465536Digital Input CodeD LE − (L S B )−50510−404080120Temperature − 5CE r r o r (m V )120140160180200220240260280300I DD − Supply Current − m Af − F r e q u e n c y − H z−10−5−404080120Temperature − 5CE r r o r (m V )DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.LINEARITY ERROR ANDLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUTDIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUTCODE CODE (-40°C)(25°C)Figure 1.Figure 2.LINEARITY ERROR ANDZERO-SCALE ERRORDIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUTvsCODE TEMPERATURE(105°C)Figure 3.Figure 4.FULL-SCALE ERRORI DD HISTOGRAMvsTEMPERATUREFigure 5.Figure 6.6Submit Documentation FeedbackI (SOURCE/SINK) − mA0123456− O u t p u t V o l t a g e − VV O U TDigital Input CodeD D I S u p p l y C u r r e n t − −AµQ u i e s c e n t C u r r en t − Aµ050100150200250−40−10205080110Temperature − 5CD D I S u p p l y C u r r e n t − −AµV DD − Supply Voltage − VIAµV DD − Supply Voltage − VD D− S u p p l y C u r r e n t−1005009001300170012345D D I S u p p l y C u r r e n t − −AµV (LOGIC) − VDAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =5V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.SOURCE AND SINK CURRENT CAPABILITYSUPPLY CURRENTvsDIGITAL INPUT CODEFigure 7.Figure 8.POWER-SUPPLY CURRENTSUPPLY CURRENTvsvsTEMPERATURESUPPLY VOLTAGEFigure 9.Figure 10.POWER-DOWN CURRENTSUPPLY CURRENTvsvsSUPPLY VOLTAGELOGIC INPUT VOLTAGEFigure 11.Figure 12.7Submit Documentation FeedbackTime (2 µs/div)V DD = 5 V,V REF = 4.096 V,From Code: FFFF T o Code: 0000Zoomed Falling Edge 1 mV/divTrigger Pulse 5 V/divFalling Edge 1 V/divTime (2 µs/div)V DD = 5 V,V REF = 4.096 V,From Code: 0000T o Code: FFFFZoomed Rising Edge 1 mV/divTrigger Pulse 5 V/divRising Edge 1 V/divTime (2 µs/div)V DD = 5 V,V REF = 4.096 V,From Code: 4000T o Code: CFFFZoomed Rising Edge 1 mV/divTrigger Pulse 5 V/divRising Edge 1 V/divTime (2 µs/div)V DD = 5 V,V REF = 4.096 V,From Code: CFFF T o Code: 4000Zoomed Falling Edge 1 mV/divTrigger Pulse 5 V/divFalling Edge 1 V/divV DD = 5 V,V REF = 4.096 V From Code: 8000T o Code: 7FFF Glitch: 0.16 nV-sMeasured Worst CaseTime 400 ns/divV O U T (500m V /d i v )V DD = 5 V,V REF = 4.096 V From Code: 7FFF T o Code: 8000Glitch: 0.08 nV-sTime 400 ns/divV O U T (500m V /d i v )DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =5V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.FULL-SCALE SETTLING TIME:5-V RISING EDGEFULL-SCALE SETTLING TIME:5-V FALLING EDGEFigure 13.Figure 14.HALF-SCALE SETTLING TIME:5-V RISING EDGEHALF-SCALE SETTLING TIME:5-V FALLING EDGEFigure 15.Figure 16.GLITCH ENERGY:5-V,1-LSB STEP,RISING EDGEGLITCH ENERGY:5-V,1-LSB STEP,FALLING EDGEFigure 17.Figure 18.8Submit Documentation FeedbackV DD = 5 V,V REF = 4.096 V From Code: 8010T o Code: 8000Glitch: 0.08 nV-sTime 400 ns/divV O U T (500V /d i v )m V DD = 5 V,V REF = 4.096 V From Code: 8000T o Code: 8010Glitch: 0.04 nV-sTime 400 ns/divV O U T (500m V /d i v )V DD = 5 V,V REF = 4.096 V From Code: 80FF T o Code: 8000Glitch: Not Detected Theoretical Worst CaseTime 400 ns/divV O U T (5 m V /d i v )V DD = 5 V,V REF = 4.096 V From Code: 8000T o Code: 80FFGlitch: Not Detected Theoretical Worst CaseTime 400 ns/divV O U T (5 m V /d i v )8486889092949698S N R − S i g n a l -t o -N o i s e R a t i o − d Bf − Output Frequency − kHz−100−90−80−70−60−50−40012345T H D − T o t a l H a r m o n i c D i s t o r t i o n − d BOutput Tone − kHzDAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =5V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.GLITCH ENERGY:5-V,16-LSB STEP,RISING EDGEGLITCH ENERGY:5-V,16-LSB STEP,FALLING EDGEFigure 19.Figure 20.GLITCH ENERGY:5-V,256-LSB STEP,RISING EDGEGLITCH ENERGY:5-V,256-LSB STEP,FALLING EDGEFigure 21.Figure 22.TOTAL HARMONIC DISTORTIONSIGNAL-TO-NOISE RATIOvsvsOUTPUT FREQUENCYOUTPUT FREQUENCYFigure 23.Figure 24.9Submit Documentation Feedback100150200250300350100100010000100000n V /H z− V o l t a g e N o i s e −V n f − Frequency − Hzf − Frequency − HzG a i n − d BDAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =5V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.POWER SPECTRAL DENSITYOUTPUT NOISE DENSITYFigure 25.Figure 26.10Submit Documentation FeedbackTYPICAL CHARACTERISTICS:V DD =2.7VL E − (L S B )Digital Input CodeD LE − (L S B )−6−4−20246L E − (L S B )D LE − (L S B )Digital Input CodeL E − (L S B )Digital Input CodeD LE − (L S B )510Temperature − 5CE r r o r (m V )30060090012001500120140160180200220240260280300I DD − Supply Current − m Af − F r e q u e n c y − H z−10−505Temperature − 5CE r r o r (m V )DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.LINEARITY ERROR ANDLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERROR vs DIGITALDIFFERENTIAL LINEARITY ERROR vs DIGITALINPUT CODE INPUT CODE(-40°C)(25°C)Figure 27.Figure 28.LINEARITY ERROR ANDZERO-SCALE ERRORDIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUTvsCODE TEMPERATURE(105°C)Figure 29.Figure 30.FULL-SCALE ERRORI DD HISTOGRAMvsTEMPERATUREFigure 31.Figure 32.11Submit Documentation FeedbackI (SOURCE/SINK) − mA− O u t p u t V o l t a g e − VV O U TDigital Input CodeD D I S u p p l y C u r r e n t − −Aµ10030050070000.51 1.52 2.5D D I S u p p l y C u r r e n t − −AµV (LOGIC)− VQ u i e s c e n t C u r r e n t − AµTemperature − 5CTime (2 µs/div)V DD = 2.7 V,V REF = 2.5 V,From Code: 0000T o Code: FFFFZoomed Rising Edge 1 mV/divTrigger Pulse 2.7 V/divRising Edge 0.5 V/divV DD = 2.7 V,V REF = 2.5 V,From Code: FFFF T o Code: 0000Zoomed Falling Edge 1 mV/divTrigger Pulse 2.7 V/divFalling Edge 0.5 V/divTime (2 µs/div)DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =2.7V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.SOURCE AND SINK CURRENT CAPABILITYSUPPLY CURRENTvsDIGITAL INPUT CODEFigure 33.Figure 34.POWER-SUPPLY CURRENTSUPPLY CURRENTvsvsTEMPERATURELOGIC INPUT VOLTAGEFigure 35.Figure 36.FULL-SCALE SETTLING TIME:2.7-V RISING EDGEFULL-SCALE SETTLING TIME:2.7-V FALLING EDGEFigure 37.Figure 38.12Submit Documentation FeedbackTrigger Pulse 2.7 V/divZoomed Rising Edge 1 mV / divV DD = 2.7 V V REF = 2.5 V From code; 4000T o code: CFFFRising Edge 0.5 V/divTime − 2 m s/div V DD = 2.7 V,V REF = 2.5 V,From Code: CFFF T o Code: 4000Zoomed Falling Edge 1 mV/divTrigger Pulse 2.7 V/divFalling Edge 0.5 V/divTime (2 µs/div)V DD = 2.7 V,V REF = 2.5 VFrom Code: 7FFF T o Code: 8000Glitch: 0.08 nV-sTime 400 ns/div V O U T (200 m V /d i v )V DD = 2.7 V,V REF = 2.5 V From Code: 8000T o Code: 7FFF Glitch: 0.16 nV-sMeasured Worst CaseTime 400 ns/divV O U T (200 m V /d i v )V DD = 2.7 V,V REF = 2.5 V From Code: 8000T o Code: 8010Glitch: 0.04 nV-sTime 400 ns/divV O U T (200 u V /d i v )V DD = 2.7 V,V REF = 2.5 V From Code: 8010T o Code: 8000Glitch: 0.12 nV-sTime 400 ns/divV /d i v )V O U T (200 u V /d i v )DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =2.7V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.HALF-SCALE SETTLING TIME:2.7-V RISING EDGEHALF-SCALE SETTLING TIME:2.7-V FALLING EDGEFigure 39.Figure 40.GLITCH ENERGY:2.7-V,1-LSB STEP,RISING EDGEGLITCH ENERGY:2.7-V,1-LSB STEP,FALLING EDGEFigure 41.Figure 42.GLITCH ENERGY:2.7-V,16-LSB STEP,RISING EDGEGLITCH ENERGY:2.7-V,16-LSB STEP,FALLING EDGEFigure 43.Figure 44.13Submit Documentation FeedbackV DD = 2.7 V,V REF = 2.5 VFrom Code: 80FF T o Code: 8000Glitch: Not Detected Theoretical Worst CaseTime 400 ns/divV O U T (5 m V /d i v )AV DD = 2.7 V,V ref = 2.5 VFrom Code: 8000T o Code: 80FFGlitch: Not Detected Theoretical Worst CaseTime 400 ns/divV O U T (5 m V /d i v )DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006TYPICAL CHARACTERISTICS:V DD =2.7V (continued)At T A =25°C,unless otherwise noted.Unsigned binary equivalent inputs are shown in all figures.GLITCH ENERGY:2.7-V,256-LSB STEP,RISING EDGEGLITCH ENERGY:2.7-V,256-LSB STEP,FALLING EDGEFigure 45.Figure 46.14Submit Documentation FeedbackTHEORY OF OPERATION DAC SECTIONV OUT*V REF2)V REF D65536(1)To OutputAmplifierRESISTOR STRINGSERIAL INTERFACE OUTPUT AMPLIFIER DAC8550SLAS476C–MARCH2006–REVISED MARCH2006 The architecture consists of a string DAC followed byan output buffer amplifier.Figure47shows the blockdiagram of the DACFigure47.DAC8550ArchitectureThe input coding to the DAC8550is2's complement,so the ideal output voltage is given by:where D=decimal equivalent of the2's complementcode that is loaded to the DAC register;D rangesfrom-32768to+32767where D=0is centered atV REF/2.Figure48.Resistor StringThe resistor string section is shown in Figure48.It issimply a string of resistors,each of Thecode loaded into the DAC register determines atwhich node on the string the voltage is tapped off toThe DAC8550has a3-wire serial interface(SYNC, be fed into the output amplifier by closing one of theSCLK,and D IN),which is compatible with SPI™, switches connecting the string to the amplifier.QSPI™,and Microwire™interface standards,as well Monotonicity is ensured due to the string resistoras most DSP interfaces.See the Serial Write architecture.Operation timing diagram for an example of a typicalwrite sequence.The write sequence begins by bringing the SYNC line The output buffer amplifier is capable of generatingLOW.Data from the D IN line is clocked into the24-bit rail-to-rail output voltages with a range of0V to V DD.shift register on each falling edge of SCLK.The serial It is capable of driving a load of2Ωk in parallel withclock frequency can be as high as30MHz,making 1000pF to GND.The source and sink capabilities ofthe DAC8550compatible with high-speed DSPs.On the output amplifier can be seen in the typical curves.the24th falling edge of the serial clock,the last data The slewrate is1.8V/µs with a full-scale setting timebit is clocked in and the programmed function is of8µs with the output unloaded.excuted(i.e.,a change in DAC register contents The inverting input of the output amplifier is brought and/or a change in the mode of operation).out to the V FB pin.This allows for better accuracy inAt this point,the SYNC line may be kept LOW or critical applications by tying the V FB point and thebrought HIGH.In either case,it must be brought amplifier output together directly at the load.OtherHIGH for a minimum of33ns before the next write signal conditioning circuitry may also be connectedsequence so that a falling edge of SYNC can initiate between these points for specific applications.the next write sequence.Since the SYNC bufferdraws more current when the SYNC signal is HIGH15Submit Documentation FeedbackSYNC INTERRUPTINPUT SHIFT REGISTERPOWER-ONRESETCLK D INValid Write Sequence: Output Updateson the 24th Falling Edge24th Falling Edge24th Falling EdgeDB23DB80DB23DB80POWER-DOWN MODESDAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006than it does when it is LOW,SYNC should be idled LOW between write sequences for lowest power In a normal write sequence,the SYNC line is kept operation of the part.As mentioned above,it must be LOW for at least 24falling edges of SCLK and the brought HIGH again just before the next write DAC is updated on the 24th falling edge.However,if sequence.SYNC is brought HIGH before the 24th falling edge,it acts as an interrupt to the write sequence.The shift register is reset and the write sequence is seen as invalid.Neither an update of the DAC register The input shift register is 24bits wide,as shown in contents nor a change in the operating mode occurs,Figure 49.The first six bits are don't care bits.The as shown in Figure 50.bits (PD1andPD0)are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes).For a more complete description of the various modes see The DAC8550contains a power-on reset circuit that the Power-Down Modes section.The next 16bits are controls the output voltage during power-up.On the data bits.These are transferred to the DAC power-up,the output voltages are set to midscale;it register on the 24th falling edge of SCLK.remains there until a valid write sequence is made to the DAC.This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.XXXXXXPD1PD0D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0Figure 49.DAC8550Data Input Register FormatFigure 50.SYNC Interrupt Facilityat 5V.However,for the three power-down modes,the supply current falls to 200nA at 5V (50nA at 3V).Not only does the supply current fall,but the The DAC8550supports four seperate modes of output stage is also internally switched from the operation.These modes are programmable by setting output of the amplifier to a resistor network of known two bits (PD1and PD0)in control register.Table 1values.The advantage with this is that the output shows how the state of the bits corresponds to the impedance of the device is known while in mode of operation of the device.power-down mode.There are three different options.The output is connected internally to GND through a Table 1.Modes of Operation for the DAC85501-k Ωresistor,a 100-k Ωresistor,or it is left open-circuited (High-Z).The output stage is illustrated PD1PD0OPERATING MODE(DB17)(DB16)in Figure 51.00Normal operation All analog circuitry is shut down when the ----Power-down modespower-down mode is activated.However,the 01Output typically 1k Ωto GND contents of the DAC register are unaffected when in power-down.The time to exit power-down is typically 10Output typically 100k Ωto GND 2.5µs for V DD =5V,and 5µs for V DD =3V.See the 11High-ZTypical Characteristics for more information.When both bits are set to 0,the device works normally with a typical current consumption of 200µA16Submit Documentation FeedbackDAC8550to Microwire InterfaceOUTFBNOTE: (1)Additional pins omitted for clarity.MICROPROCESSOR INTERFACINGDAC8550TO 8051InterfaceDAC8550to 68HC11InterfaceNOTE: (1)Additional pins omitted for clarity.NOTE: (1)Additional pins omitted for clarity.DAC8550SLAS476C–MARCH 2006–REVISED MARCH 2006Figure 53shows an interface between the DAC8550compatible device.Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8550on the rising edge of the SK signal.Figure 51.Output Stage During Power-DownFigure 53.DAC8550to Microwire Interface See Figure 52for a serial interface between the Figure 54shows a serial interface between the a typical 8051-type microcontroller.and the 68HC11microcontroller.SCK of The setup for the interface is as follows:TXD of the the 68HC11drives the SCLK of the DAC8550,while 8051drives SCLK of the DAC8550,while RXD drives the MOSI output drives the serial data line of the the serial data line of the device.The SYNC signal is DAC.The SYNC signal is derived from a port line derived from a bit-programmable pin on the port of (PC7),similar to the 8051diagram.the 8051.In this case,port line P3.3is used.When data is to be transmitted to the DAC8550,P3.3is taken LOW.The 8051transmits data in 8-bit bytes;thus only eight falling clock edges occur in the transmit cycle.To load data to the DAC,P3.3is left LOW after the first eight bits are transmitted,then a second write cycle is initiated to transmit the second byte of data.P3.3is taken HIGH following the completion of the third write cycle.The 8051outputs Figure 54.DAC8550to 68HC11Interface the serial data in a format which has the LSB first.The DAC8550requires its data with the MSB as the first bit received.The 8051transmit routine must The 68HC11should be configured so that its CPOL therefore take this into account,and mirror the data bit is 0and its CPHA bit is 1.This configuration as needed.causes data appearing on the MOSI output to be valid on the falling edge of SCK.When data is being transmitted to the DAC,the SYNC line is held LOW (PC7).Serial data from the 68HC11is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.(Data is transmitted MSB first.)In order to load data to the DAC8550,PC7is left LOW after the first eight bits are transferred,then a second and third serial write Figure 52.DAC8550to 80C51/80L51Interfaceoperation is performed to the DAC.PC7is taken HIGH at the end of this procedure.17Submit Documentation Feedback。
This document is printed on chlorine-free (ECF) paper with soy ink. Printed in JapanLCK-0511For details please contact:For Vocal RecordingFor Guitarist(Song Writer)For DJ Mixing and PodcastingFor Making Video(Audio Capture)Desktop PCUSBIEEE1394orFireWireVideo CameraCD Player MD Player etc.Mics(Condenser Microphones)HeadphoneDesktop PCMicUSBSynthsizer (MO6 etc.)HSSpeakersUSBNOTE PCTurn table (Record Player)Turn table (Record Player)HDDAudio playerMW10Preamp for Acoustic GuitarAcoustic GuitarSystem ExamplesHSSpeakersHSSpeakersUSBNOTE PCMW12MW12MW10*All specifications are subject to change without notice.*All trademarks and registered trademarks are property of their respective owners.SpecificationsElectrical CharacteristicsMW10MW12UNIT Total Harmonic Distortion 0.1%Frequency Response 20Hz~20kHz (ST Out)-3 (MIN), 0 (TYP), 1 (MAX)dB Hum & NoiseEquivalent Input Noise (CH IN /MIC)-128dBu Residual Output Noise (ST OUT)-100dBu ST master control at nominal level and all-87-88dBu channel LEVEL controls at minimum level. (ST OUT)All channel AUX controls at minimum level. (AUX SEND)-85-81dBu ST master control and one channel LEVEL control -64dBu at nominal level. (CH INPUT 1, 2) (ST OUT)Maximum Voltage GainMIC to CH INSERT OUT 60dB MIC to ST OUT, GROUP OUT 7684dB MIC to ST OUT, GROUP to ST -94dB MIC to REC OUT64.262.2dB MIC to AUX SEND (PRE)7076dB MIC toAUX SEND (POST)7686dB LINE to ST OUT, GROUP OUT 5058dB LINE to AUX SEND (PRE)7076dB LINE to AUX SEND (POST)4757dB LINE TO ST OUT(MW10: CH7/8, 9/10)2634dB (MW12: CH/10, 11, 12)RETURN to ST OUT 1216dB RETURN to AUX SEND -9dB 2TR IN to ST OUT23.827.8dB Crosstalk-70dBAnalog Input SpecificationsInput Imp,Appropriate lmpMW10MW12UNIT MIC INPUT GAIN3k ohms, 50-600 ohms mic -60 ~ -16MIC INPUT SENSITIVITY to MAX -72 ~ +4-80 ~ +4dBu LINE INPUT GAIN10k ohms, 600 ohms line -34 ~ +10LINE INPUT SENSITIVITY to MAX -46 ~ +30-54 ~ +30dBu ST CH MIC INPUT GAIN3k ohms,50-600 ohms mic -60 ~ -16ST CH LINE INPUT SENSITIVITY to MAX -72 ~ -10-80 ~ -10dBu ST CH LINE INPUT GAIN10k ohms,50-600 ohms line -34 ~ +10ST CH LINE INPUT SENSITIVITY to MAX -46 ~ +30-54 ~ +30dBu ST CH MIC INPUT GAIN3k ohms, 50-600 ohms mic -60 ~ -16ST CHMIC INPUT SENSITIVITY to MAX -72 ~ -10-80 ~ -10dBu ST CH LINE INPUT GAIN10k ohms, 600 ohms line-34 ~ +10ST CH LINE INPUT SENSITIVITY to MAX -46 ~ +30-54 ~ +30dBu ST CH INPUT -22 ~ +10-30 ~ +10dBu CH INSERT IN 10k ohms, 600 ohms line-12 ~ +20-20 ~ +20dBu RETURN (L, R)-8 ~ +24-12 ~ +24dBu 2TR IN-22 ~ +10-26 ~ +10dBuAnalog Output SpecificationsInput Imp, Appropriate Imp MW10MW12UNIT ST OUT (L, R)Normal 150 ohms, 10k ohms line (MW10)+4Max 75 ohms, 600 ohms line (MW12)+20+24dBu AUX SEND Normal 150 ohms, 10k ohms line +4Max +20dBu GROUP OUT Normal 150 ohms, 10k ohms line -+4Max -+20dBu CH INSERT OUTNormal 150 ohms, 10k ohms line 0Max +20dBu C-R OUT Normal 150 ohms, 10k ohms line +4Max +20dBu Rec OUT Normal 600 ohms, 10k ohms line -10Max +10dBu PHONESNormal 100 ohms, 40 ohms phone3Max75dBuGeneral SpecificationsMW10MW12High Pass Filter 80kHz 12dB/OctaveCH EQ±15dBHIGH: 10kHz (shelving)MID: 2.5kHz (peaking)LOW: 100Hz (shelving)Phantom Power +48VPower Adaptor PA-10PA-20Power Consumption 19 W29 WDimensions (W x H x D)251 mm x 65 mm x 290.5 mm322 mm x 108 mm x 416.6 mmNet Weight1.8 kg 5 kgTemperature Range Operating temperature: 0 to 40 ˚C, Storage temperature: -20 to 60 ˚CDigital Input/Output USB Audio1.1, 44.1/48kHz 16bit, USB B typeOther-Included Rack mount EarsHum & Noise Rs=150 ohms, Gain=Maximum (CH INPUT 1-2), Hum & Noise are measured with a-6dB/********************;equivalent to a 20 kHz filter with infinite dB/octave attenuation.(CH INPUT 1-11/12 to ST OUT, GROUP OUT, AUX SEND, C-R OUT, REC OUT)1 kHz, 10k ohms PAN/BAL: panned hard left or hard right.Setting up for the first timeAfter you’ve installed and launched Cubase LE for the first time,you’ll need to make a few configuration settings—such as selecting the audio driver, enabling inputs and outputs within Cubase LE, etc. Once you’ve done this, the MW can be used for recording every time you open Cubase LE.Getting ready to recordOpen a new project in Cubase LE, and set up for recording. Select or create an audio track (stereo or mono), open the Mixer window, and turn Click on (for a metronome guide). Set the start point for recording, too.Everything connected? You’re almost ready… Turn Record Enable on, and check the levels while you adjust the Gain and Master Level controls on the MW.Recording and playbackNow start recording (from the Transport panel), play or sing the part, and stop when you’re finished. Play it back and add other parts to it as needed, building up a complete song part-by-part. Mixing your songOnce you have several different parts—all on different tracks—call up the Mixer window. Use the faders in the Mixer to control the balance of the parts, and use the Pan controls and EQ processing to adjust the sound as needed.TIP – Use your favorite outboard gearIf you’re recording vocals, you can insert your favorite outboard compressor or EQ into the signal path before recording, by using the MW’s rear-panel INSERT jacks. Guitarists can plug in their stomp boxes to record the exact sound they want.TIP – Dig into your mic closetThe MW also has 48V phantom power, so you can use high-quality condenser or ribbon microphones and get pro-quality sound for your vocals and acoustic instruments.TIP – Plug-in effectsCubase LE also has a wide variety of plug-ineffects— including reverbs, delays, distortion, and more—you can use to enhance or alter the sound of each track as desired.Tip – Cut out the Latency problem!If you require to use the VST instruments with MIDI controller and you need a low latency. No problem! You can download ASIO low latency audio driver at Inspiration can come at any time. But it can also leave—if you have to spend too much time fiddling with your equipment. Not so with the MW. With the included Cubase LE software, the MW gives you a simple yet comprehensive system for recording all your musical ideas to computer—and recording your moments of inspiration before they have a chance to leave!Plug in a guitar, a microphone, a keyboard, even a CD player. Use the three-band EQ to tweak your sound, and connect your favorite effect device to the send/return jacks for further processing. The familiar mixer layout lets you stay in your comfort zone and work efficiently. Recording to Cubase LE is a breeze, too—especially with the downloadable low-latency ASIO driver, which lets you use your plug-in software synths and effects in real time.The MW is also ideal for collaborating with others. Just bring it along with your laptop and guitar, and you’ve got a complete, portable mobile studio—ready to go anywhere and record with anyone.Scene 1Laying down tracks for solo musicians, producers, small project studiosIf you’re a DJ and have a standard two-turntables-and-a-microphone setup, the MW can help keep your beats flowing. The MW has enough connectors for bigger live rigs as well—letting you add a couple of synths and a CD player, and still have room for more.The big-brother MW12 is even more capable, handling up to 12 simultaneous inputs. It features a paired bus (Group 1/2) for assigning channels to a separate grouped output. There’s also a PFL (Pre-Fader Listen) switch that lets you conveniently cue up tracks—so you can monitor the sound of a source through your headphones before letting your audience hear it.At home, use the MW with Cubase LE to record your personal mixes, then burn them to CDs for your friends and fans. This system is perfect for creating custom remixes, too. With the full audio editing capabilities of Cubase LE—including automatic tempo matching and stretching of audio parts—plus multitrack recording of up to 48 tracks, you’ve got all you need to record, edit and mix your musical masterpieces.Scene 3Enjoying total control for club music, DJ work, mixing straight to CDScene 2Capturing the moment for recording backup singers, multi-instrument partsRecording ProcedureScenesMusic is a succession of magic moments—made even more magical and exciting when you get several musicians and singers together. The MW lets you capture those moments, mixing down the performance of several backup singers or instrumentalists and recording them directly to a two-channel stereo track in Cubase LE.With the MW and a laptop, the whole world becomes your personal recording studio. Portable, self-contained, flexible, comprehensive—the MW mixers give you virtually everything you need to make great recordings. Since Cubase LE gives you 48 tracks of audio to work with, you can build up songs part-by-part and easily create professional sounding arrangements.Use the MW as a keyboard submixer when you play live, or use it as a utility mixer for events, gatherings and small rehearsals—and even record these events direct to stereo on your computer.Step 1Step 3Step 4Step 2Front PanelsMW10MW12Yamaha MW10 and MW12USB Mixing StudioGetting the music that’s in your head out into the real world doesn’t have to be difficult. In fact, with Yamaha’s new MW10 and MW12 USB Mixing Studio, making great music is easier than ever before. Combined with the powerful Cubase LE audio/MIDI sequencing software, the MW Mixer provides a comprehensive tabletop studio setup for the solo recording musician and for the travelling producer/arranger.High-quality multitrack mixing/recording systems don’t get any simpler than this. Along with its versatile mixing functions, the MW features a true plug-and-play USB audio interface—giving you a fast, no-nonsense way to get quality audio tracks into your computer. With Cubase LE, it’s also an advanced, all-in-one solution that turns any computer into a complete, top-flight recording system.USB StudioConnect the MW to a USB terminal on your laptop or desktop computer, and you’ve got an instant, high-quality audio recording studio in-a-box.The MW delivers true plug-and-play USB audio input/output interfacing, and lets you easily mix your audio sources down to two-track stereo for recording to computer.The MW package includes Steinberg’s Cubase LE—a cross-platform software that provides a complete audio/MIDI recording solution, along with video playback and music notation capabilities. A low-latency ASIO driver is available for free download at our website, giving you optimum performance and letting you use VST plug-in instruments and effects in real time. Cubase LE has over 40 built-in VST instruments and effects, but you can add more as your needs grow.Mixer Input SectionThe MW10 gives you a total of 10 inputs, including four ultra-low-noise mic preamps. The MW12 has even more—12 inputs, with six mic pre amps. These high-performance balanced inputs also have a phantom power switch, allowing you to take advantage of the superior sonic quality of professional-level condenser microphones.These mixers accept just about any source you want to plug into them, with a full variety of input connectors—including balancedXLR, 1/4” phone jacks and RCA pin jacks. Comprehensive sound shaping is also onboard with pan controls, 3-band EQ and 80 Hz high-pass filters (to cut hum and low-frequency noise) on each channel strip.The MW provides insert patch points —for two channels on the MW10, and four on the MW12—letting you put external compressors and EQ into the signal path, and process your vocals or guitar as needed.Mixer Master SectionThese versatile mixers are also fully equipped for your external processing and monitoring needs. Two AUX send/return buses let you apply further signal processing on each channel—for example, with your favorite external reverb and delay units, or other effects devices.In addition to the main stereo outputs, the MW features separate headphone, control room and recording outputs as well, giving you plenty of options for a wide range of monitoring and recording applications. And visual monitoring of the output level is made accurate and easy with the bright 12-segment level meters.Exclusive Features of the MW12The MW12 has all the USB studio features found on the MW10, but packs even more mixing power, control and flexibility into its compact package. Foremost are the 12 inputs, including sixbalanced XLR inputs (for microphones), and four stereo line input channels. The MW provides separate inserts for Channels 1 – 4, letting you route the incoming signals through your favorite processors before mixing and recording.The MW12 is also rack-mountable and uses long-throw faders instead of knobs for easy level control. The two AUX Sends each have separate knob controls, and the AUX 1 bus can be configured pre- or post-fader, useful for setting up an independent monitor mix. The MW12 also has Master Send and Return controls for maximum control over the AUX buses.Separate Group buses 1 and 2 give you further flexibility in creating sub mixes. The MW12 features a convenient PFL (Pre-Fader Listen) switch that lets you monitor an incoming signal (in your headphones, for example) without having to boost the level of the channel, and has independent Stereo switches on all channels, for sending the signal to both the stereo L/R bus and the computer.HardwareSoftwareCubase LE is a full-featured music production software based on the award-winning Cubase SX and SL programs. It gives you up to 48 simultaneous audio tracks and 64 MIDI tracks, plus a variety of VST plug-in software synths and effects, as well as full VSTi compatibility, with support for up to eight VST instruments. Just as the Yamaha MW USB Mixing Studio is your all-in-one solution to mixing and recording tracks to computer, the powerful Cubase LE provides all you need to record, edit, process and mixdown your masterpieces. At the center of Cubase LE is a full-fledged audio/MIDI sequencer, which allows you to record audio (vocals, guitar, etc.) along with MIDI data (from keyboards, synthesizers, etc.) and have everything in perfect sync. What’s more, Cubase LE also includes built-in virtual sound modules, letting you play and record MIDI tracks with software synths. The LM-7 provides drum and percussion kits, while the VB-1 has a variety of bass sounds. And the Universal Sound Module has a comprehensive set of instrument sounds in every category, mapped according to the standard GM format. These VSTinstruments give you the power to create full arrangements —without the need for external tone generators.Cubase LE also has a complete set of built-in virtual effects to process your sound —everything from reverb, chorus and delay effects to distortion, rotary speaker, filter and modulation—plus many different and unusual variations within. All of the effects are software based, so you can enhance and transform the sound all inside your computer!The editing features of Cubase LE give you further control over yourrecordings, providing a number of different ways to rearrange your parts and tracks. Use the mainProject window to recordand do basic work on your tracks (such as cutting, copying and moving sections), and use the other editing windows for more detailed work. The Sample Editor, for example, lets you easily manipulate your audio recordings. For MIDI recordings,there are a variety of options—the Key Editor (in piano roll form), the Drum Editor (with convenient event and drum mapping indications), the Score Editor (for notation based editing), and the detailed List Editor (showing all MIDI events).The power and versatility of Cubase LE is truly amazing, when you take a look at all the different projects and applications it can handle. If you’re into video production, you can easily use Cubase LE to create complex soundtracks and sound effect beds for your projects. Simply import the video (from your camcorder, for example) into Cubase LE and record narration and music on top—and have all your tracks synchronize perfectly with the images. Then creatively enhance your projects with the effects in Cubase LE—making huge explosive sounds with the help of reverb, or using the Vocoder effect for robot-like voices.Since the MW lets you record your analog sources (microphone, etc.) to computer in digital form, this compact setup is perfect for podcasting applications as well. Produce your own Internet radio programs, create custom remixes, and record your own CDs—the possibilities are endless.Cubase LE is compatible with both the Mac and Windows PC platforms, and since Cubase LE projects are completely upward compatible with the professional level Cubase SX and SL, you can still use your LE songs if and when you decide to upgrade. Cubase LE is the perfect way to enter the world of computer-based recording, giving you all the tools to produce professional level recordings—quickly and easily—while providing a system that you can expand into the future!Note: If you want to connect a MIDI keyboard, the optional Yamaha UX16 USB/MIDI interface provides a very simple, inexpensive way to get MIDI data into and out of your computer.Block DiagramsRear PanelsMacintoshWindowsPower Mac G4 450 MHzPentium III 500 MHz or AMD K7(P III / Athlon 1 GHz or faster recommended)256 MB RAM (512 MB recommended)256 MB RAM (512 MB recommended)1GB of free hard disk space for 1GB of free hard disk space for complete content complete contentcomplete contentOS X Version 10.2 or higherWindows 2000, Windows XP Home and XP Professional CoreAudio compatible audio hardwareWindows MME compatible audio hardware ASIO compatible sound card recommendedSystem RequirementsCubase LE。
