基于FPGA相关的毕设论文文献翻译

Choosing a signal generator for frequency-agile apps (为频率捷变应用选择信号发生器)Student ID：0703010110Name:董林Date:5/18/2010Choosing a signal generatorfor frequency-agile appsDepending on a signal generator's primary use, or a company's budget, one of thevarious types of traditional signal generator designs may YIG-tuned orbanded-synthesizer as typically been preferred over the others. However, the recentemergence of signal generators based on a synthetic-instrument architecturepromises to change the selection process.In testing frequency-agile radios, finding a signal generator able to keep up withthe desired frequency-hopping pattern on instrument with a very fast hopping rate andsettling time limits the user's options. If the test system were only required to producesimple frequency modulation, or only used as a fast hopping local oscillator, afast-tuning signal generator would be fine. Unfortunately, this same signal generatoris unlikely to produce the complex modulation required by the latest commercialwireless or military communication standards.As a result, designers have typically purchased two or more signal generators toperform unique tasks within the application, adding considerable expense. Theintroduction of synthetic-instrument (SI) signal generators consisting of anarbitrary-waveform generator (AWG) and a vector up-converter takes it possible toreduce the number of signal generators needed, and thereby reduce costs. What’s asynthetic instrument? As defined by the Synthetic Instrument Working Group (SIWG),a synthetic instrument is a combination of hardware and software modulesconcatenated together so they can emulate traditional instrumentation (see Fig. 1)while allowing flexibility in instrumentation configuration.Fig. 1. Synthetic-instrument architectures divide functions between hardware and software toincrease flexibility.The SIWG is chartered with developing the standards for the interfaces betweenmodules, so as to facilitate vendor and module interchangeability. This interchangeability would promote the longevity and upgradeability of test systems.Choosing an instrument architecture In the specific case of a signalgenerator, the hardware modules would include a vector up-converter and AWG,while the software modules would consist of some baseband signal generationsoftware. The software modules could be hosted on a personal computer or perhapsresident in the AWG.One benefit of an SI signal generator is the flexibility it offers engineer to chooseinstrumentation performance based on the device that needs to be tested. For instance,if all the devices to be tested are narrow band and of a low frequency, a test engineercould choose an inexpensive AWG and RF up-converter. Then, when a companydevelops new products requiring either wider bandwidth or operating at higherfrequencies, the engineer may only need to upgrade the AWG or up-converter previously selected.Traditional signal generators have specified the tuning, or frequency-switching, speed as the time it takes to tune from one frequency to the next with a specified stability in both frequency and amplitude. Currently, the most popular traditional signal generators are based on YIG-tuned oscillators, which are the source of switching-speed limits.One major benefit of these signal generators is their ability to internally generate complex modulated base bands, thanks to optionally built-in I/Q modulators and flexible AWG. While the switching speed of this class of instrument has improved over the years, currently available products can only achieve switching speeds in the 100 to 500 region sufficient for the commercial wireless industry, but not fast enough for frequency-agile radar.Another type of signal generator is the banded-synthesizer design. To achieve a desired fundamental frequency, the instrument multiplies and divides the output of a high-performance local oscillator.This technique can result in switching speeds below 1 taking it fast enough for many radar applications and some advanced tactical radios, like Link-16out the design doesn't have the flexible modulation types needed for Link-16 and other modern frequency-agile digital communications. One choice for solving this seemingly paradoxical problem is an ultra-wide-bandwidth AWG coupled to a vector up-converter with an ultra-wideband modulator.Another choice would be to use the "golden radio" method of signal generation. Used since the early days of radio, this method had been the only method available to test the newest modulation formats.The method consists of using an actual radio as a piece of test equipment, first measuring the radio's performance on calibrated pieces of test equipment like a power meter, spectrum analyzer, and vector signal analyzer, so that one can assume this radio's performance is "perfect." The golden radio can now be the measure to which all of the other radios can be compared. This test technique has many advantages, including cost (parts are available when the radio is being developed) and the correct modulation data and format.However, the golden radio is usually not as stable as a piece of NIST-traceable test equipment, and herein lies the problem. If its performance drifts, the golden radio can fail good radios are pass defective ones.Tradeoff example A Link-16 radio is a good example that challenges of both switching speed and the flexibility needed with today's complex modulation schemes. Since some may not be familiar with these military systems, whose broadcast techniques are also seen in commercial systems, a brief description of a Link-16 radio is in order.The Link-16 is an ad-hoc military tactical radio network which uses frequency (channel) agility to avoid interference or jamming, which is very similar to the operation of the popular Bluetooth network. What makes the Link-16 waveformchallenging to generate is its requirement for sub-microsecond switching speeds and the MSK (Minimum Shift Keying) modulation it requires for encoding data.Current off-the-shelf signal generators do not provide this kind of combined performance, requiring customers to use a custom signal generator or use the "golden radio" approach to testing their Link-16 radios. These choices are either costly and poorly supported, or do not provide the test accuracy ratio (TAR) required to validate the radio's operational performance.The minimum military requirement is a 3:1 TAR: the signal generator must be 3 times better performance than the radio it is testing. Because the golden-radio approach uses an actual production radio, it has a TAR of slightly better than 1:1.Unlike Bluetooth, the Link-16 frequency hopping sequence is determined by a secure cryptographic unit that tells the radio where to tune in order to receive the next data message. This additional requirement all but forces a radio manufacturer to use the golden-radio approach; the option of using use a custom signal generator is stymied by the fact that the generator must be a secure (classified) piece of test equipment, further complicating its use as general purpose.An SI signal generator can overcome this complex problem (see Fig. 2). Its use of an AWG can provide the flexibility to add virtually any kind of modulation format and associated data into the available memory.Fig. 2. The N8241A arbitrary waveform generator operates at 1.25 Gsamples/s (500 MHz) with optional direct sequencing for external control of a memory sequence, while the N8212A vector up-converter allows tuning from 250 kHz to 20 GHz, with external I/Q bandwidth inputs up to 1 GHz.Instead of trying to tune the vector I/Q up-converter to keep up with the demands of the cryptographic scheme, one would tune the up-converter to the desired frequency and program the AWG to change frequencies digitally.The AWG bandwidth (sample rate) must be at least as wide as the range of hopping frequencies (255 MHz for Link-16), and then the test engineer can program all the possible frequencies (at baseband) with the required waveforms which can then be sequenced in the proper order. This will have the same effect of the fast tuning radio. The vector up-converter must have the required bandwidth of the entire hopping waveform range (255 MHz).Since the hopping pattern is, typically, unknown to the user, some way of directly interfacing with the cryptographic hardware is required. Using a digital word provided by the crypto to tell the AWG which segment of the waveform memory to play will provide the need connection.If all that is needed is narrow-band RF capability, the SI solution may be more expensive than a traditional signal generator today. However, high-performance D/A converters are continuously improving and coming down in price, which can make this kind of a product available to every engineering operation.Evolving the test benchIf you look at a typical test bench today, you'll likely see rows of boxes stacked several feet high, surrounded by a maze of wires, cords, and test leads. Configured to fulfill the functionality requirements of engineers developing and testing new product designs, such test benches usually contain many different types of instruments voltmeters, ammeters, ohmmeters, voltage and/or current sources, and frequency generators, to name but a few.In an attempt to reduce the benchtop's confusing complexity, things are beginning to change. The latest test-bench instruments combine many, if not most, of the functions found in several stand-alone instruments into one box, offering engineers a lot more power, choice, and flexibility in less space.Raising functional density The biggest and most notable change in the design and manufacture of newer generations of bench top instruments is increased integration. For instance, DMMs traditionally multi-function devices that measured voltage, current, and resistance now can measure more parameters. Most DMMs can handle frequency and temperature, as well as parameters for specific diode and transistor tests.Even more recent generations of DMMs included scanner cards that let them switch from point to point in a circuit or to several devices under test (DUTs). Most DMMs now also include a storage buffer with the ability to hold up to 450,000 readings. A key option for test engineers, scan-and-store capability lets them apply the DMM's full functionality to multipoint testing and capture a broad set of results. In effect, the latest DMMs can act as complete data acquisition systems with a full range of measurement functions.Another feature being integrated into DMMs is some type of signal-source unit (see Fig. 1). In the past, test engineers had to link power supplies and/or signal generators together with a measuring instrument, such as a DMM. Now, there are single units available that both source signals and measure and record results. Some of these instruments have two or more signal channels for greater functional density and flexibility.Fig.1. A signal-source unit such as the Series 2600 SourceMeter adds signal sources to enhanced DMM functionality to increase functional density on the benchtop.Along with increased integration comes the demand for more specialized instruments. For instance, some oscilloscopes feature specialized interfaces for testing newly emerging serial buses. On the other hand, some cutting-edge applications demand entirely new tools and features. The field of nanotechnology research anddevelopment demands instruments that can accurately and repeatedly measure extremely small quantities in the nanovolts range and below. Nanotechnology research also demands highly accurate and stable sources of arbitrary waveforms. Many instruments can now offer the precise and stable waveforms necessary for nanotechnology applications.Better communication The growth of the Internet and the World Wide Web has also impacted test instruments. Web-enabled instruments are fairly common today. Most of these instruments contain an Ethernet connection that lets the instrument talk to a PC or connect to other instruments to form a complete data-acquisition system. Most Web-enabled instruments contain a built-in Web page with a specific instrument URL. The Web page allows users to read and set such network parameters as IP address, MAC address, and calibration dates, and to send commands to and query data from a unit.Another advance in interfaces is the development of the LAN extensions for instrumentation (LXI) being developed by the LXI Consortium. Basically, LXI is a communications standard for networking small, modular instruments with or without front panel control or on board display in which Ethernet serves as the system communications backbone.The Consortium's goal is to define a common instrumentation standard to offer the flexible packaging and tight integration advantages of proprietary modular instruments without the physical constraints and added cost of card-cage architectures. The plan is for the LXI standard to evolve with, and take advantage of, current and future LAN developments that go beyond the basic connection capabilities of legacy test and measurement systems. These developments include web-style interfacing, local- and wide-area networking, and precision timing synchronization capabilities (see table).As for other communication interfaces, IEEE-488, or GPIB, is still a dominant one, partly because it has been around for nearly three decades. One of the first networks specifically developed to interconnect and control programmable instrument, this parallel interface is built into many, if not most, instruments on the market s. Its published data rates are 1 Mbit/s, with a maximum of 8 Mbits/s in burst mode.Another interface gaining popularity in test and measurement applications is USB. It is already widely used in computer peripherals such as printers, mice, and digital cameras as a quick and easy way to connect to a PC. Virtually all desktop and laptop PCs on the market come equipped with USB ports. These ports have full software support under common operating systems such as Windows 2000 and XP.For test and measurement applications, USB offers some significant advantages. USB provides users with a simple means of developing test and measurement applications by offering advantages over PC plug-in boards. These include plug-and-play capability, better noise immunity, cost savings, and portability, among others.USB offers full- and high-speed data transfer rates. Computers configured with USB 1.1 ports can transfer data at up to 12 Mbits/s. For high-performance applications, high-speed USB 2.0 ports boast speeds of up to 480 Mbits/s.Bench automation Only a few years ago, software was used to control rack and stack test systems mostly in production applications. More and more, benchtop instruments come equipped with software so that users can develop application-specific test routines and execute them from either the instrument itself or from a PC. Connecting a computer to an instrument to log data provides records of test data, which ISO and other standards are making necessary.Some examples of software that ships with test instrumentation include Test Script Builder (TSB) and LabTracer from Keithley for the Series 2600 SourceMeter instruments and Benchlink from Agilent, which ships with 34XXX series instruments, and Jitter Analysis Software from Tektronix.LabTracer is a Windows-based application that controls the instruments and allows simultaneous use of up to eight source-meter instruments for collecting, time stamping, and graphing voltage and/or current readings. Benchlink controls the instrument, permits scanning of multiple channels, and logs and graphs data. Jitter Analysis Software is used with Tektronix oscilloscopes to capture and analyze data and make accurate jitter measurements.Along with increased software use and programmability options, there are a host of standard communication interfaces available to ease transfer and collection of recorded data. Two examples are VISA and IVI.VISA is a software layer that standardizes communication between test instruments and different buses, including GPIB, serial links, and Ethernet. It lets programmers and users choose different buses for communication within the same program.IVI is a level of standardization for instruments of the same type DMMs, sources, and so forth that sits atop VISA. It permits, for instance, a DMM from Keithley respond to the same program calls as a DMM from Agilent.Adaptability Today, test bench instruments need to be easily and quickly customizable for a number of different measurement tasks. Flexibility is a must, especially with shorter engineering cycles and tighter instrumentation budgets.A basic instrument can be tailored to any number of specific measurement tasks with the help of embedded scripting. Basically this allows an instrument to execute a specified number of source and measure functions repeatedly. For instance, an individual instrument can be set up as a thermal impedance meter, LXI test system, or a small-scale functional tester.Taking the measure of pulse generators In recent years, new testing techniques have been developed to meet the challenges posed by the rapid development of new standards in industries such as semiconductor and communication technology. One such technique is pulse testing.Pulse testing Testing advanced semiconductor devices, as well as RF devices such as high-speed serial communications links, are among the many uses for instruments with pulse capabilities. Pulse or pattern generators are used in a wide variety of applications in both the lab and on the production line.Researchers often need to stimulate a device under test (DUT) with a pulse, series of p ulses, or known data patterns at specified rates in order to characterize device performance. For instance, a pulse generator can deliver a single pulse that can be used for transient testing, to determine a device's transfer function and thereby characterize the material under test. Pulse or pattern generators are often configured into test systems that also include source-measure units, digital multimeters, voltmeters, switches, and oscilloscopes.Need for pulse testing The desire for higher operating speeds in electronic circuits has resulted in shrinking device geometries and the use of new materials and more complex designs. These changes bring with them higher power density and the potential for increased fragility and new failure mechanisms, all of which can have a tremendous impact on device life. Also, analog components used in these circuits behave differently at higher speeds, so they can't be characterized using traditional dc testing methods.So to examine new designs, test equipment must be able to produce simulated clock and data signals at the higher operating speeds at which circuits will actually perform. Pulse sizes can be made extremely small on the order of a few nanoseconds and pulse testing can overcome problems inherent in dc testing techniques.In addition, as components have become smaller, the need for pulsed testing techniques becomes more critical. Smaller DUTs are more susceptible to self-heating, which can destroy or damage the part or change its response to test signals, masking the response the user is seeking. Pulse testing is commonly used when characterizing nanoelectronic devices.Advanced IC technologies incorporate new materials and failure mechanisms that traditional dc testing techniques may not be powerful enough to uncover. The limits of dc methods are apparent in charge-trapping behavior in gate dielectrics in semiconductor devices. The issue is the relatively long periods of time required for these dc techniques.During device development, structures like single-electron transistors (SETs), sensors, and other experimental devices often display unique properties. Characterizing these properties without damaging one-of-a-kind structures requires systems that provide tight control over sourcing to prevent device self-heating. Tocontrol the amount of energy delivered to a device, high amplitude accuracy and programmable rise and fall times are necessary.Voltage pulsing can produce much narrower pulse widths than current pulsing, so it's often used in experiments such as thermal transport, in which the timeframe of interest is shorter than a few hundred nanoseconds.What to look for Facilities involved in testing semiconductors, nanotechnology devices, and high speed components are faced with intense budget and time-to-market constraints. However, they cannot compromise on measurement quality, valuable rack or bench-top space, or ease of use. These designers need pulse generators that satisfy their current as well as future testing requirements.In addition to such parameters as pulse rise and fall times, the three key items to keep in mind while evaluating a pulse/pattern generator are flexibility, fidelity, and ease of use. The first, flexibility, is essential to a good pulse generator, because it lets users control critical signal parameters such as amplitude, offset, rise and fall times, pulse widths, and duty cycle of the output signal.Interdependency of these parameters can reduce the flexibility of the instrument; if you adjust one parameter, another parameter may change. It is essential for controlled testing that when you adjust, say, the rise-time of a pulse, its amplitude does not change. Independent control over key signal parameters makes an instrument flexible and useable in many different applications.A generator's fidelity is affected by the amount of overshoot or droop in a pulse, and it can make the instrument unsuitable for your application. Further, these undesirable effects can be worsened by the setup and cabling that your application requires. Using an instrument that minimizes these effects will help reduce these setup challenges.When considering an instrument's fidelity, look carefully at its specifications. Parameter such as rise-time or fall-time are typically specified at either 10% to 90% or 20% to 80%, but using 20% to 80% allows a slower pulse to appear to have a faster rise-time and the actual fidelity of the pulse could be significantly lower.Ease of use is a factor whose worth is often underestimated. After all, if a user interface is truly intuitive, it makes it much quicker for experienced test engineers as well as novices to get the job done.为频率捷变应用选择信号发生器根据信号发生器的主要用途或公司的预算，设计师通常会采用传统的信号发生器设计，如YIG调谐或带状合成器。

论文翻译A Precision frequency synthesis method by FPGAContentsA method of frequency measurement based on a closed loop composed mainly of a Frequency Comparator (FC) and a Direct Digital Synthesizer (DDS) is presented in this paper. The DDS serves as reference sinewave signal generator acting at one of the FC's inputs. The FC accepts the hard-limited waveform of the DDS as well as the unknown frequency. From the comparison of the two signals a logic output that controls an up/down counter is produced. The counter's output acting as the Frequency Setting Word (FSW) instructs the DDS to produce a new sinewave closer in frequency to the unknown one. When the loop settles, the FSW gives the digital estimate of the unknown frequency. Advantage is taken from the inherent high resolution of the DDS and noise immunity of the loop, to design an equally precise and immune frequency meter. All the additional associated stages up to the instrument's display are presented.1 IntroductionThe most commonly used frequency measurement technique adopts counters that count the pulses of the unknown frequency during a predefined time window (aperture). Apart from this, techniques where the pulses of a reference frequency are counted during one or more periods of the unknown one are also common. In the latter case, the period instead of the frequency is estimated .Some papers in the literature deal with the problem of low frequency measurement and are focusing in the frequency range of cardiac (heart) signals (a few hertz) or in the mains frequency (50-60 Hz).These techniques are actually measuring the period of the signals and use some way to calculate its reciprocal, the frequency. In the frequency is calculated by the method of look-up tables. Others are microprocessor or microcontroller based.The above methods can be characterized as open-loop methods i.e. digital counters are used to count during a predefined tinle interval and calculate the result afterwards. Its closed-loop form characterizes the proposed method in this paper. By the term "closed-loop" we denote some sort of feedback. A waveform with a known (controlled) frequency is produced within the circuit and is fed back to the frequency comparison stage which consecutively forces it to approximate the unknown (input) frequency. The device that produces the above mentioned waveform of controlled frequency is a Direct Digital Synthesizer.2 Direct Digital SynthesisA typical Direct Digital Synthesizer consists of a RAM containing samples of a sinewave (sine look-up table, LUT). These samples are swept in a controlled manner by the aid of a Frequency Setting Word (FSW), which determines the phase step. A typical FSW is 32-bit wide, but 48-bit synthesizers leading in higher frequency resolution are also available. A phase accumulatorproduces the successive addresses of the sine look-up table and generates a digitized sine wave output. The digital part of the DDS, the phase accumulator and the LUT, is called Numerically Controlled Oscillator (NCO). The final stage, which in contrast to the previous one is mostly analog, consists of a D/A converter followed by a filter. The filter smoothes the digitized sinewave, producing a continuous output signal. In the applications where a square wave output is needed, this is obtained by a hard limiter after the filter. It is not equivalent to use e.g. the MSB of the accumulator's output instead of the filtered and hard limited waveform because significant jitter will be encountered.The frequency of the output signal for an n-bit system is calculated in the following way; If the phase step is equal to one, the accumulator will count by ones, taking clock cycles to address the entire LUT and to generate one cycle of the output sinewave. This is the lowest frequency that the system can generate and is also its frequency resolution. Setting the FSW equal to two, results in the accumulator counting by twos, taking clock cycles to complete one cycle of the outputsinewave. It can easily be shown that for any integer m, where m<, the number of clock cycles taken to generate one cycle of the output sine wave is /m, and the output frequency (fDDS) andthe frequency resolution (fres) are given by the following formulas ：f DDS = f res = f clk / For n = 32 and having a clock frequency of fclk = 33 MHz, the frequency resolution is 7.68 mHz. If n is increased to 48, with the same clock frequency, a resolution of 120 nHz is possible. 3 The proposed frequency measurement technique The idea that led to our present design came from the extremely high frequency resolution of the DDS devices and is enforced by the noise immunity of its closed loop form. A (known) frequency source, the DDS, is employed in a closed loop and is forced progressively to produce an output with a frequency equal to the unknown input . A rule of thumb in the DDS systems is that the maximum acceptable synthesized frequency is about 25% of the clock frequency (well below the Nyquist limit). According to this, our prototype that uses a 33 MHz clock would effectively count up to 8 MHz. Looking at the GaAs products, we can see that recently available DDS devises can operate at clock frequencies up to the extent of 400 MHz. Therefore, by the present method, frequency counters working up to 100 MHz can be designed. The resolution will depend on the number of FSW bits and the clock frequency. The clock frequency fclk of the DDS is very critical because as it decreases, the resolution of the proposed method (defined as fclk/) becomes finer i.e. it improves. The impact of the clock frequency decrease is the subsequent decrease of its maximum output frequency that limits the counter's maximum count. The major blocks have been 2n 12n -12n -2n 2n m fclk⨯2n2nshown . Among them are the Frequency Comparator and the DDS. To overcome some disadvantages of the specific frequency comparator a correction stage has been incorporated. This stage is also used for the measurement extraction in order to display the correct reading.3.1 Operation of the circuitThe circuit operates in such a way that at the beginning of a new measurement the DDS output frequency would be controlled in a successive approximation way. The initial DDS frequency would be half of it's maximum. In addition, the frequency step of the approximation would equal the 1/4 of the DDS maximum frequency. On every approximation the frequency step is divided by two and added or subtracted to the FSW of the DDS, depending on the output of the Frequency Comparator. The approximation procedure stops when the step size decreases to one. After that, an up/down counter substitutes the approximation mechanism.The digital FSW, after the appropriate correction and decoding, is presented in an output device i.e. an LCD display or any other suitable means. Alternatively, it can be digitally recorded or it can be read by a computer.As conclusion of this initial approach we could say that the proposed method is based on a Digital Controlled Synthesizer which is forced to produce a frequency almost equal to the unknown one.3.2 Frequency comparisonThe frequency comparator seems to be the most critical stage of the design. The implementation is based on a modified phase/frequency comparator proposed by Philips in the 74HC4046 PLL device. It consists primarily of two binary counters, counting up to two and an RS flip-flop.The function of the frequency comparator is based on the principle that the lower frequency, i.e. larger period, includes (embraces) at least one or more full periods of the higher frequency (smaller period). This means that two or more rising edges of the higher frequency waveform are included within the lower frequency period. Considering the above, the circuit operates as follows: When the first counter (#1) encounters two rising edges of the unknown frequency in one period of the DDS, it sets the output of the RS flip-flop. The logic "1" of the RS flip-flop acting at the U/D control input of the Up/Down counter forces the DDS to rise its output frequency. On the contrary, when the second counter (#2) counts two rising edges of the DDS output within a period of the unknown frequency it resets the RS flip-flop's output. This action decreases the frequency of the DDS.At a first glance one could think that the synthesized frequency could reach the measured one (fin) and then the operation of the counter stops. Unfortunately this is not the case. A dynamic mechanism takes place instead. The circuit needs some time to realize the correct frequency relation. We will refer to this time as "hysteresis". Hysteresis depends on the initial timing relation of the DDS output and on the unknown frequency. Initially, during the hysteresis period, the indication regarding the larger frequency is ambiguous i.e. it can be erroneous. The ambiguity settles whentwo rising edges of the higher frequency waveform occur during one period of the lower one. If we consider the case of the DDS frequency to be equal to the unknown one, we will find that the comparator's output will toggle, indicating alternatively that the DDS frequency is higher or lower than the unknown. This is actually an acceptable and expected condition,because (as in a voltage comparator) an equality indication could not exist. In our case this is not a problem because the circuit is embedded in a closed loop. The loop will act in a manner that after some short time, the hysteresis, the situation will be reversed and so on. The duration of hysteresis is variable. This situation is controlled, as will be explained later. Although an analog implementation of the frequency comparator would look more robust to noise we insisted to the digital implementation for three reasons: ease of implementation in VLSI or Programmable Logic Devices (PLDs) with no need of analog components, wide frequency range of operation and shorter response time.3.3 Interaction between frequency comparator and digital synthesizerAfter the successive approximation of the unknown frequency the Frequency Comparator "realizes" that the synthesized frequency is higher (lower) than the unknown one and produces a logic 0 (1) at the output which commands the up/down counter to count in the down (up) direction. As previously mentioned, the output of this counter is considered to be the FSW to the DDS stage. In the case when the DDS frequency was initially lower, the synthesized frequency will increase progressively to reach the unknown one. This will not be "realized" by the frequency comparator and the synthesized frequency will keep on increasing for some clock cycles, until the comparator detects the correct relation of it's two input frequencies, the unknown one and the DDS output. The same phenomenon will be observed for the opposite (decreasing) case also. This is due to hysteresis that was mentioned earlier.When DDS output (f DDS) has approached fin, due to hysteresis, no specific frequency is synthesized. Instead, it swings between f1 and f2, where f1 and f2are the two extreme values of the frequency swing lying symmetrically around fin. The DDS output can be considered as a frequency modulated carrier by a triangular waveform. The triangular waveform is the analog representation of the FSW applied to the DDS. lower trace shows a typical output of the Frequency Comparator. In the same figure, upper trace, is shown in analog form the FSW variation as it is trying to approach the correct value. This waveform has been captured using an auxiliary hardware circuit: A digital-to-analog converter (DAC) was connected to the output of the U/D counter (MSBs) in order to study the operation. This DAC is not shown in the block diagram of the circuit. Stated differently, the lower trace is the U/D command (input) to the counter while the upper trace is a hypothetical "frequency modulating" waveform. It is obvious that the term "hypothetical" is used because there is not such a waveform available somewhere in the circuit (except for the auxiliary DAC). Instead, its numerical equivalent exists. The magnitude of the slope of the elements of the triangular waveform is constant for constant input frequency and depends on the clock of the U/D counter(horizontal axis) and the voltage reference of the DAC (vertical axis). This slope is k • fin.3.4 Description of the prototype hardwareFor evaluation purposes two prototypes have been built and tested in the laboratory. The first approach was a low frequency instrument (operating up to 15 KHz) . The purpose of this implementation was to study the principles of operation of the proposed method. Next, a higher frequency prototype was built which will be described in more detail here. In order to implement the digital part of the prototype, (Frequency Comparator, Successive Counter, Correction Stage) two PLD devices from Altera (EPF 8064LC68-12) were used. These devices are interconnected with the DDS, which is the Q2240I-3S1 from Qualcomm. The DDS has a 32-bit input and a 12-bit output for the sine lookup table (LUT). The 12-bit output of the LUT is fed into the D/A converter, the AD9713B from Analog Devices. Its analog output is connected to an I/V amplifier (current-to-voltage converter).The generated sinewave has upper harmonics, due to the DAC operation. These harmonics are removed from the filters that follow the DAC. The correction stage is implemented partially on the PLDs and partially on the microcontroller. Based on the up-down command of the frequency comparator we store the two extreme values, FSW1 and FSW2, which are then transferred into the micro-controller (Atmel AT89C52), transformed into numerical representation and fed to the LCD Display. The micro-controller also controls the whole operation of the prototype.The behaviour of the instrument was according to the expected and was alike to a conventional bench frequency counter. The speed of measurement was checked using lower trace, obtained by the aid of a digital oscilloscope. Each state, high or low, of this waveform corresponds to the time required for one measurement.4 ConclusionIn this paper an alternative method of frequency measurement has been proposed. It has been pointed out that in most cases this method is faster than conventional methods for the same frequency resolution. On the other hand, the precision of the method can be very high due to the inherent high frequency resolution characteristic of the DDS that is employed. This synthesizer, which can be thought as an oscillator, is driven to "oscillate" in the region of the unknown input frequency. A comparison with conventional methods has been given and two prototypes have been built and tested in the laboratory.The second major advantage of this method is that if repetitive frequency measurements are to be taken, the instrument remains locked and the frequency measurement does not restart from the beginning, but instead is automatically driven to lower or higher values. In other words, the loop has the capability to follow the changes in the frequency of the input signal. In the conventional counting techniques the counting procedure is repeated (restarted) for each new measurement.Another important advantage is the noise immunity of the system, due to its closed loop nature.A detailed study of the noise behavior has not been carried out in this paper. This is mainly because the aim of this text is to present an alternative principle of frequency measurement. Moreover, thefinal output of the system is taken after some further processing (measurement correction) which also contributes to the noise immunity.。

毕业设计（论文）设计(论文)题目基于FPGA的微处理器设计摘要本文使用结构化编程方法，将微处理器内核按照功能划分为不同的模块，采用VHDL语言设计每一个模块的内部功能和外围接口，设计实现了一种基于FPGA芯片的微处理器系统。

该微处理器主要由控制器、运算器和寄存器组成，具有指令控制、操作控制、时间控制和数据加工等基本功能，可实现四位操作数的各种运算，其指令长度为16位定长，采用了直接寻址方式。

最后采用QUARTUSII对设计进行了仿真测试，结果表明设计实现了微处理器的主要功能。

关键字：FPGA，微处理器，VHDLABSTRACTA microprocessor on FPGA is realized by using structured programming. This microprocessor core is divided into several different function modules which are designed using VHDL.The microprocessor consists of controller, arithmetic unit and registers. It realizes the instruction control, operation control, time sequence control and data processing functions. The direct addressing mode is adopted. The various operations for 4bit operand can be achieved. Its instruction length is 16 bit.The design is simulated by using QUARTUSII, and the results show that the main functions of a microprocessor are achieved.Key Words:FPGA, CPU, VHDL目录摘要............................................................................................................................................. I I ABSTRACT..................................................................................................................................... I II 第1章绪论. (1)背景 (1)微处理器的概况 (1)课题研究方法及技术背景 (1)研究方法 (1)技术背景 (2)课题工作内容 (3)第二章微处理器体系结构 (4)CPU的功能和构成 (4)指令系统分析 (5)RISC 与总线结构 (5)指令系统 (6)指令时序分析 (8)RISC与流水线 (8)程序计数器与流水线 (8)CPU整体结构即设计思想 (9)CPU的外部引脚规划 (9)CPU的整体框图 (10)CPU结构的层次划分 (11)第三章CPU数据通路设计 (12)程序计数器模块PC (12)程序存储器PC_RAM (13)指令寄存器模块 (14)时钟发生器模块 (14)寄存器堆TRAM (15)ALU模块 (16)第四章CPU控制单元的设计 (18)控制器Control模块 (18)有限状态机FSM模块 (19)有限状态机 (19)利用的VHDL语言进行状态机描述 (19)第五章RISC CPU的仿真验证 (21)各模块的组合 (21)综合RTL电路图 (21)RISCCPU的功能仿真验证 (24)算术运算类指令验证 (24)逻辑运算类指令验证 (25)移位类指令验证 (25)LD数据输出指令仿真 (26)ST运算数据存储仿真 (26)总结 (27)第六章总结和展望 (28)参考文献 (29)致谢 ...................................................................................................................错误!未定义书签。

使用LabVIEW FPGA模块开发可编程自动化控制器学院：通信与电子工程学院班级：电子071学号： 2007131010姓名：欧洪材Building Programmable Automation Controllers with LabVIEWFPGAOverviewProgrammable Automation Controllers (PACs) are gaining acceptance within the industrial control market as the ideal solution for applications that require highly integrated analog and digital I/O, floating-point processing, and seamless connectivity to multiple processing nodes. National Instruments offers a variety of PAC solutions powered by one common software development environment, NI LabVIEW. With LabVIEW, you can build custom I/O interfaces for industrial applications using add-on software, such as the NI LabVIEW FPGA Module.With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instruments delivers an intuitive, accessible solution for incorporating the flexibility and customizability of FPGA technology into industrial PAC systems. You can define the logic embedded in FPGA chips across the family of RIO hardware targets without knowing low-level hardware description languages (HDLs) or board-level hardware design details, as well as quickly define hardware for ultrahigh-speed control, customized timing and synchronization, low-level signal processing, and custom I/O with analog, digital, and counters within a single device. You also can integrate your custom NI RIO hardware with image acquisition and analysis, motion control, and industrial protocols, such as CAN and RS232, to rapidly prototype and implement a complete PAC system.Table of Contents1.Introduction2.NI RIO Hardware for PACs3.Building PACs with LabVIEW and the LabVIEW FPGA Module4.FPGA Development Flowing NI SoftMotion to Create Custom Motion Controllers6.Applications7.ConclusionIntroductionYou can use graphical programming in LabVIEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices. RIO technology, the merging of LabVIEW graphical programming with FPGAs on NI RIOhardware, provides a flexible platform for creating sophisticated measurement and control systems that you could previously create only with custom-designed hardware.An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can configure and reconfigure the logic on FPGAs for your specific application. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. The flexible,software-programmable architecture of FPGAs offer benefits such ashigh-performance execution of custom algorithms, precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. While FPGAs are often used in industrial control products, FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complex design tools used more by hardware design engineers than by controlengineers.Within the test-fixture the tx output of the transmitter module is loop ed back to the rx input of the receiver module.This allows the transmitter module to be used as test signal generator for the receiver module.Data can be written in parallel format to the transmitter module and looped back in serial format to the rx input of the receiver module,and data received can finally be read out in paral lel format from the receiver module.In order to automate the testing of the UART a s much as possible,tree independent Verilog tasks were written as follows.The Ve rilog task“write_to_transmitter”holds all necessary statements required to generate a s ingle parallel data write sequence to the transmitter module.Data that are writt en to the transmitter upon execution of the“write_to_transmitter”task,get la tched internal to the test-fixture for later analysis.The Verilog task“read_ou t_receiver”holds all necessary statements required to generate a single paral lel data read out sequence from the receiver module.Data that are read out of the receiver upon execution of the“read_out_receiver”task,get latched internalto the test-fixture for later analysis.The Verilog task“compare_data”holds a ll necessary statements required to compare the previous data written to the tran smitter module,to the corresponding and most recent data received and read out f rom the receive r module.If any discrepancy occurs,the“compare_data”task fl ags for an error by writing out the data values that were written to the transmitte r module,as well as the corresponding data values that were received by and read o ut from the receiver module.The simulation is immediately stopped by the“compa re_data”task if any discrepancy occurs.Besides the tree above mentioned Verilo g tasks,the test-fixture holds the statements to generate the mclkx16,the master reset signals as well as the“tx to rx”loop back feature.The statements are c onsidered trivial,and will not be illustrated here,but can be referred to within the test-fixture itself.The core of the test-fixture is a behavioral level“for loop”that executes the tree above mentioned Verilog tasks in order to write all possible data combinations to the transmitter and verify that same data gets prop erly received by the receiver.The for loop is showed below in figure21.Next to port definitions comes port directions.Directions are specified as in put,output or inout(bidirectional),and can be referred to in table1.Next to the specification of port directions comes declaration of internal signals.Inter nal signals in Verilog are declared as“wire”or“reg”data types.Signals of the“wire”type are used for continuos assignments,also called combinatorial s tatements.Signals of the“reg”type are used for assignments within the Verilog“always”block,often use for sequential logic assignments,but not necessari ly.For further explanation see aVerilog reference book.Data types of the internal signals of the module can be referred to in table3.We have now passed by all nec essary declarations,and are now ready to look at the actual ing hardware description language allows us to describe the function of the transm itter in a more behavioral manner,rather than focus on it’s actual implementation at gate level In software programming language, functions and procedures breaks larger programs into more readable,manageable and certa inly maintainable pieces.The Verilog language provides functions and tasks as co nstructs,analogous to software functions and procedures.A Verilog function andtask are used as the equivalent to multiple lines of Verilog code,where certain i nputs or signals affects certain outputs or variables.The use of functions and ta sks usually takes place where multiple lines of code are repeatedly used in a desi gn,and hence makes the design easier to read and certainly maintain.A Verilog fu nction can have multiple inputs,but always have only one output,while the Veril og task can have both multiple inputs,and multiple outputs and even in some cases,non of each.Below is shown the Verilog task,that hold all necessary sequential statements,to describe the transmitter in the“shift”modeWith the LabVIEW FPGA Module and NI RIO hardware, you now can use LabVIEW, a high-level graphical development environment designed specifically for measurement and control applications, to create PACs that have the customization, flexibility, and high-performance of FPGAs. Because the LabVIEW FPGA Module configures custom circuitry in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically. Figure 1 illustrates many of the NI RIO devices that you can configure using the LabVIEW FPGA Module.Figure 1. LabVIEW FPGA VI Block Diagram and RIO Hardware PlatformsNI RIO Hardware for PACsHistorically, programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools, which require overcoming a very steep learning curve. With the LabVIEW FPGA Module, NI has opened FPGA technology to a broader set of engineers who can now define FPGA logic using LabVIEW graphical development. Measurement and control engineers can focus primarily on their test and control application, where their expertise lies, rather than the low-level semantics of transferring logic into the cells of the chip. The LabVIEW FPGA Module model works because of the tight integration between the LabVIEW FPGA Module and the commercial off-the-shelf (COTS) hardware architecture of the FPGA and surrounding I/O components.National Instruments PACs provide modular, off-the-shelf platforms for your industrial control applications. With the implementation of RIO technology on PCI, PXI, and Compact Vision System platforms and the introduction of RIO-based CompactRIO, engineers now have the benefits of a COTS platform with thehigh-performance, flexibility, and customization benefits of FPGAs at their disposal to build PACs. National Instruments PCI and PXI R Series plug-in devices provide analog and digital data acquisition and control for high-performance, user-configurable timing and synchronization, as well as onboard decision making on a single device. Using these off-the-shelf devices, you can extend your NI PXI or PCI industrial control system to include high-speed discrete and analog control, custom sensor interfaces, and precise timing and control.NI CompactRIO, a platform centered on RIO technology, provides a small, industrially rugged, modular PAC platform that gives you high-performance I/O and unprecedented flexibility in system timing. You can use NI CompactRIO to build an embedded system for applications such as in-vehicle data acquisition, mobile NVH testing, and embedded machine control systems. The rugged NICompactRIO system is industrially rated and certified, and it is designed for greater than 50 g of shock at a temperature range of -40 to 70 °C.NI Compact Vision System is a rugged machine vision package that withstands the harsh environments common in robotics, automated test, and industrial inspection systems. NI CVS-145x devices offer unprecedented I/O capabilities and network connectivity for distributed machine vision applications.NI CVS-145x systems use IEEE 1394 (FireWire) technology, compatible with more than 40 cameras with a wide range of functionality, performance, and price. NI CVS-1455 and NI CVS-1456 devices contain configurable FPGAs so you can implement custom counters, timing, or motor control in your machine vision application.Building PACs with LabVIEW and the LabVIEW FPGA ModuleWith LabVIEW and the LabVIEW FPGA Module, you add significant flexibility and customization to your industrial control hardware. Because many PACs are already programmed using LabVIEW, programming FPGAs with LabVIEW is easy because it uses the same LabVIEW development environment. When you target the FPGA on an NI RIO device, LabVIEW displays only the functions that can be implemented in the FPGA, further easing the use of LabVIEW to program FPGAs. The LabVIEW FPGA Module Functions palette includes typical LabVIEW structures and functions, such as While Loops, For Loops, Case Structures, and Sequence Structures as well as a dedicated set of LabVIEW FPGA-specific functions for math, signal generation and analysis, linear and nonlinear control, comparison logic, array and cluster manipulation, occurrences, analog and digital I/O, and timing. You can use a combination of these functions to define logic and embed intelligence onto your NI RIO device.Figure 2 shows an FPGA application that implements a PID control algorithm on the NI RIO hardware and a host application on a Windows machine or an RT target that communicates with the NI RIO hardware. This application reads from analog input 0 (AI0), performs the PID calculation, and outputs the resulting data on analog output 0 (AO0). While the FPGA clock runs at 40 MHz the loop in this example runs much slower because each component takes longer than one-clock cycle to execute. Analog control loops can run on an FPGA at a rate of about 200 kHz. You can specify the clock rate at compile time. This example shows only one PID loop; however, creating additional functionality on the NI RIO device is merely a matter of adding another While Loop. Unlike traditional PC processors, FPGAs are parallel processors. Adding additional loops to your application does not affect the performance of your PID loop.Figure 2. PID Control Using an Embedded LabVIEW FPGA VI with Corresponding LabVIEW HostVI.FPGA Development FlowAfter you create the LabVIEW FPGA VI, you compile the code to run on the NI RIO hardware. Depending on the complexity of your code and the specifications of your development system, compile time for an FPGA VI can range from minutes to several hours. To maximize development productivity, with the R Series RIO devices you can use a bit-accurate emulation mode so you can verify the logic of your design before initiating the compile process. When you target the FPGA Device Emulator, LabVIEW accesses I/O from the device and executes the VI logic on the Windows development computer. In this mode, you can use the same debugging tools available in LabVIEW for Windows, such as execution highlighting, probes, and breakpoints.Once the LabVIEW FPGA code is compiled, you create a LabVIEW host VI to integrate your NI RIO hardware into the rest of your PAC system. Figure 3 illustrates the development process for creating an FPGA application. The host VI uses controls and indicators on the FPGA VI front panel to transfer databetween the FPGA on the RIO device and the host processing engine. These front panel objects are represented as data registers within the FPGA. The host computer can be either a PC or PXI controller running Windows or a PC, PXI controller, Compact Vision System, or CompactRIO controller running a real-time operating system (RTOS). In the above example, we exchange the set point, PID gains, loop rate, AI0, and AO0 data with the LabVIEW host VI.Figure 3. LabVIEW FPGA Development FlowThe NI RIO device driver includes a set of functions to develop a communication interface to the FPGA. The first step in building a host VI is to open a reference to the FPGA VI and RIO device. The Open FPGA VI Reference function, as seen in Figure 2, also downloads and runs the compiled FPGA code during execution. After opening the reference, you read and write to the control and indicator registers on the FPGA using the Read/Write Control function. Once you wire the FPGA reference into this function, you can simply select which controls and indicators you want to read and write to. You can enclose the FPGA Read/Write function within a While Loop to continuously read and write to the FPGA. Finally, the last function within the LabVIEW host VI in Figure 2 is the Close FPGA VI Reference function. The Close FPGA VI Reference function stops the FPGA VI and closes the reference to the device. Now you can download other compiled FPGA VIs to the device to change or modify its functionality.The LabVIEW host VI can also be used to perform floating-point calculations, data logging, networking, and any calculations that do not fit within the FPGA fabric. For added determinism and reliability, you can run your host application on an RTOS with the LabVIEW Real-Time Module. LabVIEW Real-Time systems provide deterministic processing engines for functions performed synchronously or asynchronously to the FPGA. For example, floating-point arithmetic, including FFTs, PID calculations, and custom control algorithms, are often performed in the LabVIEW Real-Time environment. Relevant data can be stored on a LabVIEW Real-Time system or transferred to a Windows host computer for off-line analysis, data logging, or user interface displays. The architecture for this configuration is shown in Figure 4. Each NI PAC platform that offers RIO hardware can run LabVIEW Real-Time VIs.Figure 4. Complete PAC Architecture Using LabVIEW FPGA, LabVIEW Real-Time and Host PC Within each R Series and CompactRIO device, there is flash memory available to store a compiled LabVIEW FPGA VI and run the application immediately upon power up of the device. In this configuration, as long as the FPGA has power, it runs the FPGA VI, even if the host computer crashes or is powered down. This is ideal for programming safety power down and power up sequences when unexpected events occur.Using NI SoftMotion to Create Custom Motion ControllersThe NI SoftMotion Development Module for LabVIEW provides VIs and functions to help you build custom motion controllers as part of NI PAC hardware platforms that can include NI RIO devices, DAQ devices, and Compact FieldPoint. NI SoftMotion provides all of the functions that typically reside on a motion controller DSP. With it, you can handle path planning, trajectory generation, and position and velocity loop control in the NI LabVIEW environment and then deploy the code on LabVIEW Real-Time or LabVIEW FPGA-based target hardware.NI SoftMotion includes functions for trajectory generator and spline engine and examples with complete source code for supervisory control, position, and velocity control loop using the PID algorithm. Supervisory control and the trajectory generator run on a LabVIEW Real-Time target and run at millisecond loop rates. The spline engine and the control loop can run either on a LabVIEW Real-Time target at millisecond loop rates or on a LabVIEW FPGA target at microsecond loop rates.ApplicationsBecause the LabVIEW FPGA Module can configure low-level hardware design of FPGAs and use the FPGAs within in a modular system, it is ideal for industrial control applications requiring custom hardware. These custom applications can include a custom mix of analog, digital, and counter/timer I/O, analog control up to 125 kHz, digital control up to 20 MHz, and interfacing to custom digital protocols for the following:Batch control∙Discrete control∙Motion control∙In-vehicle data acquisition∙Machine condition monitoring∙Rapid control prototyping (RCP)∙Industrial control and acquisition∙Distributed data acquisition and control∙Mobile/portable noise, vibration, and harshness (NVH) analysis ConclusionThe LabVIEW FPGA Module brings the flexibility, performance, and customization of FPGAs to PAC platforms. Using NI RIO devices and LabVIEW graphical programming, you can build flexible and custom hardware using the COTS hardware often required in industrial control applications. Because you are using LabVIEW, a programming language already used in many industrial control applications, to define your NI RIO hardware, there is no need to learn VHDL or other low-level hardware design tools to create custom hardware. Using the LabVIEW FPGA Module and NI RIO hardware as part of your NI PAC adds significant flexibility and functionality for applications requiring ultrahigh-speed control, interfaces to custom digital protocols, or a custom I/O mix of analog, digital, and counters.使用LabVIEW FPGA（现场可编程门阵列）模块开发可编程自动化控制器综述工业控制上的应用要求高度集成的模拟和数字输入输出、浮点运算和多重处理节点的无缝连接。

基于FPGA数字信号音频处理The Digital Signal Processing of audio based on FPGA摘要：目前，随着电子技术的快速发展人们对MP3多媒体播放器、DVD音频唱盘、Iphone等的音质、体积、功耗和处理速度有了更多更高要求。

因此现在数字音频处理技术已经逐渐取代模拟音频处理技术，并且得到了迅速的普及应用。

音频处理的数字化是利用数字滤波算法对采集的音频信号进行变换处理来实现，对此在本文中介绍了数字滤波器的一些算法。

傅里叶变换（DFT）作为其数字信号处理中的基本运算，发挥着重要作用。

特别是可快速傅里叶变换换（FFT）算法的提出，减少了当N很大的时候DFT的运算量，使得数字信号处理的实现与应用变得更加容易。

由于快速傅里叶变换算法在实际中得到了广泛应用，毕业设计给出了基-2FFT原理、讨论了按时间抽取FFT算法的特点。

本文主要探讨了基于FPGA数字信号音频处理的理论与实现，涉及到了其结构与设计流程、硬件描述语言（VHDL）、Quartus II软件、音频录放、DE2开发板介绍等等。

关键词：音频处理技术、数字滤波、算法、FPGAAbstractAt present,with the rapid development of the electronic technology,people have many higher requirements such as sound quality,volume,power waste and processing speed to the MP3 multimedia,DVD audio disc,Iphone and so on.So nowadays,the analog audio processing technology is replaced gradually by the digital audio processing technology,and digital audio processing technology has a chance to become common and widely used.The audio processing digitization is using the digital filter algorithm to sample.In the part of this passage there are some introduction about the digital filter algorithm. DFT plays an important part in digital signal processing as a basic calculation.Especially,FFT algorithm reduces the calculation quantity when N is a little great ,which makes it much easier for implement and application.As the fast Fourier transform algorithm in practice to a wide range of applications，radix-2 FFT theory has been given out and the characteristic of DIT FFT are discussed in the design of graduation.The passage mainly probes into the theories and realization of the digital signal processing of audio based on FPGA(Field Programmable Gate Array),including its structure and processing of design.It also contains VHDL，Quartus II software ，audio record and broadcast,introduction of DE2 study board and so on.Keywords:audio processing technology、digital filter、algorithm、FPGA前言第一章绪论1.1音频处理技术概述在科技飞速发展的数字化时代，数字音频技术是数字信号处理中应用最为广泛的数字技术之一。

Building Programmable Automation Controllers with LabVIEWFPGAOverviewProgrammableAutomation Controllers (PACs) are gaining acceptancewithin the industrial control marketasthe ideal solution for applications that require highly integrated analogand digital I/O, floating-point processing,and seamlessconnectivity to multiple processingnodes.National Instrumentsoffers a variety of PAC solutions poweredby one common software developmentenvironment, NI LabVIEW. With LabVIEW, you can build custom I/O interfacesfor industrial applications using add-on software, such asthe NI LabVIEW FPGA Module.With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instrumentsdelivers an intuitive, accessiblesolution for incorporating the flexibility and customizability of FPGA technology into industrial PAC systems.You can define the logic embeddedin FPGA chips acrossthe family of RIO hardware targetswithout knowing low- level hardware description languages(HDLs) or board-level hardwaredesign details, as well asquickly define hardwarefor ultrahigh-speedcontrol, customized timing and synchronization,low-level signal processing,and custom I/O with analog,digital, and counterswithin a single device. You also can integrate your custom NI RIO hardwarewith image acquisition and analysis,motion control, and industrial protocols, such asCAN and RS232,to rapidly prototype and implement a completePAC system.Table of Contents1.Introduction2.NI RIO Hardware for PACs3.Building PACswith LabVIEW andthe LabVIEW FPGA Module4.FPGA Development Flowing NI SoftMotion to CreateCustom Motion Controllers6.Applications7.ConclusionIntroductionYou can usegraphical programming in LabVIEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices.RIO technology, the merging of LabVIEW graphicalprogramming with FPGAs on NI RIO hardware,provides a flexible platform for creating sophisticatedmeasurementand control systemsthat you could previously createonly with custom-designedhardware.An FPGA is a chip that con sistsof many uncon figured logic gates.U nlike the fixed, vendor-definedfunctionality of an ASIC (application-specific integratedcircuit) chip, you can con figure an drec on figurethe logic on FPGAsfor your specificapplicati on. FPGAsareused in applicationswhere either the cost of developingand fabricating an ASIC is prohibitive, or the hardware must be rec on figured after being placed into service. The flexible, software- programmablearchitectureof FPGAs offer ben efits suchashigh-performa nceexecuti on of customalgorithms, precisetiming andsynchronization, rapid decisionmaking, and simultaneousexecutionof paralleltasks.Today,FPGAsappearin suchdevicesasinstruments,consumerelectronics,automobiles,aircraft, copy machines,andapplication-specific computerhardware.While FPGAs are ofte n used in in dustrial co ntrol products, FPGA fun ctio nality has not previously bee nm adeaccessibleto in dustrial con trol engin eers. Defining FPGAs hashistorically requiredexpertiseusing HDL programming or complex designtools usedmore by hardwaredesignengineersthanby control engineers.With the LabVIEW FPGA Module andNI RIO hardware,you now can useLabVIEW, a high-level graphicaldevelopmentenvironmentdesignedspecifically for measurementand con trol applicatio ns,to createPACsthat havethe customizati on flexibility, an dhigh- performa nceof FPGAs. Becausethe LabVIEW FPGA Module con figures custom circuitry in hardware,your systemca n processa nd gen erates ynchroni zeda nalog and digital sig nals rapidly and deterministically. Figure 1 illustratesmany of the NI RIO devicesthat you can con figure us ing the LabVIEW FPGA Module.Figure 1. LabVIEW FPGA VI Block Diagram and RIO Hardware PlatformsNI RIO Hardware for PACsHistorically, programmingFPGAshasbeenlimited to engineerswho havein-depth knowledgeof VHDL or other low-level designtools, which requireovercoming a very steep learni ng curve. With theLabVIEW FPGA Module, NI hasope nedFPGAtech no logytoa broadersetof engineerswho cannow define FPGA logic using LabVIEW graphical development.Measurementandcontrol engineerscanfocus primarily on their test andcontrol application, wheretheir expertiselies, ratherthanthe low-level semanticsoftransferring logic into the cells of the chip. The LabVIEW FPGA Module model works becauseof the tight integration betweenthe LabVIEW FPGA Module andthe commercialoff-the-shelf (COTS) hardwarearchitectureof the FPGA and surrounding I/O components.National InstrumentsPACsprovide modular, off-the-shelf platforms for your industrial control applications.With theimplementation of RIO technology on PCI, PXI, and Compact Vision Systemplatforms andthe introduction of RIO-based CompactRIO, engineersnow havethe benefits of a COTS platform with the high-performance,flexibility, and customizationbenefits of FPGAs at their disposalto build PACs.National InstrumentsPCI and PXI R Seriesplug-in devicesprovide analoganddigital dataacquisitionand control for high-performance,user-configurabletiming and synchronization, aswell as onboard decision making on a single device. Using theseoff-the-shelf devices,you canextendyour NI PXIor PCI industrial control systemto include high-speeddiscreteand analog control, custom sensorinterfaces,and precisetiming and control.NI CompactRIO,a platform centeredonRIO technology,provides a small, industrially rugged,modular PAC platform that gives you high-performanceI/O and unprecedented flexibility in systemtiming. You canuseNI CompactRIO to build an embeddedsystemfor applications such asin-vehicle dataacquisition, mobile NVH testing, and embeddedmachine control systems.The ruggedNI CompactRIO systemis industrially rated and certified, andit is designedfor greaterthan 50 g of shockat atemperaturerangeof -40to70°C.NI Compact Vision Systemis a rugged machinevision packagethat withstandsthe harsh environmentscommon in robotics, automatedtest,and industrial inspection systems.NI CVS-145x devices offer unprecedentedI/O capabilities andnetwork connectivity for distributed machinevision applications.NI CVS-145x systemsuseIEEE 1394 (FireWire) technology,compatible with more than40 cameraswith awide rangeof functionality, performance,and price. NI CVS-1455 and NI CVS-1456 devicescontain configurable FPGAs so you can implement custom counters,timing, or motor control in your machine vision application.Building PACswith LabVIEW andthe LabVIEW FPGA ModuleWith LabVIEW and the LabVIEW FPGA Module, you addsignificant flexibility and customizationto your industrial control hardware.Becausemany PACs are already programmedusing LabVIEW, programming FPGAs with LabVIEW is easybecauseit uses the sameLabVIEW developmentenvironment. When you target the FPGA on an NI RIO device, LabVIEW displaysonly the functions that can be implementedin the FPGA, further easingthe useof LabVIEW to programFPGAs. The LabVIEW FPGA Module Functions paletteincludes typical LabVIEW structuresand functions, such as While Loops, For Loops, CaseStructures,and SequenceStructuresas well as a dedicatedset of LabVIEW FPGA- specific functions for math, signal generationandanalysis,linear and nonlinear control, comparisonlogic, array and cluster manipulation, occurrences,analog and digital I/O, and timing. You canusea combination of thesefunctionsto definelogic and embedintelligence onto your NI RIO device.Figure 2 showsan FPGA application that implementsa PID control algorithm on theNI RIO hardwareanda host application on a Windows machineoranRT targetthat com muni cateswith the NI RIO hardware.This applicati on readsfrom an alogi nputO(AIO),performsthePID calculation,andoutputstheresulting dataonanalogoutput0 (AO0). While theFPGA clock run sat 40 MHz the loop i n this exampler un s much slower becauseeach componenttakeslongerthan one-clockcycle to execute.Analog control loops can run on an FPGA at a rate of about200 kHz. You can specify the clock rate at compile time. This exampleshowso nly on e PID loop; however,creat in gadditi on al f un cti on ality on the NI RIO device is merely a matter of adding anotherWhile Loop. Unlike traditional PC processors, FPGAs are parallel processorsAdd ing additi on al loops to your applicati on does not affect the performanceof your PID loop.LabVIEW FPGA VILabVIEW Host V!FPGA DevelopmentFlowAfter you createthe LabVIEW FPGA VI, you compile the code to run on the NI RIO hardware.Depending on the complexity of your code andthespecificationsof your developmentsystem,compiletime for an FPGA VI can rangefrom minutesto several hours. To maximize developmentproductivity, with the R SeriesRIO devicesyou canusea bit- Figure 2. PID Control Using an Embedded LabVIEW FPGA VI with Corresponding LabVIEW Host VI.accurateemulation modesoyou canverify the logic of your designbeforeinitiating the compile process.Whenyou targetthe FPGA Device Emulator, LabVIEW accesses/O from thedeviceand executesthe VI logic on the Windows developmentcomputer.ln this mode, you can usethe samedebuggingtools available in LabVIEW for Windows, such asexecution highlighting, probes, and breakpoints.Oncethe LabVIEW FPGA codeis compiled, you createa LabVIEW host VI to integrate your NI RIO hardware into the restof your PAC system.Figure 3 illustrates the development processfor creatingan FPGA application. The host VI usescontrols andindicators on the FPGA VI front paneltotransferdatabetweentheFPGA on the RIO device andthehost process ingengin e.Thesefr ont pan el objects are represe ntedasdataregisterswithi n the FPGA. ThehostcomputercanbeeitheraPCor PXI controller running Windows or aPC, PXI controller, CompactVision System,or CompactRIO controller running a real-time operatingsystem(RTOS).ln theaboveexample,we exchangethesetpoint, PID gains,loop rate,AI0, andAO0 datawith the LabVIEW hostVI.Creals FPGA VI Emukt* An Pt to恒針(R Series onlyiCompile to FPGA Creald Hcot Vl(s) Figure 3. LabVIEW FPGA Development FlowThe NI RIO device driver includesa setof functionsto developacommunication in terfaceto the FPGA. The first stepi n buildi ng a hostVI is to ope n a refere nceto theFPGA VI an d RIO device. The Ope nF PGA VI Refere ncefunction, assee nin Figure2, also downloadsand runsthe compiled FPGA codeduring execution.After opening the referenee, you read a nd write to the con trol andin dicator registers on the FPGA using the Read/Write Control function. Onceyou wire the FPGA referenceinto this function, you can simply select which con trols andin dicators you want to reada nd write to. You can en closethe FPGA Read/Writefunction within a While Loop to continuously readand write to the FPGA. Fin ally, the last fu nctio n within the LabVIEW hostVI in Figure 2 is the Close FPGA VI Referencefunction. The Close FPGA VI Referencefunction stopsthe FPGA VI and closes the referenceto the device. Now you can download other compiled FPGA VIs to thedeviceto changeor modify its functionality.The LabVIEW hostVI can alsobeusedto perform float in g-po int calculati on s, data logg ing, n etwork ing, andan y calculatio nsthatd ono tfit with in theFPGA fabric. For added determinismand reliability, you canrun your host application on an RTOSwith the LabVIEW Real-Time Module. LabVIEW Real-Time systemsprovide deterministicprocess ingengin esfor fun cti ons performeds ynchrono uslyor asyn chro no uslyto theFPGA. For example,floating-point arithmetic, including FFTs, PIDcalculations,andcustomccontrol algorithms, areoften performedin the LabVIEW Real-Time environment.Relevantdatacan be stored ona LabVIEW Real-Time systemor transferredto a Windows host computerfor off-line analysis,datalogging, or userinterfacedisplays. The architecturefor this configuration is shown in Figure 4. EachNI PAC platform that offers RIO hardware canrun LabVIEW Real-TimeVIs.Using NI SoftMotion to CreateCustom Motion ControllersThe NI SoftMotion Development Module for LabVIEW providesVIs andfunctions tohelp you build custommotion controllers aspartof NI PAC hardwareplatforms that can include NI RIO devices,DAQ devices,andCompact FieldPoint. NI SoftMotion provides all of the functions that typically resideon a motion controller DSP.With it, youcanhandlepath planning, trajectory generation,andposition andvelocity loop control in the NI LabVIEW environmentandthendeploy thecodeon LabVIEW Real-Time or LabVIEW FPGA-based targethardware.NI SoftMotion includesfunctionsfor trajectory generatorandsplineengineandexampleswith completesourcecodefor supervisorycontrol, position, andvelocity control loop usi ng the PID algorithm. Supervisoryc on trol an d the trajectory ge neratorr un on a LabVIEW Real-Timetargetand run atmillisecond loop rates.Thesplineengineandthe control loopcanrun eitheron aLabVIEW Real-Timetargetatmillisecond loop ratesoron a LabVIEW FPGA targetat microsec on dloop rates.Applicati onsBecausethe LabVIEW FPGA Module canconfigure low-level hardwaredesignof FPGAs and usethe FPGAs within in a modular system,it is ideal for in dustrial con trolapplicatio ns requiri ng custom hardware. Thesecustom applicati on sea n in elude a custom mix of analog,digital, andcounter/timer I/O, analogcontrol upto 125 kHz,ItHostProgram Emtefprisi T«gertPtogiam FPSA HardwareFigure 4. Complete PAC Architecture Using LabVIEW FPGA, LabVIEW Real-Time and Host PCWith in eachR Seriesa nd CompactRIOdevice,thereis flash memory available tostorea compiled LabVIEW FPGA VI and run theapplicationimmediately upon power up of the device. In this configuration, aslong asthe FPGA haspower, it runsthe FPGA VI, even if the hostcomputercrashesor is powered down. This is ideal for programming safety power down andpowerup sequencewhen unexpectedeventsoccur.digital control up to 20 MHz, and interfacing to custom digital protocols for thefollowing:« Batch control・Discretec on trol・Motion control・In-vehicle dataacquisition・Machine condition monitoring«Rapid control prototyping (RCP)・In dustrial con trol an dacquisiti on« Distributed dataacquisition and control・Mobile/portable noise, vibration, andharshness(NVH) analysis Con clusi onThe LabVIEW FPGA Module bringsthe flexibility, performance,andcustomizationof FPGAsto PAC platforms. Using NI RIO devicesand LabVIEW graphical programming, you can build flexible an d custom hardwareusi ng the COTS hardwareofte n required i n in dustrial control applications.Becauseyou areusing LabVIEW, a programming Ianguagealreadyused in many in dustrial con trol applicati on s,to defi neyour NI RIO hardware,thereis non eedto lear nV HDL or other low-level hardwaredesig ntoolsto createcustom hardware. Usi ng the LabVIEW FPGA Module a ndNI RIO hardwareaspart of your NI PAC addssig nifica nt flexibility andfunctionality for applicationsrequiring ultrahigh-speedcontrol, interfacesto customdigital protocols, or a custom I/O mix of analog,digital, andcounters.使用LabVIEW FPGA （现场可编程门阵列）模块开发可编程自动化控制器综述工业控制上的应用要求高度集成的模拟和数字输入输出、浮点运算和多重处理节点的无缝连接。

Building Programmable Automation Controllers with LabVIEWFPGAOverviewProgrammable Automation Controllers (PACs) are gaining acceptance within the industrial control market as the ideal solution for applications that require highly integrated analog and digital I/O, floating-point processing, and seamless connectivity to multiple processing nodes. National Instruments offers a variety of PAC solutions powered by one common software development environment, NI LabVIEW. With LabVIEW, you can build custom I/O interfaces for industrial applications using add-on software, such as the NI LabVIEW FPGA Module.With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instruments delivers an intuitive, accessible solution for incorporating the flexibility and customizability of FPGA technology into industrial PAC systems. You can define the logic embedded in FPGA chips across the family of RIO hardware targets without knowinglow-level hardware description languages (HDLs) or board-level hardware design details, as well as quickly define hardware for ultrahigh-speed control, customized timing and synchronization, low-level signal processing, and custom I/O with analog, digital, and counters within a single device. You also can integrate your custom NI RIO hardware with image acquisition and analysis, motion control, and industrial protocols, such as CAN and RS232, to rapidly prototype and implement a complete PAC system.Table of Contents1.Introduction2.NI RIO Hardware for PACs3.Building PACs with LabVIEW and the LabVIEW FPGA Module4.FPGA Development Flowing NI SoftMotion to Create Custom Motion Controllers6.Applications7.ConclusionIntroductionYou can use graphical programming in LabVIEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices. RIO technology, the merging of LabVIEW graphical programming with FPGAs on NI RIO hardware, provides a flexible platform for creating sophisticated measurement and control systems that you could previously create only with custom-designed hardware.An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can configure and reconfigure the logic on FPGAs for your specific application. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. The flexible, software-programmable architecture of FPGAs offer benefits such ashigh-performance execution of custom algorithms, precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, and application-specific computer hardware. While FPGAs are often used in industrial control products, FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complex design tools used more by hardware design engineers than by control engineers.With the LabVIEW FPGA Module and NI RIO hardware, you now can use LabVIEW, a high-level graphical development environment designed specifically for measurement and control applications, to create PACs that have the customization, flexibility, andhigh-performance of FPGAs. Because the LabVIEW FPGA Module configures custom circuitry in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically.NI RIO Hardware for PACsHistorically, programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools, which require overcoming a very steep learning curve. With the LabVIEW FPGA Module, NI has opened FPGA technology to a broader set of engineers who can now define FPGA logic using LabVIEW graphical development. Measurement and control engineers can focus primarily on their test and control application, where their expertise lies, rather than the low-level semantics oftransferring logic into the cells of the chip. The LabVIEW FPGA Module model works because of the tight integration between the LabVIEW FPGA Module and the commercial off-the-shelf (COTS) hardware architecture of the FPGA and surrounding I/O components.National Instruments PACs provide modular, off-the-shelf platforms for your industrial control applications. With the implementation of RIO technology on PCI, PXI, and Compact Vision System platforms and the introduction of RIO-based CompactRIO, engineers now have the benefits of a COTS platform with the high-performance, flexibility, and customization benefits of FPGAs at their disposal to build PACs. National Instruments PCI and PXI R Series plug-in devices provide analog and digital data acquisition and control for high-performance, user-configurable timing and synchronization, as well as onboard decision making on a single device. Using these off-the-shelf devices, you can extend your NI PXI or PCI industrial control system to include high-speed discrete and analog control, custom sensor interfaces, and precise timing and control.NI CompactRIO, a platform centered on RIO technology, provides a small, industrially rugged, modular PAC platform that gives you high-performance I/O and unprecedented flexibility in system timing. You can use NI CompactRIO to build an embedded system for applications such as in-vehicle data acquisition, mobile NVH testing, and embedded machine control systems. The rugged NI CompactRIO system is industrially rated and certified, and it is designed for greater than 50 g of shock at a temperature range of -40 to 70 °C.NI Compact Vision System is a rugged machine vision package that withstands the harsh environments common in robotics, automated test, and industrial inspection systems. NI CVS-145x devices offer unprecedented I/O capabilities and network connectivity for distributed machine vision applications.NI CVS-145x systems use IEEE 1394 (FireWire) technology, compatible with more than 40 cameras with a wide range of functionality, performance, and price. NI CVS-1455 and NI CVS-1456 devices contain configurable FPGAs so you can implement custom counters, timing, or motor control in your machine vision application.Building PACs with LabVIEW and the LabVIEW FPGA ModuleWith LabVIEW and the LabVIEW FPGA Module, you add significant flexibility and customization to your industrial control hardware. Because many PACs are alreadyprogrammed using LabVIEW, programming FPGAs with LabVIEW is easy because it uses the same LabVIEW development environment. When you target the FPGA on an NI RIO device, LabVIEW displays only the functions that can be implemented in the FPGA, further easing the use of LabVIEW to program FPGAs. The LabVIEW FPGA Module Functions palette includes typical LabVIEW structures and functions, such as While Loops, For Loops, Case Structures, and Sequence Structures as well as a dedicated set of LabVIEW FPGA-specific functions for math, signal generation and analysis, linear and nonlinear control, comparison logic, array and cluster manipulation, occurrences, analog and digital I/O, and timing. You can use a combination of these functions to define logic and embed intelligence onto your NI RIO device.This application reads from analog input 0 (AI0), performs the PID calculation, and outputs the resulting data on analog output 0 (AO0). While the FPGA clock runs at 40 MHz the loop in this example runs much slower because each component takes longer than one-clock cycle to execute. Analog control loops can run on an FPGA at a rate of about 200 kHz. You can specify the clock rate at compile time. This example shows only one PID loop; however, creating additional functionality on the NI RIO device is merely a matter of adding another While Loop. Unlike traditional PC processors, FPGAs are parallel processors. Adding additional loops to your application does not affect the performance of your PID loop.FPGA Development FlowAfter you create the LabVIEW FPGA VI, you compile the code to run on the NI RIO hardware. Depending on the complexity of your code and the specifications of your development system, compile time for an FPGA VI can range from minutes to several hours. To maximize development productivity, with the R Series RIO devices you can use a bit-accurate emulation mode so you can verify the logic of your design before initiating the compile process. When you target the FPGA Device Emulator, LabVIEW accesses I/O from the device and executes the VI logic on the Windows development computer. In this mode, you can use the same debugging tools available in LabVIEW for Windows, such as execution highlighting, probes, and breakpoints.Once the LabVIEW FPGA code is compiled, you create a LabVIEW host VI to integrate your NI RIO hardware into the rest of your PAC system. The host VI uses controls and indicators on the FPGA VI front panel to transfer data between the FPGA onthe RIO device and the host processing engine. These front panel objects are represented as data registers within the FPGA. The host computer can be either a PC or PXI controller running Windows or a PC, PXI controller, Compact Vision System, or CompactRIO controller running a real-time operating system (RTOS). In the above example, we exchange the set point, PID gains, loop rate, AI0, and AO0 data with the LabVIEW host VI.The NI RIO device driver includes a set of functions to develop a communication interface to the FPGA. The first step in building a host VI is to open a reference to the FPGA VI and RIO device. The Open FPGA VI Reference function, also downloads and runs the compiled FPGA code during execution. After opening the reference, you read and write to the control and indicator registers on the FPGA using the Read/Write Control function. Once you wire the FPGA reference into this function, you can simply select which controls and indicators you want to read and write to. You can enclose the FPGA Read/Write function within a While Loop to continuously read and write to the FPGA. Finally, the last function within the LabVIEW host VI is the Close FPGA VI Reference function. The Close FPGA VI Reference function stops the FPGA VI and closes the reference to the device. Now you can download other compiled FPGA VIs to the device to change or modify its functionality.The LabVIEW host VI can also be used to perform floating-point calculations, data logging, networking, and any calculations that do not fit within the FPGA fabric. For added determinism and reliability, you can run your host application on an RTOS with the LabVIEW Real-Time Module. LabVIEW Real-Time systems provide deterministic processing engines for functions performed synchronously or asynchronously to the FPGA. For example, floating-point arithmetic, including FFTs, PID calculations, and custom control algorithms, are often performed in the LabVIEW Real-Time environment. Relevant data can be stored on a LabVIEW Real-Time system or transferred to a Windows host computer for off-line analysis, data logging, or user interface displays. The architecture for this configuration . Each NI PAC platform that offers RIO hardware can run LabVIEW Real-Time VIs.Within each R Series and CompactRIO device, there is flash memory available to store a compiled LabVIEW FPGA VI and run the application immediately upon power up of the device. In this configuration, as long as the FPGA has power, it runs the FPGA VI,even if the host computer crashes or is powered down. This is ideal for programming safety power down and power up sequences when unexpected events occur.Using NI SoftMotion to Create Custom Motion ControllersThe NI SoftMotion Development Module for LabVIEW provides VIs and functions to help you build custom motion controllers as part of NI PAC hardware platforms that can include NI RIO devices, DAQ devices, and Compact FieldPoint. NI SoftMotion provides all of the functions that typically reside on a motion controller DSP. With it, you can handle path planning, trajectory generation, and position and velocity loop control in the NI LabVIEW environment and then deploy the code on LabVIEW Real-Time or LabVIEW FPGA-based target hardware.NI SoftMotion includes functions for trajectory generator and spline engine and examples with complete source code for supervisory control, position, and velocity control loop using the PID algorithm. Supervisory control and the trajectory generator run on a LabVIEW Real-Time target and run at millisecond loop rates. The spline engine and the control loop can run either on a LabVIEW Real-Time target at millisecond loop rates or on a LabVIEW FPGA target at microsecond loop rates.ApplicationsBecause the LabVIEW FPGA Module can configure low-level hardware design of FPGAs and use the FPGAs within in a modular system, it is ideal for industrial control applications requiring custom hardware. These custom applications can include a custom mix of analog, digital, and counter/timer I/O, analog control up to 125 kHz, digital control up to 20 MHz, and interfacing to custom digital protocols for the following:∙Batch control∙Discrete control∙Motion control∙In-vehicle data acquisition∙Machine condition monitoring∙Rapid control prototyping (RCP)∙Industrial control and acquisition∙Distributed data acquisition and controlMobile/portable noise, vibration, and harshness (NVH) analysis ConclusionThe LabVIEW FPGA Module brings the flexibility, performance, and customization of FPGAs to PAC platforms. Using NI RIO devices and LabVIEW graphical programming, you can build flexible and custom hardware using the COTS hardware often required in industrial control applications. Because you are using LabVIEW, a programming language already used in many industrial control applications, to define your NI RIO hardware, there is no need to learn VHDL or other low-level hardware design tools to create custom hardware. Using the LabVIEW FPGA Module and NI RIO hardware as part of your NI PAC adds significant flexibility and functionality for applications requiringultrahigh-speed control, interfaces to custom digital protocols, or a custom I/O mix of analog, digital, and counters.使用LabVIEW FPGA（现场可编程门阵列）模块开发可编程自动化控制器综述工业控制上的应用要求高度集成的模拟和数字输入输出、浮点运算和多重处理节点的无缝连接。

Introduced FPGAProgrammable logic devices is a universal logic chip can be configured for various purposes, which is to achieve ASIC (Application Specific Integrated Circuit) semi-customized device, its emergence and development make electronic systems designers can use CAD tools to design their own ASIC device in the laboratory. Especially the emergence and development of FPGA (Field Programmable Gate Array), as a microprocessor, memory, the figures for electronic system design and set a new industry standard (You can purchase the standard product catalog in the sales market). Digital systems are facing to the developing of microprocessor, memory, FPGA those three standard building blocks constituting or their integration direction.Using FPGA devices design digital circuit, can not only simplify the design process and can reduce the size and cost of the entire system, increasing system reliability. They do not need to spend the traditional sense a lot of time and effort required to create integrated circuits, to avoid the investment risk and become the fastest-growing industries of electronic devices group. The main advantage of using FPGA devices circuit design of digital systems is as follows: (1)Design flexibleUsing FPGA devices may not be limited to standard series device at logic functional . And logic can be modified at any stage of the system design and the use of the process, and only re-programming the using FPGA device can be completed, provides the system design for great flexibility.(2) Increased functional densityFunctional density means the number of logic functions can be integrated in given space. The count of components gate in programmable logic chip is high, a piece of FPGA can replace several films, dozens of films or even hundreds of small-scale digital integrated circuit chip. FPGA devices use fewer chips when achieves digital system, thus reducing the number of chips, reducing printed circuit board area and the number of printed circuit boards, eventually causing an overall reduction in system size.(3) Improve reliabilityReducing the number of chips and the printed board, not only can reduce system size, but it greatly enhanced system reliability. System with a high degree of integration have much higher reliability than the same system with a low degree of integration designed by many standardcomponents. Using FPGA device reduces the number of chips required to achieve the system, the number of leads and pads on the printed circuit board is also reduced, so the reliability of the system can be improved.(4) Shortening the design cycleBecause of programmability and flexibility of FPGA devices, and use it to design a system, the time required is much shorter than the traditional method. FPGA devices have high integration, the printed circuit board layout simply when using. Meanwhile, after the success of the prototype design, due to the advanced development tools, high degree of automation, its logic is very simple and quick to modify. Therefore, using FPGA devices can greatly shorten the design cycle and accelerate speed to market, improve product competitiveness.(5) Work fastFPGA/CPLD devices work fast, generally can reach several hundred Hertz, far faster than the DSP device. And circuit series required to achieve the system is less after using FPGA devices, thus the working speed of the entire system will be improved.(6)Increased system security performanceMany FPGA devices have encryption capabilities, using FPGA devices widely in system can effectively prevent the product from being illegally imitation of others.(7) Reduce costsUsing FPGA devices to achieve digital system design, if only consider the price of the device itself, sometimes do not see its advantage, but the factors that affect the cost of the system is multifaceted. comprehensive consideration, cost advantages of using FPGA is obvious. First, using FPGA devices is easy to modify design, shorten the design cycle, allowing the system to reduce the cost of research and development; secondly, FPGA devices enable to reduce the printed circuit board area and the number of plug-ins required, thereby reducing the manufacturing cost of the system; once again, the use of FPGA devices enables the system to improve reliability, reduce maintenance workload, thereby reducing the cost of servicing the system. In short, the system design using FPGA devices cost savings.FPGA design principles :One important guiding principle of FPGA design: the balance and interchangeable of size and speed, this principle is reflected with a large number of validation in filter design behind.Here, "area" means the number of FPGA / CPLD logic resources consumed by design , theFPGA can be measured by the consuming of flip-flop (FF) and a lookup table (LUT) , a more general approach can measure by the number of equivalent logic gates which occupied by design. "Speed" refers to the highest frequency can be achieved with stable operation on the chip, this frequency is determined by the design of the timing condition, and closely related to the clock cycle, PAD to PAD Time, Clock Setup Time, Clock Hold Time, Clock-to-Output Delay timing and many timing feature quantity. Area and speed are always imbued with FPGA design ,are the ultimate standard of design quality evaluation. Two basic concepts of area and speed: the balance of the area and the speed , the area and the speed of exchange.Size and speed are a pair of opposites contradiction. Requires a design along with the smallest design area, and the highest operating frequency is unrealistic. A more scientific design goal should be under the premise of meeting the design timing requirements (including the requirements of the design frequency), occupying the smallest chip area. Or in the specified area, designed to make more timing margin, running higher frequency. Both targets fully reflects the thinking of the balance of the area and speed. About the area and speed requirements, should not be simply interpreted as the pursue of raising the engineers level and design perfection, but should recognize that they are directly related to quality and cost of the products . If the timing margin of the design is relatively large, run a relatively high frequency, which means design is more robust, the quality of the whole system is more certified; On the other hand, design consumes less area, it means that the unit chip can achieve more functional modules, needs less chips, the cost of the entire system also will be slashed. As two parts of the contradiction, area and speeds’ status are not the same. In contrast, to meet requirements of timing and operating frequency is more important, when the two conflict, using the criteria of speed priority.Area and speed of exchange is an important idea in FPGA design. In theory, if a design have larger timing margin, and can run much higher frequency than design requirements, it will be able to reuse the function module to reduce the chip area consumed by entire design, this is the savings using the advantages of the speed to change area; On the contrary, if a design's timing requirements are high, conventional methods can not reach the design frequency, then generally make data flow serial-parallel transforming, parallel copy multiple operating modules, take on the "serial-parallel conversion" thought to operate on the entire design, conduct the "serial-parallel conversion"in date at the output of the chip module, from a macro point of view, the entire chip have meet the requirements of processing speed, this corresponds with the areareplication and faster of exchange.Give an example. Assuming input data stream of the digital signal processing system is 350Mb / s, while the processing speed in the FPGA design data processing module up to 150Mb / s, since the data throughput of processing module can not meet the requirements, direct implementation at FPGA is impossible. In this case, we should use"area-for-speed" thought, at least copied into three processing module, the input data first conduct serial-parallel conversion, then using these three modules conduct parallel processing, then the processing result conduct "serial conversion " to complete the data rate requirements. We look at both ends of the entire processing module, the data rate is 350Mb / s, while inside the FPGA, the data rate of each sub-module process is 150Mb / s, in fact, the indemnification of the entire data throughput is dependent on the three sub-modules parallel processing, that takes more advantage of the chip area, to achieve high-speed processing,to achieve the design through the "copy area in exchange for improving processing speed"thinking.FPGA is the abbreviation of the field programmable gate array, it is the product on the basis of PAL, GAL, EPLD and other programmable devices' further development. It is appeared as a semi-custom circuit in ASIC field, it not only solve the lack of custom circuits, but also overcome the defect of limited numbers of gates in original programmable device.FPGA uses LCA (Logic Cell Array) such a new concept, including internal CLB (Configurable Logic Block), IOB (Input Output Block), and internal connections in three parts. The basic characteristics of FPGA:(1)Using FPGA to design ASIC circuits, users do not need to cast film production can get applicative chips.(2)FPGA can make the specimen of other full-custom or semi-custom ASIC circuits .(3)FPGA internal have rich triggers and I / O pins.(4)FPGA is one of the shortest design cycle, the lowest development costs, the least risky devices in ASIC circuits.(5)FPGA uses high-speed CHMOS technology with low power, can be compatible with CMOS, TTL level.It can be said that the FPGA chip is one of the best choice for small-scale systems to improve system integration and reliability .Currently, FPGA have many varieties, XILINX's XC Series, TI company's TPC series,company's ALTERA series.FPGA sets its work status by a program stored in the on-chip RAM, so when work, it needs to program the on-chip RAM. The user can use different programming form depending on the configuration mode.When powered up, FPGA chip will read the data inside EPROM to the on-chip programming RAM. When the configuration is completed, FPGA go into working condition. After brownout, FPGA restore to the blank chip, the internal logic disappears, therefore, FPGA can be used repeatedly. FPGA programming don't need a dedicated FPGA programmer, just use common EPROM、PROM programmer. When the FPGA function need modified, just to change an piece of EPROM. Thus, one same FPGA, different programming data, can bring different circuit functions. Therefore, FPGA is very flexible.There are a variety of FPGA configuration modes: parallel host mode for an FPGA plus an EPROM; master-slave mode can support a PROM programs multi-chip FPGA; serial mode can use serial PROM programs FPGA; peripheral mode can make FPGA to be used as peripherals of micro-processor, programmed by the microprocessor.Verilog HDL is a hardware description language, used as multiple abstract design levels of digital system modeling from algorithm-level, gate-level to switch level. Digital systems can describe hierarchically, and can conduct timing modeling in the same description explicitly.Verilog HDL language has the following ability to describe: behavioral characteristics of the design, the data flow characteristics of the design, structure and composition of the design as well as including response monitoring, response delay and waveform generation mechanism of design verification. All these use the same modeling language. In addition, Verilog HDL language provides programming language interface, through the interface, it can access design from external design in the simulation, verification period, including the simulation of specific control and operation.Verilog HDL language not only defines the syntax but also defines a clear simulation and simulation semantics for grammatical structure. Thus, the model written by this language can use the Verilog emulator to verify. Language inherit multiple operator structure from C programming language. Verilog HDL provides expanded modeling capabilities, which many extensions initially difficult to understand.FPGA介绍：可编程逻辑器件是一种可以构成各种用途逻辑的通用芯片，它是实现专用集成电路ASIC（Application Specific Integrated Circuit）的半定制器件，它的出现和发展使电子系统设计师借助于CAD手段在实验室里就可以设计自己的ASIC器件。

Building Programmable Automation Controllers with LabVIEWFPGAOverviewProgrammable Automation Controllers (PACs) are gaining acceptance within the industrial control market as the ideal solution for applications that require highly integrated analog and digital I/O, floating-point processing, and seamless connectivity to multiple processing nodes. National Instruments offers a variety of PAC solutions powered by one common software development environment, NI LabVIEW. With LabVIEW, you can build custom I/O interfaces for industrial applications using add-on software, such as the NI LabVIEW FPGA Module.With the LabVIEW FPGA Module and reconfigurable I/O (RIO) hardware, National Instruments delivers an intuitive, accessible solution for incorporating the flexibility and customizability of FPGA technology into industrial PAC systems. You can define the logic embedded in FPGA chips across the family of RIO hardware targets without knowinglow-level hardware description languages (HDLs) or board-level hardware design details, as well as quickly define hardware for ultrahigh-speed control, customized timing and synchronization, low-level signal processing, and custom I/O with analog, digital, and counters within a single device. You also can integrate your custom NI RIO hardware with image acquisition and analysis, motion control, and industrial protocols, such as CAN and RS232, to rapidly prototype and implement a complete PAC system.Table of Contents1.Introduction2.NI RIO Hardware for PACs3.Building PACs with LabVIEW and the LabVIEW FPGA Module4.FPGA Development Flowing NI SoftMotion to Create Custom Motion Controllers6.Applications7.ConclusionIntroductionYou can use graphical programming in LabVIEW and the LabVIEW FPGA Module to configure the FPGA (field-programmable gate array) on NI RIO devices. RIO technology, the merging of LabVIEW graphical programming with FPGAs on NI RIO hardware, provides a flexible platform for creating sophisticated measurement and control systems that you could previously create only with custom-designed hardware.An FPGA is a chip that consists of many unconfigured logic gates. Unlike the fixed, vendor-defined functionality of an ASIC (application-specific integrated circuit) chip, you can configure and reconfigure the logic on FPGAs for your specific application. FPGAs are used in applications where either the cost of developing and fabricating an ASIC is prohibitive, or the hardware must be reconfigured after being placed into service. The flexible,software-programmable architecture of FPGAs offer benefits such as high-performance execution of custom algorithms, precise timing and synchronization, rapid decision making, and simultaneous execution of parallel tasks. Today, FPGAs appear in such devices as instruments, consumer electronics, automobiles, aircraft, copy machines, andapplication-specific computer hardware. While FPGAs are often used in industrial control products, FPGA functionality has not previously been made accessible to industrial control engineers. Defining FPGAs has historically required expertise using HDL programming or complex design tools used more by hardware design engineers than by control engineers.With the LabVIEW FPGA Module and NI RIO hardware, you now can use LabVIEW, a high-level graphical development environment designed specifically for measurement and control applications, to create PACs that have the customization, flexibility, andhigh-performance of FPGAs. Because the LabVIEW FPGA Module configures custom circuitry in hardware, your system can process and generate synchronized analog and digital signals rapidly and deterministically. Figure 1 illustrates many of the NI RIO devices that you can configure using the LabVIEW FPGA Module.Figure 1. LabVIEW FPGA VI Block Diagram and RIO Hardware PlatformsNI RIO Hardware for PACsHistorically, programming FPGAs has been limited to engineers who have in-depth knowledge of VHDL or other low-level design tools, which require overcoming a very steep learning curve. With the LabVIEW FPGA Module, NI has opened FPGA technology to a broader set of engineers who can now define FPGA logic using LabVIEW graphical development. Measurement and control engineers can focus primarily on their test and control application, where their expertise lies, rather than the low-level semantics of transferring logic into the cells of the chip. The LabVIEW FPGA Module model works because of the tightintegration between the LabVIEW FPGA Module and the commercial off-the-shelf (COTS) hardware architecture of the FPGA and surrounding I/O components.National Instruments PACs provide modular, off-the-shelf platforms for your industrial control applications. With the implementation of RIO technology on PCI, PXI, and Compact Vision System platforms and the introduction of RIO-based CompactRIO, engineers now have the benefits of a COTS platform with the high-performance, flexibility, and customization benefits of FPGAs at their disposal to build PACs. National Instruments PCI and PXI R Series plug-in devices provide analog and digital data acquisition and control for high-performance, user-configurable timing and synchronization, as well as onboard decision making on a single device. Using these off-the-shelf devices, you can extend your NI PXI or PCI industrial control system to include high-speed discrete and analog control, custom sensor interfaces, and precise timing and control.NI CompactRIO, a platform centered on RIO technology, provides a small, industrially rugged, modular PAC platform that gives you high-performance I/O and unprecedented flexibility in system timing. You can use NI CompactRIO to build an embedded system for applications such as in-vehicle data acquisition, mobile NVH testing, and embedded machine control systems. The rugged NI CompactRIO system is industrially rated and certified, and it is designed for greater than 50 g of shock at a temperature range of -40 to 70 °C.NI Compact Vision System is a rugged machine vision package that withstands the harsh environments common in robotics, automated test, and industrial inspection systems. NICVS-145x devices offer unprecedented I/O capabilities and network connectivity for distributed machine vision applications.NI CVS-145x systems use IEEE 1394 (FireWire) technology, compatible with more than 40 cameras with a wide range of functionality, performance, and price. NI CVS-1455 and NI CVS-1456 devices contain configurable FPGAs so you can implement custom counters, timing, or motor control in your machine vision application.Building PACs with LabVIEW and the LabVIEW FPGA Module With LabVIEW and the LabVIEW FPGA Module, you add significant flexibility and customization to your industrial control hardware. Because many PACs are already programmed using LabVIEW, programming FPGAs with LabVIEW is easy because it uses the same LabVIEW development environment. When you target the FPGA on an NI RIO device, LabVIEW displays only the functions that can be implemented in the FPGA, further easing the use of LabVIEW to program FPGAs. The LabVIEW FPGA Module Functions palette includes typical LabVIEW structures and functions, such as While Loops, For Loops, Case Structures, and Sequence Structures as well as a dedicated set of LabVIEWFPGA-specific functions for math, signal generation and analysis, linear and nonlinear control, comparison logic, array and cluster manipulation, occurrences, analog and digital I/O, and timing. You can use a combination of these functions to define logic and embed intelligence onto your NI RIO device.Figure 2 shows an FPGA application that implements a PID control algorithm on the NI RIO hardware and a host application on a Windows machine or an RT target that communicates with the NI RIO hardware. This application reads from analog input 0 (AI0), performs the PID calculation, and outputs the resulting data on analog output 0 (AO0). While the FPGA clock runs at 40 MHz the loop in this example runs much slower because each component takes longer than one-clock cycle to execute. Analog control loops can run on an FPGA at a rate of about 200 kHz. You can specify the clock rate at compile time. This example shows only one PID loop; however, creating additional functionality on the NI RIO device is merely a matter of adding another While Loop. Unlike traditional PC processors, FPGAs are parallel processors. Adding additional loops to your application does not affect the performance of your PID loop.Figure 2. PID Control Using an Embedded LabVIEW FPGA VI with Corresponding LabVIEW HostVI.FPGA Development FlowAfter you create the LabVIEW FPGA VI, you compile the code to run on the NI RIO hardware. Depending on the complexity of your code and the specifications of your development system, compile time for an FPGA VI can range from minutes to several hours.To maximize development productivity, with the R Series RIO devices you can use abit-accurate emulation mode so you can verify the logic of your design before initiating the compile process. When you target the FPGA Device Emulator, LabVIEW accesses I/O from the device and executes the VI logic on the Windows development computer. In this mode, you can use the same debugging tools available in LabVIEW for Windows, such as execution highlighting, probes, and breakpoints.Once the LabVIEW FPGA code is compiled, you create a LabVIEW host VI to integrate your NI RIO hardware into the rest of your PAC system. Figure 3 illustrates the development process for creating an FPGA application. The host VI uses controls and indicators on the FPGA VI front panel to transfer data between the FPGA on the RIO device and the host processing engine. These front panel objects are represented as data registers within the FPGA. The host computer can be either a PC or PXI controller running Windows or a PC, PXI controller, Compact Vision System, or CompactRIO controller running a real-time operating system (RTOS). In the above example, we exchange the set point, PID gains, loop rate, AI0, and AO0 data with the LabVIEW host VI.Figure 3. LabVIEW FPGA Development FlowThe NI RIO device driver includes a set of functions to develop a communication interface to the FPGA. The first step in building a host VI is to open a reference to the FPGA VI and RIO device. The Open FPGA VI Reference function, as seen in Figure 2, also downloads and runs the compiled FPGA code during execution. After opening the reference, you read and write to the control and indicator registers on the FPGA using the Read/Write Control function. Once you wire the FPGA reference into this function, you can simply select which controls and indicators you want to read and write to. You can enclose the FPGA Read/Write function within a While Loop to continuously read and write to the FPGA. Finally, the last function within the LabVIEW host VI in Figure 2 is the Close FPGA VI Reference function. The Close FPGA VI Reference function stops the FPGA VI and closes the reference to the device. Now you can download other compiled FPGA VIs to the device to change or modify its functionality.The LabVIEW host VI can also be used to perform floating-point calculations, data logging, networking, and any calculations that do not fit within the FPGA fabric. For added determinism and reliability, you can run your host application on an RTOS with the LabVIEW Real-Time Module. LabVIEW Real-Time systems provide deterministicprocessing engines for functions performed synchronously or asynchronously to the FPGA. For example, floating-point arithmetic, including FFTs, PID calculations, and custom control algorithms, are often performed in the LabVIEW Real-Time environment. Relevant data can be stored on a LabVIEW Real-Time system or transferred to a Windows host computer for off-line analysis, data logging, or user interface displays. The architecture for this configuration is shown in Figure 4. Each NI PAC platform that offers RIO hardware can run LabVIEW Real-Time VIs.Figure 4. Complete PAC Architecture Using LabVIEW FPGA, LabVIEW Real-Time and Host PC Within each R Series and CompactRIO device, there is flash memory available to store a compiled LabVIEW FPGA VI and run the application immediately upon power up of the device. In this configuration, as long as the FPGA has power, it runs the FPGA VI, even if the host computer crashes or is powered down. This is ideal for programming safety power down and power up sequences when unexpected events occur.Using NI SoftMotion to Create Custom Motion ControllersThe NI SoftMotion Development Module for LabVIEW provides VIs and functions to help you build custom motion controllers as part of NI PAC hardware platforms that can include NI RIO devices, DAQ devices, and Compact FieldPoint. NI SoftMotion provides all of the functions that typically reside on a motion controller DSP. With it, you can handle path planning, trajectory generation, and position and velocity loop control in the NI LabVIEW environment and then deploy the code on LabVIEW Real-Time or LabVIEW FPGA-based target hardware.NI SoftMotion includes functions for trajectory generator and spline engine and examples with complete source code for supervisory control, position, and velocity control loop using the PID algorithm. Supervisory control and the trajectory generator run on a LabVIEW Real-Time target and run at millisecond loop rates. The spline engine and the control loop can run either on a LabVIEW Real-Time target at millisecond loop rates or on a LabVIEW FPGA target at microsecond loop rates.ApplicationsBecause the LabVIEW FPGA Module can configure low-level hardware design of FPGAs and use the FPGAs within in a modular system, it is ideal for industrial controlapplications requiring custom hardware. These custom applications can include a custom mix of analog, digital, and counter/timer I/O, analog control up to 125 kHz, digital control up to 20 MHz, and interfacing to custom digital protocols for the following:•Batch control•Discrete control•Motion control•In-vehicle data acquisition•Machine condition monitoring•Rapid control prototyping (RCP)•Industrial control and acquisition•Distributed data acquisition and control•Mobile/portable noise, vibration, and harshness (NVH) analysis ConclusionThe LabVIEW FPGA Module brings the flexibility, performance, and customization of FPGAs to PAC platforms. Using NI RIO devices and LabVIEW graphical programming, you can build flexible and custom hardware using the COTS hardware often required in industrial control applications. Because you are using LabVIEW, a programming language already used in many industrial control applications, to define your NI RIO hardware, there is no need to learn VHDL or other low-level hardware design tools to create custom hardware. Using the LabVIEW FPGA Module and NI RIO hardware as part of your NI PAC adds significant flexibility and functionality for applications requiring ultrahigh-speed control, interfaces to custom digital protocols, or a custom I/O mix of analog, digital, and counters.使用LabVIEW FPGA（现场可编程门阵列）模块开发可编程自动化控制器综述工业控制上的应用要求高度集成的模拟和数字输入输出、浮点运算和多重处理节点的无缝连接。