HD74BC373A中文资料

Regarding the change of names mentioned in the document, such as Hitachi

Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

© 1999 Fairchild Semiconductor CorporationDS012015

September 1999Revised October 199974LVT373 • 74LVTH373 Low Voltage Octal Transparent Latch with 3-STATE Outputs74LVT373 • 74LVTH373Low Voltage Octal Transparent Latchwith 3-STATE OutputsGeneral DescriptionThe LVT373 and LVTH373 consist of eight latches with3-STATE outputs for bus organized system applications.The latches appear transparent to the data when LatchEnable (LE) is HIGH. When LE is LOW, the data satisfyingthe input timing requirements is latched. Data appears onthe bus when the Output Enable (OE) is LOW. When OE isHIGH, the bus output is in a high impedance state.The LVTH373 data inputs include bushold, eliminating theneed for external pull-up resistors to hold unused inputs.These octal latches are designed for low-voltage (3.3V)VCC applications, but with the capability to provide a TTLinterface to a 5V environment. The LVT373 and LVTH373are fabricated with an advanced BiCMOS technology toachieve high speed operation similar to 5V ABT whilemaintaining low power dissipation.FeaturessInput and output interface capability to systems at 5V VCCsBushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), alsoavailable without bushold feature (74LVT373).sLive insertion/extraction permittedsPower Up/Down high impedance provides glitch-freebus loadingsOutputs source/sink −32 mA/+64 mAsFunctionally compatible with the 74 series 373 Ordering Code: Logic SymbolsIEEE/IECOrder NumberPackage NumberPackage Description74LVT373WMM20B20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide74LVT373SJM20D20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVT373MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide74LVTH373WMM20B20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide74LVTH373SJM20D20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide74LVTH373MTCMTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide元器件交易网274LVT373 • 74LVTH373Connection DiagramPin DescriptionsTruth TableH = HIGH Voltage LevelL = LOW Voltage LevelZ = High ImpedanceX = ImmaterialO0 = Previous O0 before HIGH-to-LOW transition of Latch EnableFunctional DescriptionThe LVT373 and LVTH373 contain eight D-type latcheswith 3-STATE standard outputs. When the Latch Enable(LE) input is HIGH, data on the Dn inputs enters thelatches. In this condition the latches are transparent, i.e., alatch output will change state each time its D inputchanges. When LE is LOW, the latches store the informa-tion that was present on the D inputs a setup time preced-ing the HIGH-to-LOW transition of LE. The 3-STATEstandard outputs are controlled by the Output Enable (OE)input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are inthe high impedance mode but this does not interfere withentering new data into the latches.Logic Diagram

Original Creation Date: 11/18/96Last Update Date: 06/19/97Last Major Revision Date: 04/17/97CN74F373-X REV 1A0MICROCIRCUIT DATA SHEETOCTAL TRANSPARENT LATCH WITH TRI-STATE OUTPUTS General DescriptionThe F373 consists of eight latches with Tri-State outputs for bus organized systemapplications. The flip-flops appear transparent to the data when Latch Enable (LE) isHIGH. When LE is LOW, the data that meets the setup times are latched. Data appear onthe bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in thehigh impedance state. NS Part Numbers74F373DCIndustry Part Number74F373Prime DieM373ProcessingQuality Conformance InspectionSubgrp Description Temp ( C)o1Static tests at +252Static tests at +703Static tests at 04Dynamic tests at +255Dynamic tests at +706Dynamic tests at 07Functional tests at +258AFunctional tests at +708BFunctional tests at 09Switching tests at +2510Switching tests at +7011

FEATURES1

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1Q

1D

2D

2Q

3Q

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4Q

GNDVCC

8Q8D

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LEDW OR PW PACKAGE

(TOP VIEW)

DESCRIPTION/ORDERINGINFORMATIONSN74LVC373A-Q1OCTALTRANSPARENTD-TYPELATCH

WITH3-STATEOUTPUTS

SCAS710B–SEPTEMBER2003–

•QualifiedforAutomotiveApplications

•ESDProtectionExceeds2000VPer

MIL-STD-883,Method3015;Exceeds200V

UsingMachineModel(C=200pF,R=0)

•OperatesFrom2Vto3.6V

•InputsAcceptVoltagesto5.5V

•Maxtpdof7.5nsat3.3V

•TypicalVOLP(OutputGroundBounce)<0.8V

atVCC=3.3V,TA=25°C

•TypicalVOHV(OutputVOHUndershoot)>2V

atVCC=3.3V,TA=25°C

•SupportsMixed-ModeSignalOperationonAll

Ports(5-VInput/OutputVoltageWith3.3-VVCC)

•IoffSupportsPartial-Power-DownMode

Operation

TheSN74LVC373AoctaltransparentD-typelatchisdesignedfor2.7-Vto3.6-VVCCoperation.

Whilethelatch-enable(LE)inputishigh,theQoutputsfollowthedata(D)inputs.WhenLEistakenlow,theQ