AS603 datasheet_en_V1.0

AS603Processor DatasheetRevision1.0, March 2009Synochip Co., LtdRm102, Building 17, No.176 TianmushanS y n oc h i pCo nf i d e n t i a lDisclaimerThis documentation is provided for use with Synochip products. No license to Synochip property rights is granted. Synochip assumes no liability, provides no warranty either expressed or implied relating to the usage, or intellectual property right infringement except as provided for by Synochip Co., Ltd. All information in this document should be treated as preliminary. Synochip may make changes to this document without notice. Anyone relying on this documentation should contact Synochip for the current documentation and errata.S yn oc hi pCo nf i d e n t i a lVersion listModify ContentVersionDataChapter PageContent 1.0 2009-3-16 Initial 1.1 2009-3-26 6.5 13 Booting mode select 6.8 15 Features of Timers 8 22 Package diagram1.2 2009-3-14 6.5 13 Table 6-2 5.1 5 Figure 5-1 5.2 6 Table 5-1 1.3 2009-4-20 5 5-8 Pin names 1.4 2009-4-21 3 3 Features1.5 2009-6-29 8 23 Mechanical CharacteristicsS yn oc hi pCo nf id e n t i a lContentsDisclaimer..................................................................................................................................................................II Version list...............................................................................................................................................................III Contents...................................................................................................................................................................IV Figure Contents........................................................................................................................................................VI Table Contents........................................................................................................................................................VII 1 General Description............................................................................................................................................1 2 Block Diagram....................................................................................................................................................2 3 Features...............................................................................................................................................................3 4 Target Applications.............................................................................................................................................4 5 Pin Information (5)5.1 Pin Assignment.........................................................................................................................................5 5.2 Pin Description.........................................................................................................................................6 6 Function Description. (9)6.1 Cordis 5+ RISC Core (9)6.1.1 Highlights and Key Feature............................................................................................................9 6.2 Memory Architecture (10)6.2.1 Overview......................................................................................................................................10 6.2.2 Memory Maps..............................................................................................................................10 6.3 Interrupt Architecture.............................................................................................................................11 6.4 JTAG.......................................................................................................................................................12 6.5 Booting...................................................................................................................................................12 6.6 PM..........................................................................................................................................................13 6.7 GPIO.......................................................................................................................................................14 6.8 Timers.....................................................................................................................................................14 6.9 USART...................................................................................................................................................15 6.10 USB........................................................................................................................................................16 6.11 OTP ........................................................................................................................................................17 6.12 SCI..........................................................................................................................................................17 6.13 SQI..........................................................................................................................................................17 6.14 APC........................................................................................................................................................18 6.15 SDC........................................................................................................................................................18 6.16 CCP........................................................................................................................................................19 6.17 LOCSC...................................................................................................................................................19 6.18 RTC ........................................................................................................................................................19 7 Electrical Characteristics. (21)7.1 Limiting Values.......................................................................................................................................21 7.2 Operation Conditions..............................................................................................................................21 7.3 DC Specification ....................................................................................................................................22 8 Mechanical Characteristics...............................................................................................................................23 9 Ordering Information. (24)S yn oc hi pCo nf i d e n t i a l10 Abbreviations (25)S yn oc hi pCo nf i d e n t i a lFigure ContentsFigure 2-1 AS603 Block Diagram.....................................................................................................................2 Figure 5-1 128-lead LQFP Package Outline (Top View)...................................................................................5 Figure 6-1 AS603 Memory Maps....................................................................................................................11 Figure 8-1 AS603 Package (23)S yn oc hi pCo nf i d e n t i a lTable ContentsTable 5-1 AS603 Pin List...................................................................................................................................6 Table 6-1 Offsets and IRQ Assignment of Cordis 5+ processor......................................................................12 Table 6-2 Boot Sources Select.........................................................................................................................13 Table 6-3 Data Flow Format In USB ISP Mode..............................................................................................13 Table 6-4 Flash Data Structure........................................................................................................................13 Table 7-1 AS603 Limiting Values....................................................................................................................21 Table 7-2 V oltage, Temperature, and Frequency Electrical Specifications......................................................22 Table 7-3 Standard I/O Pin DC Operation Conditions (22)S yn oc hi pCo nf i d e n t i a l1 General DescriptionAS603 is a member of the Synochip’s Cordis 5+ family, Cordis 5+ is the 32-bit RISC core which is featured with 16-/32-bit ISA and a Harvard bus architecture. The enhanced DSP instruction extensions and accelerators are supported by this core. In addition, a 5-stage pipeline is used to increase the amount of operational parallelism,giving the most performance out of each clock cycle.The AS603 featured with a Hardware Convolution Accelerator providing 10-50 times acceleration benefits the image processing,and a specific Hardware interface of CMOS sensor for Video capture. In addition,the AS603 also featured with Multi processing specific instructions (lext2b, lext4b, div64) and registers for specific data processing.AS603 works on typical frequency of 120 MHz. It provides a set of high-performance peripheral components including SQI(Serial Quad Interface), 128KByte SRAM, 64KByte ROM, 4Kb OTP memory, USB 2.0(FS) Device, 3xUSART (UART/SPI/I 2C), 4xCCP(Capture/Compare/PWM), SCI(Smart Card Interface), LOCSC(Limited Optical CMOS Sensor Controller), SDC(SDRAM Controller), APC(Asynchronous Parallel Controller), RTC, andup to 99 GPIOs.The AS603 is a 32-bit SOC combine sophisticated, flexible signal system-on-chip integration with unparalleledreal-time multi-tasking capabilities. AS 603 reaches an excellent balance between the cost and performance .The Complex applications previously impossible with legacy SOC can now be accommodated with ease by powerful, cost-effective and simple-to-programs 32bit- SOC.The AS603 is positioned for cost-conscious applications requiring significant control processing and connectivity capabilities, including motion control, monitoring (remote, fire/ security, etc.), HV AC and building controls, power and energy monitoring and conversion, network appliances and switches, factory automation, electronic point-of-sale machines, test and measurement equipment, medical instrumentation, and gaming equipment. Providing this complete feature frees the SoC designers to concentrate on design issues unique to their system.S yn oc hi pCo nf i d e n t i a l2 Block DiagramFigure 2-1 AS603 Block DiagramS yn oc hi pCo nf i d e n t i3 FeaturesCordis 5+ RISC Processor Corez I-Cache: 8K bytes, 64 bytes line size, 2-way associated z D-Cache: 4K bytes, 32 bytes lines size, 2-way associated z IEEE1149.1 compliant JTAG debug interfacez Various DSP instructions for computing-intensive applications z Timer x 2 with WDT and password protection z 4 hardware breakpointsz Reset Vector mapped to ROM Internal Memoriesz ROM :64K Bytes z SRAM :128K Bytesz OTP Memory :4K bits(512*8), 1 bit programming with Charge Pump External Memoriesz Asynchronous SRAM/flash : 32M Bytes z SQI Flash : 16M Bytes z SDRAM : 16M Bytes Various Peripheral Interfacesz USB 2.0 full speed with integrated PHYz USART(Configurable as UART,SPI or I 2C) x 3 z 4-way CCP(Capture, Compare, PWM)z Up to 99 GPIO ports, some with Interrupt functionsz 5V tolerance IOs , including Four High-current Drive I/O lines, Up to 15 mA Each z Smart Card Interface (ISO7816 interface)z Limited Optical CMOS Sensor Controller (hardware optical image sensor interface) Special Featuresz Hardware AcceleratorsHardware Convolution Accelerator provides 10-50 times acceleration Multi processing specific instructions (lext2b, lext4b, div64) and registers z 32 bits unique Serial Number z JTAG lock z RTC z PORz On chip PLLz Sleep and wakeup on different levelz Dynamic switch of the operation frequency z Fetch instructions from Flash memoryS yn oc hi pCo nf i d e n t i a l4 Target Applicationsz Video door phone z Remote monitoringz Electronic point-of-sale (POS) machines z Test and measurement equipment z Network appliances and switches z Factory automationz HVAC and building control z Gaming equipment z Motion controlz Medical instrumentation z Fire and security z Power and energy zTransportationS yn oc hi pCo nf i d e n t i a l5 Pin InformationThe AS603 is in 128-lead LQFP package.5.1 Pin AssignmentFigure 5-1 128-lead LQFP Package Outline (Top View)i a l5.2 Pin DescriptionTable 5-1 AS603 Pin ListNumberPIN NameIO typeDescriptionGlobal Signals 22 XTAL_IN I Crystal in for oscillator 23 XTAL_OUT O Crystal out for oscillator 83 XTAL_RTC_IN I 32k Crystal in for RTC 84 XTAL_RTC_OUT O 32k Crystal out for RTC 119 RESETNI Reset signal80 CLK_OUT/GPIOA[0] I/O Configurable clock output 69 EXT_INT[2]/GPIOA[30]I/O External interrupt input signal127 EXT_INT[1]/HSYNC/GPIOA[2] I/OExternal interrupt input signal, multiplexed byLOCSC HSYNC64 EXT_INT[0]/GPIOA[1] I/O External interrupt input signal101 TEST_EN INo Connect. Recommended to be connected toground104 GPIOE[2] I/O 103 GPIOE[1] I/O 102 GPIOE[0] I/O Boot mode select Power Interface 32 PLL_VDD P 1.8V power supply for PLL 31 PLL_VSS G Ground for PLL 116 CORE_VDD[3] P 81 CORE_VDD[2] P52 CORE_VDD[1] P 26 CORE_VDD[0] P 1.8V power supply for digital core117 CORE_VSS[3] G 82 CORE_VSS[2] G51 CORE_VSS[1] G 12 CORE_VSS[0] G Ground for digital core100 IO_VDD[3] P 65 IO_VDD[2] P33 IO_VDD[1] P 4 IO_VDD[0] P 3.3V power supply for IO99 IO_VSS[3] G 66 IO_VSS[2] G34 IO_VSS[1] G 3 IO_VSS[0] G Ground for IO30 USB_VDDH P 3.3V power supply for USB 27 USB_VSSH G Ground for USB JTAG Interface 85 JTAG_TDI/GPIOA[3] I/O JTAG test data input 86 JTAG_TDO/GPIOA[4] I/O JTAG test data output 87 JTAG_TMS/GPIOA[5] I/O JTAG test mode select 88 JTAG_TCK/GPIOA[6] I/O JTAG test clock USB Interface 28 USB_DP AI/O USB positive connect 29 USB_DN AI/O USB negative connect 24 USB_PU I/O USB pull up signal SQI Interface 67 SQI_IO0/GPIOA[24] I/O SQI data output 6 SQI_IO1/GPIOA[25] I/O SQI data input 25 SQI_IO2/GPIOA[26] I/O SQI write protect output 98 SQI_IO3/GPIOA[27] I/O SQI Hold output 68 SQI_CLK/GPIOA[28] I/O SQI serial clock input 5 SQI_CS/GPIOA[29] I/O SQI Chip select output USART0 InterfaceMode Master Slave SPI Clock output Clock inputI2C Clock output Clock input 77 USART0_CLK/GPIOA[7] I/OUART reservedS yn oc hi pCo nf i d e n t i a lMode Master SlaveSPIData input Data output I2C Data line 78 USART0_DIO1/GPIOA[8]I/O UART Receive data Mode Master Slave SPI Data output Data inputI2C Reserved 79 USART0_DIO2/GPIOA[9] I/OUART Transmit dataUSART1 InterfaceMode Master Slave SPI Clock output Clock inputI2C Clock output Clock input 97 USART1_CLK/GPIOA[10]I/OUART reserved Mode Master Slave SPI Data input Data outputI2C Data line 95 USART1_DIO1/GPIOA[11]I/OUART Receive data Mode Master Slave SPI Data output Data inputI2C Reserved 96 USART1_DIO2/GPIOA[12] I/OUART Transmit data USART2 InterfaceMode Master Slave SPI Clock output Clock inputI2C Clock output Clock input 128 USART2_CLK/GPIOA[13]I/OUART reserved Mode Master Slave SPI Data input Data outputI2C Data line 1 USART2_DIO1/GPIOA[14]I/OUART Receive data Mode Master Slave SPI Data output Data inputI2C Reserved 2 USART2_DIO2/GPIOA[15] I/OUART Transmit dataSCI and CCP Interface120 SCI_CLK/CCP0/GPIOA[20] I/OSCI clock signal, multiplexed by CCP0 121 SCI_RST/CCP1/GPIOA[21] I/O SCI reset signal, multiplexed by CCP1 122 SCI_IO/CCP2/GPIOA[22] I/O SCI data signal, multiplexed by CCP2123 SCI_PRES/CCP3/GPIOA[23] I/O SCI card present signal, multiplexed by CCP3Single Purpose GPIO124 GPIOC[0] I/O 125 GPIOC[1] I/O 7 GPIOC[3] I/O 8 GPIOC[4] I/O 9 GPIOC[5] I/O 10 GPIOC[6] I/O 11 GPIOC[7] I/O 35 GPIOC[8] I/O 36 GPIOC[9] I/O37 GPIOC[10] I/O 38 GPIOC[11] I/O 70 GPIOC[12] I/O 71 GPIOC[13] I/O 72 GPIOC[14] I/O 73 GPIOC[15] I/O 74 GPIOC[16] I/O 75 GPIOC[17] I/O 76 GPIOC[18] I/OSingle Purpose IO PortAPC/SDC/LOCSC Interface 39 PCEN0/GPIOA[16] I/O APC Chip Select 59 PCEN1/GPIOA[17]I/OAPC Chip Select 118 PWEN/GPIOA[18] I/O APC write enable 40 PRDN/GPIOA[19] I/O APC read enable58 DQ[15]/GPIOB[15]I/OAPC/SDC data bus[15:8]S yn oc hi pCo nf i d e n t i a l56 DQ[14]/GPIOB[14] I/O54 DQ[13]/GPIOB[13] I/O 50 DQ[12]/GPIOB[12] I/O 48 DQ[11]/GPIOB[11] I/O 46 DQ[10]/GPIOB[10] I/O 44 DQ[9]/GPIOB[9] I/O 42 DQ[8]/GPIOB[8] I/O 57 DQ[7]/GPIOB[7] I/O 55 DQ[6]/GPIOB[6] I/O 53 DQ[5]/GPIOB[5] I/O 49 DQ[4]/GPIOB[4] I/O47 DQ[3]/GPIOB[3] I/O 45 DQ[2]/GPIOB[2] I/O 43 DQ[1]/GPIOB[1] I/O 41 DQ[0]/GPIOB[0] I/OAPC/SDC/LOCSC data bus[7:0]126 PCLK/GPIOC[2]I/O LOCSC PCLK 60 ADDR[23]/BA[1]/GPIOD[23] I/O61 ADDR[22]/BA[0]/GPIOD[22] I/OAPC address bus [23:22], multiplexed by BA of SDC62 ADDR[21]/DQM[1]/GPIOD[21] I/O 63 ADDR[20]/DQM[0]/GPIOD[20] I/O APC address bus [21:20], multiplexed by DQM of SDC 13 ADDR[19]/GPIOD[19] I/O 14 ADDR[18]/GPIOD[18] I/O 15 ADDR[17]/GPIOD[17] I/O 16 ADDR[16]/GPIOD[16] I/O17 ADDR[15]/GPIOD[15] I/O 18 ADDR[14]/GPIOD[14] I/O 19 ADDR[13]/GPIOD[13] I/O 20 ADDR[12]/GPIOD[12] I/O APC address bus [19:12]21 ADDR[11]/GPIOD[11] I/O 105 ADDR[10]/GPIOD[10] I/O 106 ADDR[9]/GPIOD[9] I/O 107 ADDR[8]/GPIOD[8] I/O 108 ADDR[7]/GPIOD[7] I/O 109 ADDR[6]/GPIOD[6] I/O110 ADDR[5]/GPIOD[5] I/O 111 ADDR[4]/GPIOD[4] I/O 112 ADDR[3]/GPIOD[3] I/O 113 ADDR[2]/GPIOD[2] I/O 114 ADDR[1]/GPIOD[1] I/O 115 ADDR[0]/GPIOD[0] I/O APC/SDC address bus[11:0]94 SCLK/GPIOD[24] I/O SDC Clock signal 93 CS_N/GPIOD[25] I/O SDC Chip Selects 92 CKE/GPIOD[26] I/O SDC Clock Enable 91 RAS_N/GPIOD[27] I/O SDC Command signal 90 CAS_N/GPIOD[28] I/O SDC Command signal 89 WE_N/GPIOD[29] I/O SDC Command signalS yn oc hi pCo nf i d e n t i a l6 Function Description6.1 Cordis 5+ RISC CoreThe processor used in AS603 chips is the Synochip’s innovation Cordis 5+ RISC core.Cordis 5+ is a full-featured, mid-range embedded processor core with best-in-class speed, speed area and power characteristics. It is designed as a complete processor solution for SoCs targeted at consumer, networking, automotive and other cost-sensitive markets.The Cordis 5+ core’s flexible, configurable memory architecture makes it ideal for RTOS-based applications.Powerful DSP options enable it to perform more functions, eliminating separate logic or DSP blocks from the SoC. The innovation image processing specific instructions and accelerators in Cordis 5+ processor can significantly accelerate the image processing application of AS603 chips.6.1.1 Highlights and Key FeatureHighlightsz Synochip innovation image processing specific instructions and accelerators deliver 10~60 timesperformance improvement of critical routines.z Flexible memory design including caches and closely coupled (single-cycle) memories is ideal forRTOS-based applications.z Built-in DSP features include instruction and register that accelerate signal processing algorithms.z Cordis 16-/32-bit Instruction Set Architecture reduces code size by up to 40 percent compared to 32-bitonly instruction sets.z JTAG debug port and embedded hardware breakpoints facilitate software debug. CPU Architecturez 5-stage instruction pipeline z Static branch predictionz 32-bit data, instruction and address busz Scoreboarded data memory pipeline to reduce data stallsz Single-cycle instruction CCM (Closely Coupled Memory), 64KB ROM z 2-way associated instruction cache, 8KB z 2-way associated data cache, 4KB z Little endian architecture z Up to 32, two level interrupts Cordis ISAz 16- and 32-bit instructions for high code density z No overhead for switching between 16- and 32-bitS yn oc hi pCo nf i d e n t i a lz Single-cycle instruction executionz Various Synochip specific instructions to accelerate critical routinesz Up to 64 directly addressable core registers and 32 conditional execution codes z Flexible addressing modesRegistersz 32 entry register file in base processor, extendible to 60z 26 general purpose registers, various Synochip specific registersz 32-bit auxiliary register space for single-cycle, unarbitrated data storage and retrievalDSP Instructionsz Single Cycle 32x16 and dual 16x16 MUL and MAC instructions z Parallel execution of MUL, MAC and other ALU operations z 64-bit divide instructionz Saturating arithmetic instructions z Zero overhead loop supportz Innovation byte transfer instruction for image processingPower Managementz Sleep mode via software instruction z Clock gating option z High efficiency pipeline z On-chip RAM controlsHost Interface/Debug Featuresz Software and hardware breakpoints with cascadable triggers z JTAG interface to host toolsz Debug host can access all registers and CPU memory6.2 Memory Architecture6.2.1 OverviewAS603 supports up to 4G Bytes memory space, which includes: z 8M Bits on-chip Flash Memoryz 128K SRAM, support single-cycle access at full speed. z 64K Bytes Internal ROM.z4K Bits OTP Memory, Multi-cycle access.6.2.2 Memory MapsS yn oc hi pCo nf i d e n t i a lFigure 6-1 AS603 Memory MapsNote ：the other memory space, which is not listed in the figure, such as 0x0000 FFFF~0x2000 0000 is system reserved, if the user access it, no error is returned.6.3 Interrupt ArchitectureThe Cordis 5+ processor has interrupts and exceptions. Exceptions are synchronous to an instruction. Most exceptions can occur at the same place each time a program is executed (apart from a Memory Error exception that can occur asynchronously), whereas interrupts are typically asynchronous. There are additionally two sets ofmaskable interrupts: level 2 (mid priority) and level 1 (low priority). The exception set always has the highest priority over the interrupts.The Cordis based processor features two level of interrupt:z level 2 (mid priority) interrupts which are maskable. z level 1 (low priority) interrupts which are maskableExceptions, like Reset and Instruction Error, have a higher priority than interrupts, the level 2 interrupt set has middle priority and level 1 the lowest priority. In addition there is a relative priority in the set of interrupts associated with each level.Programming an auxiliary register can change the level priority of each maskable interrupt, and the base of theinterrupt vectors can be change during program execution.S yn oc hi pCo nf i d e n t i a lIn the Cordis 5+ configurable interrupt system, there are sixteen default interrupts/exceptions associated with vectors 0 to 15, each having its own vector position.The vector offsets and IRQ assignment are shown in Table 6-1. Two long-words are reserved for each interrupt lineto allow room for a jump instruction with a long immediate address.Table 6-1 Offsets and IRQ Assignment of Cordis 5+ processorVector Name Link register Priority(Default) Relative Priority Byte Offset0 Reset - high H1 0x00 1 Memory Error ILINK2 high H2 0x08 2 Instruction Error ILINK2 high H3 0x10 3 IRQ3(Timer0) ILINK1 level 1 : low L27 0x18 4 IRQ4(USART0) ILINK1 level 1 : low L26 0x20 5 IRQ5(USART1) ILINK1 level 1 : low L25 0x286 IRQ6(USART2) ILINK2 level 2 :mid M2 0x307 IRQ7(Timer1) ILINK2 level 2 :mid M1 0x38 8 IRQ8(SCI) ILINK1 level 1 : low L24 0x409 IRQ9(reserved ) ILINK1 level 1: low L23 0x48 10 IRQ10(RTC) ILINK1 level 1 : low L22 0x50 11 IRQ11(reserved) ILINK1 level 1 : low L21 0x58 12 IRQ12(USB) ILINK1 level 1 : low L20 0x60 13 IRQ13(CCP) ILINK1 level 1 : low L19 0x68 14 IRQ14(Ext Int0) ILINK1 level 1 : low L18 0x70 15 IRQ15(Ext Int1) ILINK1 level 1 : low L17 0x78 16 IRQ16(Ext Int2) ILINK1 level 1 : low L16 0x80 17 IRQ17(GPIOC) ILINK1 level 1 : low L15 0x88 18 IRQ18(LOCSC) ILINK1 level 1 : low L140x90In the AS603, each IRQ has connected to the source, for example, the IRQ3 connected to Timer0’s interrupt, and IRQ4 connected to USART0’s interrupt.6.4 JTAGThe AS603 SoC integrates a universal debug unit, the JTAG interface. The JTAG interface compatible with the protocol IEEE STD 1149.1, contains logic for communicating with the processor and its memory system, supporting in-system-programming and on-chip-debugging. The JTAG interface provides hardware breakpoints and unlimited software breakpoint support.JTAG host can access the chip core and memory resources, but the JTAG lock on OTP memory can avoid the host to access the resources on chip. The JTAG port is multiplexed by GPIO pins. By default, the related pins are used for JTAG function.Features z On-chip-debugging z In-system-programmingz 4 action-points, each can cause a hardware breakpoint zUnlimited software breakpoint6.5 BootingThe AS603 can extend asynchronous parallel flash or SQI flash according to different applications. The AS603 supports three different boot modes depending on GPIOE[1:0] and four flag bytes programmed in peripheral flash.S yn oc hi pCo nf i d e n t i a lThe three modes are: SQI Flash mode, APC Flash mode and USB ISP mode. The power up state of GPIOE[2] selects with-driven or non-driven in USB ISP mode. Table 6-2 lists them.Table 6-2 Boot Sources SelectFlag GPIOE[1:0]Boot Source0x12345678 00 SQI Flash0x12345678 01 Asynchronous Parallel FlashNot 0x12345678 00/01-- 10 USB ISP Mode, update SQI Flash-- 11IdleThe data is written in little-endian, and transferred from lower bit. Table 6-3 lists the format of data flow in USB ISP mode.Table 6-3 Data Flow Format In USB ISP ModeName Size[Byte Addr] Content Noteflag4[0~3] Valid flag of boot table 0x12345678 is valid flag 4[4~7] Entrance address Jump to this address after boot 1[8] Register number need to be configured -- 4[9~12] Address of register 0 -- 4[13~16] Content in register 0 -- 1[17] Wait cycles -- configuration field[…] -- Repeat according to registernumber4[p~p+3] Section length -- 4[p+4] Start address of section -- section 1[…] Content of section --4[q~q+3] Length of the 2ndsection Boot end if section length is 04[q+4] Start address of the 2ndsection --section 2[…] Content of the 2ndsection-- section n[…] Repeat section. Section length equals 0 is the end flag of boot table.In SQI Flash mode and APC Flash mode, SmartLoader reads application entrance address from flash, and then jumps to this address to run. Table 6-4 lists the data storage structure in flash.Table 6-4 Flash Data StructureFlash AddrContent ByteDescription0x0000 0000-0x0000 0003 Flag4The value 0x12345678 indicates that flash hasbeen programmed.0x0000 0004-0x0000 0007Entrance address 4 SmartLoader gets application entranceaddress from here.0x0000 0008-0x0000 03FFReserved 1016 Reserved 0x0000 0400 aboveCode region16M/32M/64M Storage application program.6.6 PMThe power management (PM) unit in AS603 is the control center of the chip. It is used to control the clock and reset of each individual module in the chip, and also used for configuring the clock generation logic and controlling the configuration & power of SRAM in AS602. All the modules’ clock and reset signals are generated by the power management unit.The clock and reset generation logic in power management unit generates every module’s clock and reset signals based on the external reset pin (RESETN) and OSC pin (XTAL_IN & XTAL_OUT).There is a POR resides in the power management module so the RESETN pin is optional for generating systemS yn oc hi pCo nf id e n t i a l。