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Document Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.Appendix to GES-0128:Outside Lab Capability AssessmentREQUIREMENTSREPORT FORMCOMMENTS CARDCOPYRIGHT © 2008 WHIRLPOOL CORPORATIONDocument Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden. TABLE OF CONTENTSPage Foreword ....................................................................................................................................... 11 Auditee Preparation Guidelines ...................................................................................................... 11-12Suggested Outside Lab Capability Assessment Agenda ................................................................. 13 Outside Lab Capability Assessment Topics .................................................................................... 13 Requirement Statements and Guidelines ........................................................................................ 14-15 Auditee Final Assessment Status ................................................................................................... 16 Outside Lab Capability Assessment Requirements ......................................................................... 17 L1 - Quality Systems (equipment & data integrity)................................................................. 18 L2 - Materials Testing .......................................................................................................... 19 L3 - Codes & Regulatory Requirements ............................................................................... 20 L4 - Test Specifications & Procedures .................................................................................. 21 L5 - Test Plans .................................................................................................................... 22-23 L6 - Reliability ………………………………………………………………24 L7 - Lab Product Approval Process ...................................................................................... 25-26L8 – Lab Personnel Experience ………………………………….…………..27-28 L9 – Product Experience and Market Experience (29)Glossary of Terms …………………………………………………...30-31 Outside Lab Assessment Report .................................................................................................... 33 Assessment Individual Key Scores and Findings ............................................................................ 33-35 Comments Card ............................................................................................................................ 36 Comments & Suggestions ..............................................................................................................37Document Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.FOREWORDThe purpose of this document is to define the proper standard for the assessment of outside labs for potential data source(s) to support Whirlpool Corporation ’s product approval process. It is expected that any outside lab providing data will do so in a manner consistent with Whirlpool ’s Product Approval and Lab Operation process; thus, this Whirlpool ’s assessment is based upon the same “18 PALO Keys to Lab Improvement ” as is used internally at Whirlpool.This Outside Lab Assessment is to be used under the direction of a trained Product Approval representative.The contents of this document explain the necessary steps involved when going through a Whirlpool Outside Lab Assessment. The first section in this package is the “Outside Lab Audit Assessment Guidelines,” which are recommendations on how and what to prepare for the official assessment. Following that is the “Suggested Assessment Agenda .” This agenda is supplied to help the outside lab understand approximately how the time is allocated throughout the day while conducting the assessment. It is only a suggested agenda and does not take into account the size or complexity of the location beingassessed. The section “Guidelines for Use ” contains information about how to use this document. The biggest and most important section called “Assessment Requirements,” lists all the assessment requirements that will be used to evaluate the Outside Lab ’s Capabilities. This section is the core of the assessment process and the assessment team will evaluate the outside lab based upon this material. The sections have been organized to allow a natural flow or progression of questions while performing the Outside Lab Assessment. Finally, the last section called “Outside Lab Assessment Results &Comments Card ,” is a copy of the forms used to write the final assessment report. It includes a copy of a survey that may be filled out by the outside lab after the assessment is complete. It is through this feedback that we can continue to make the assessment process more valuable.This document shall provide all the necessary information to complete an Outside Lab Assessment and Final Report. If any more information is required, the outside lab shall contact the lead assessor. This person can answer any remaining questions.It is our intent that this process will provide Global Whirlpool Technology and Procurement personnel with a solidunderstanding of each Outside Lab ’s capabilities such that enlightened decisions can be made regarding potential testing outsourcing.AUDITEE PREPARATION GUIDELINESAUDITEE: This checklist is provided as an aid to help prepare you for your upcoming Outside Lab Capability Assessment . Basically, a Whirlpool team will be assessing your lab capabilities relative to specific Whirlpool needs and requirements. The key to a successful and efficient audit is preparation, both on the part of the auditee and the audit team. Your responsibility, as Auditee, is to make sure that the following items have been addressed and available as needed.A. Has the agenda for the day(s) of the audit been established and communicated? This is the responsibility ofWhirlpool Lead Assessor. If not complete, please contact the Lead Assessor.Document Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.B. Have you reviewed the Outside Lab assessment standard, understand the requirements and used them toperform a self-evaluation prior to the official visit? Have you sent a copy of your self-assessment to the Whirlpool Lead assessor? C. Do you understand the scoring system?D. Is your documentation and supporting evidence readily available? Suppliers should prepare for the assessmentby gathering initial documentation & evidence by key, summarize it, organize it in a manner that the information can be rapidly selected for discussion, and prepare for additional background evidence should the Lead Assessor desire additional material.Key Point: The audit can be conducted in a much more efficient manner if the supporting documentation isarranged in a sequence corresponding to the Whirlpool requirements.The audit documentation can be flowcharted according to your design process. You may arrange the evidence in that order and notify the lead auditor of the desired flow and the lead auditor will follow your recommendations by re-arranging the assessment keys in the order you have recommended (note: all keys must be completed).E. Have you identified the key contact person (Lab Manager or equivalent) to represent your organization andinterface with the lab assessment team? F. Do you have lead people identified for specific sections of the audit (i.e. reliability, equipment calibration,personnel experience, document management, planning, etc.)? Are they “ready ” when called upon? G. Has a conference room been reserved for the audit team to use? H. Is a telephone available? I.Given the expected complexity of the audit and the size of the facility, has the overall time duration of the audit been estimated and consideration given to necessary breaks, including lunch arrangements, if needed? (Note: In the interest of time, a quick working lunch brought to the audit location is typically preferred.)J. Is any safety equipment required (i.e. safety glasses, steel toe shoes, hearing protection, etc.)?Finally, if you have any other questions or concerns they can and should be resolved with the Whirlpool Certified Lead Assessor prior to the actual audit day.Document Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.SUGGESTED ASSESSMENT AGENDAACTIVITIES:EST. DURATIONIntroduction (Team members/Auditee representatives) .................................................................. 10 - 20 min. Auditee overview of Lab Operation & Facilities .............................................................................. 30 min. Lab Facility Tour ........................................................................................................................... 30 min - 1 Hr. Lab Capability Assessment ............................................................................................................ 4 - 6 Hrs. Scoring & Report Development (Whirlpool Team Only) ................................................................... 30 min – 1 Hr. Closure Meeting ............................................................................................................................ 30 - 45 min.Note: This suggested agenda does not take into account the size or complexity of the location being assessed. The estimated duration should be seen as a guideline only. A typical assessment can take anywhere from 5.0 hr. to 9.0 hrs .Outside Lab Capability Assessment TopicsKey No.KEY NAMEL1 QUALITY SYSTEMS (equipment & data integrity) L2 MATERIALS TESTINGL3 CODES & REGULATORY REQUIREMENTS L4 TEST SPECIFICATIONS & PROCEDURES L5 TEST PLANS L6 RELIABILITYL7 LAB PRODUCT APPROVAL PROCESS L8 LAB PERSONNAL EXPERIENCEL9PRODUCT EXPERIENCE AND MARKET EXPERIENCEDocument Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.REQUIREMENT STATEMENTS AND GUIDELINESAs mentioned in the Foreword, this audit was designed to evaluate all three dimensions of a lab ’s capability; the Personnel , Equipment, and Documentation . To achieve this, each assessment page is laid out in the following manner: The “KEY ” statements are the first statements written in “Bold ” letters on top of every page in the assessment. The keyDocument Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.Key ScoringAs indicated above, all keys have as a scoring technique a series of incremental points. Within each point are a number of ‘criteria statements ’ that correlate directly with increased compliance to the requirements of the key. From point-to-point these criteria build upon each other in a progressive manner toward excellence in the “Key ” subject matter.For the purposes of scoring, to achieve the “point being evaluated ” the auditee must, in the opinion of the Lead Assessor , meet or exceed all of the criteria based statements assigned to it . Only after meeting the current ‘point ’ requirements may the assessor look toward the next level of incremental criteria. Also, as noted above, to aid in scoring decisions, half-point scores (0.5, 1.5, or 2.5) are permissible.If all of the criteria are not met, the score shall be recorded at the previous “point ” level or, as appropriate, at the half-point score between the previous score and the next incremental score. Key ScoringPOINTSCRITERIA0 Non-Existent – System requirements have not been addressed; there is essentially no evidence of implementation or compliance.1 Traditional - System requirements may informally exist but they are unstructured and potentially inefficient. There is minimal compliance toward required standards.2 Learning - Adequate awareness and understanding of the preferred approach with basic proficiency and implementation levels, reasonable documentation.3 Leading – Full awareness and understanding of the preferred approach with effective and efficient implementation levels, solid documentation, an operational model.Lead Assessor QuestionsThe Lead Assessor Questions shown with each key are intended only as “thought provokers ” or “response generators ”. Their sole purpose is to stimulate supplier discussion on the key topic in a manner applicable to the key ’s scoring criteria. They are not meant to be “all inclusive ”; thus a supplier should focus their attention on the scoring criteria and not the lead assessor questions.Overlap of Key ContentFrom time-to-time it is fully expected that the content of various “Keys ” will overlap with the content of similar keys. To a degree, this is planned into the assessment. The repetition of seeing a topic in multiple areas of this assessment simply signifies the importance of its content.While this may spark some discussion regarding fairness of scoring if the auditee has a particular weakness in the duplicated area; it needs to be recognized as well that if the auditee has strength in this area, their strength will be likewise be multiplied throughout the assessment.Document Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.None, No, Some, Occasional, Most, Majority, All and Always in Criteria Statements:Many of the Results Oriented criteria statements are specifically designed to probe the level of results that the design system should create. There are four levels of evaluation for these questions that contain results oriented requirements. These four levels can be recognized by the use of the words “None, Some, Most and All ” (and their synonyms) in the evaluation criteria. The meaning of these words can be reasonably quantified as shown in the following table:LEVEL RANGE None, no 0 – 5 % Some, occasional 6 - 50 % Most, majority 51 - 85 % All, always86 - 100 %Multiple Outside Lab OperationsIf an Outside Lab has multiple lab operations (i.e. an automotive lab, an appliance lab, a lab for all others, etc.) for the purpose of managing development, cost, and efficiency, the Whirlpool Outside Lab Assessment shall be applied to the section of the Outside Lab ’s business that would typically be utilized to test Whirlpool parts and product.ASSESSMENT STATUSAuditee Status:In addition to the assessment scores, auditees are classified under one of the four different status choices. This status is with regard only to the capability assessment. Additional reviews of specific facility, equipment, fixtures, and test procedure reviews are necessary for final determination of qualification level. These four status choices are Full Qualification , Conditional Qualification, Qualification in Process, and No Qualification . See matrix below:Assessment StatusCriteria(assumes all Keys are being assessed)Full Qualification Assessment that has a minimum score of 2 points or more for each key.Conditional Qualification Assessment that has less than a minimum score of 2 points for any key, but has documented an improvement plan that is acceptable to Whirlpool, with regard to quality and schedule.Qualification InProcessAssessment that is not complete, but plans are in place.No QualificationNo plans or desire to qualify currently.Document Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.OUTSIDE LABASSESSMENTREQUIREMENTSDocument Name:Global Outside Lab QualificationProcedureDate Revised:21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.KEY #L1 - QUALITY SYSTEM (EQUIPMENT & DATA INTEGRITY)Description: This ‘Key ’ is designed to understand the process for maintaining integrity of their test equipment, test and equipment procedures (work instructions), and test records. Lead Assessor Questions:1. What is your process to calibrate & update laboratory test equipment?2. What is your process for updating test / equipment procedures or work instructions?3. What is your document control process for test records?4. What independent lab certifications or accreditations do you currently hold? (ie. ISO-17025, UL, etc.) 0 pts There is no evidence of test equipment calibrationNo evidence of a process to maintain control of test procedures (work instructions) andtest records.1 ptSome evidence of acceptable test equipment calibration; some examples of expiredcalibration tagsAn informal process to maintain control of test data & documentation exists (procedures,work instructions, etc.).Some test procedures are out-of-date or do not match actual practice2 ptsMost equipment has acceptable calibration and measurement systems analysis evidenceavailableA formal process to maintain control of test data & documentation exists (procedures,work instructions, etc.).Most test procedures are up-of-date and match actual practiceThere exists evidence that key test procedures are reviewed periodically3 ptsThe lab is currently ISO-17025 accredited OR meets the following requirements:All equipment has acceptable calibration and measurement systems analysisevidence availableAll test data (records) is stored in an easily accessible location, controlled through aformal document control system, and are kept for set periods of time (e.g. records retention)All test procedures are up-of-date and match actual practiceAll test procedures are reviewed per schedule or process trigger (evidence required) Equipment is calibrated based upon MSE / MSA needs or control chartingNotes* - calibratedbased upon factual, demonstrated evidence that ‘control ’ has been lost in the measurement device as opposed to calibration based upon a selected time interval.Document Name: Global Outside Lab QualificationProcedureDate Revised: 21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.KEY #L2 – MATERIALS TESTINGDescription: The Auditee may be expected to have a fully equipped materials testing lab to analyze and test materials for proper formulation and material properties analysis during design and development. Expected scope would be materials applicable to the industry of the products being tested.Lead Assessor Questions:1. What material testing capability do you have at this location?2. Do you have all the material testing equipment needed for your products?3. Do you have plans to update the materials testing lab? 0 pts There are no materials testing capabilities at this locationAll materials are contracted out for testing and/or analysis1 ptsSome material testing is completed at this locationThe more difficult material testing is contracted outMost auditee test personnel have less than (2) years of test experienceMost materials testing is done based upon informal, unapproved procedures2 pts Most materials testing is completed at this locationMost material testing is completed with formal, detailed test procedures and analysisreports.Most test result records are archived for future referenceSome auditee test personnel have greater than (5) years of test experienceSome test personnel have (2) or more years of formal college training3 pts All material testing is completed with formal, detailed test procedures and analysisreports.All test result records are archived for future referenceAll test result records are archived and easily retrieved for future referenceSome auditee test personnel have greater than (10) years of test experienceMost test personnel are degreed engineersNotesDocument Name: Global Outside Lab QualificationProcedureDate Revised: 21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.KEY #L3 – CODES & REGULATORY REQUIREMENTSDescription: This ‘Key ’ is intended to understand how codes and regulatory requirements are implemented and validated at the auditee ’s facility. It also is intended to assess the competency of personnel associated with the codes and regulatory operations.Lead Assessor Questions:1. Please describe the methods used in your product development group to ensure adherence to regulatory agency codesand product safety requirements.2. Please describe your level of certification (of lab and technicians) by appropriate codes agencies (e.g. UL, CSA, IEC,etc.).0 pts No identified codes function at this design locationNo codes agency certification of lab and/or technicians Auditee expects all codes & regulatory requirements to be their customer ’s responsibility 1 ptSome engineering change notice approvals include a sign-off from a codes/safety standpoint There is some evidence that outside codes houses are leveraged to minimize the risk that regulatory gaps may exist 2 ptsSome codes engineer(s) are in place at auditees design facility Some codes agency certification of auditees lab and/or technicians – or - some evidence that outside codes houses are leveraged Most engineering change notices are reviewed and signed-off by a codes/safety expert Most codes requirements are completed by product release Most code engineer test requirements are fully documented 3 ptsLead codes engineer has more than 5 years experience in the Product Approval and Lab Operations All engineering change notices AND temporary change authorizations have a codes/safety sign-off All appropriate labs and technicians are certified by regional appropriate codes agency All codes requirements are completed by product release All code engineer test requirements are fully documented NotesDocument Name: Global Outside Lab QualificationProcedure Date Revised: 21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.KEY #L4 - TEST SPECIFICATIONS & PROCEDURESDescription: Test specifications and procedures are the backbone of the testing and validation process. Their accuracy and use drive the verification and fitness for use decisions that must be made for new and revised products. This key investigates the auditee ’s test specification management system.Lead Assessor Questions:1.What is your process to develop and update test specifications? 1.Is there linkage of test specifications to customer needs? 2.How is data from the field used to create or improve specifications? 3.Who reviews newly created specifications prior to formal release? What is their authority? 4.How are specifications / test procedures reviewed over time? 5. What independent lab certifications or accreditations do you currently hold? (ie. ISO-17025, UL, etc.)0 ptsThere is no process to develop or update test specifications 1 pt There is limited input from design, customer, and field test results into test specificationcreationTest specifications are informally written by individuals who individually put them to useProcedures / test specifications are informally reviewed2 pts A formal process exists for the development and updating of test specifications; however, itmay not always be used as individually generated test specifications still occasionally existThere is some input from ‘the customer ’ and ‘field test results ’ into test specificationdevelopmentThere is some collaboration between design and the lab organizations in test specificationcreationReleased procedures / test specifications are formally reviewed to ensure correctness;review schedule is variable3 pts The lab is currently ISO-17025 accredited OR meets the following requirements:A formal, approved process for the development and updating of specifications existsand its use is a business requirement.Most specifications are developed based upon customer intended functions and are tiedto customer needs / benefits with historical data from the fieldA great deal of collaboration exists between design and lab organizations in testspecification creationReleased procedures / test specifications are regularly reviewed by a cross-functionaltechnical team according to a developed scheduleNotesDocument Name: Global Outside Lab QualificationProcedureDate Revised: 21-May-08© 20yy – 20yy Whirlpool Corporation. The subject matter shown hereon is disclosed in confidence to the extent it is original with Whirlpool.Disclosure to other parties except in filling Whirlpool orders is forbidden.KEY #L5 – TEST PLANSDescription: This ‘Key ’ evaluates the process used to develop and implement test plans for testing and approving products that meet customer requirements. It includes how test plans are continuously improved with new requirements such that results achieved from approved product lead to better products.Lead Assessor Questions:1.How are test plans for new features / products developed? Who has input to their creation? 2.Please describe how DFMEA ’s provide directional content to the creation of your test plans. 3.Is there a standardized template used for test plan development? 4.When in the development cycle are test plans created and how are they linked to the customer specifications? 5.Are new tests developed when new specifications are created? 0 ptsAuditee has no formal test plans - they do minimal testing Auditee does not create their own test plans (customer assumes this responsibility) 1 pt Evidence shows only standard tests are used and minimal or no critical thought is given for newtests.Tests plans are typically created close to product launch (reacting to the timetable)The Product Approval Group & Design Engineering only occasionally interact in test plandevelopmentThere is evidence that DFMEA ’s are used in some test plan creation.2 pts Test plans are based on prior test documents; no specific regional /global template is usedNew, unique tests are developed for unique features or new product based upon customerinsightsSome test plans are developed early in the process.Test plans are jointly developed between the Product Approval Group and Design EngineeringGroup with the Product Approval Group having the overall authority on most test plan content.There is some test plan coordination / interaction with customers (i.e. effect on other customerparts).There is evidence that DFMEA ’s are used in most test plan creation.3 ptsTest plan development template (w/standard tests) used to drive critical thought for all projecttest plans.There is clear evidence of new tests proactively developed and based upon customer insights.These tests are shown to be linked to newly developed product specificationsTest plans are jointly developed with the Product Approval Group and Design Engineering, andit is clearly documented that the Product Approval engineer has the final authority on all test plan content.There is considerable test plan coordination / interaction with customers (i.e. effect on othercustomer parts).There is evidence that DFMEA ’s are used in all test plan creation.Most test plans are developed early in the process.。

申请人：FUJITSU LTD
POSE:To make coincide the level of software and firmware with each other and to dissolve the interchangeability among various programs with the firmware, by installing the firmware for processing dedicated to instruction and a controlling storage initially setting section which operates the firmware. CONSTITUTION:An operating system 1 calls a controlling storage initially setting section 2 at the time of, for example, rising of the system. The controlling storage initially setting section 2 issues a dedicated instruction 3, whose initially setting information table 4 is designated in an operand field. After the instruction code S of the dedicated instruction 3 is decoded, the control is handed over to firmware 5 for processing dedicated instruction. The firmware 5 writes a selected microinstruction group in a prescribed area of a controlling storage 8 for specific processing after obtaining the address of the initially setting information table 4 by fetching the operand field of the dedicated instruction 3 and by accessing the initially setting information table 4. Therefore, execution of a specific processing at the firmware becomes possible.

Altera Remote Update IP Core User GuideThe Altera Remote Update IP core implements a remote system update using dedicated remote systemupgrade circuitry available in supported devices.Remote system update helps you deliver feature enhancements and bug fixes without recalling yourproduct, and reduces time-to-market and extends product life. The Altera Remote Update IP coredownloads a new configuration image from a remote location, stores the image in a configuration device, and upgrades the configuration circuitry to start a reconfiguration cycle.The dedicated circuitry performs error detection during and after the configuration process. When thededicated circuitry detects errors, the circuitry facilitates system recovery by reverting back to a safe,default factory configuration image and then provides error status information.The following figure shows a functional diagram for a typical remote system update process.Figure 1: Typical Remote System Update ProcessNote:Altera recommends you to use 20–MHz f MAX for all devices.Related Information•Configuration Center•ALTREMOTE_UPDATE Knowledge BaseInstalling and Licensing IP CoresThe Altera IP Library provides many useful IP core functions for production use without purchasing anadditional license. You can evaluate any Altera® IP core in simulation and compilation in the Quartus® II software using the OpenCore® evaluation feature. Some Altera IP cores, such as MegaCore® functions,require that you purchase a separate license for production use. You can use the OpenCore Plus feature to evaluate IP that requires purchase of an additional license until you are satisfied with the functionality and performance. After you purchase a license, visit the Self Service Licensing Center to obtain a licensenumber for any Altera product.© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.ISO 9001:2008 Registered101 Innovation Drive, San Jose, CA 95134Figure 2: IP Core Installation PathContains the Quartus II softwareContains the Altera IP Library source code <IP core name> - Contains the IP core source filesNote:The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is<home directory>/altera/ <version number>.Related Information•Altera Licensing Site•Altera Software Installation and Licensing ManualCustomizing and Generating IP CoresYou can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and parameter editor allow you to quickly select and configure IP core ports, features, and output files.IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog ) and parameter editor help you easily customize andintegrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,and generate files representing your custom IP variation.Note:The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard ™Plug-InManager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.The IP Catalog lists IP cores available for your design. Double-click any IP core to launch the parameter editor and generate files representing your IP variation. The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Qsys system file (.qsys ) or Quartus II IP file (.qip ) representing the IP core in your project. You can also parameterize an IP variation without an open project.Use the following features to help you quickly locate and select an IP core:•Filter IP Catalog to Show IP for active device family or Show IP for all device families .•Search to locate any full or partial IP core name in IP Catalog. Click Search for Partner IP , to access partner IP information on the Altera website.•Right-click an IP core name in IP Catalog to display details about supported devices, open the IP core's installation folder, andor view links to documentation.2Customizing and Generating IP CoresUG-310052015.01.23Altera CorporationFigure 3: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationNote:The IP Catalog is also available in Qsys (View > IP Catalog). The Qsys IP Catalog includesexclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, refer to Creating a System with Qsys in the Quartus II Handbook .Using the Parameter EditorThe parameter editor helps you to configure IP core ports, parameters, and output file generation options.•Use preset settings in the parameter editor (where provided) to instantly apply preset parameter values for specific applications.•View port and parameter descriptions, and links to documentation.•Generate testbench systems or example designs (where provided).UG-310052015.01.23Using the Parameter Editor3Altera CorporationSend FeedbackFigure 4: IP Parameter EditorsView IP port and parameter detailsApply preset parameters for specific applicationsSpecify your IP variation nameand target device Legacy parameter editorsSpecifying IP Core Parameters and OptionsThe parameter editor GUI allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus II software. Refer to Specifying IP Core Parameters and Options (Legacy Parameter Editors) for configuration of IP cores using the legacy parameter editor.1.In the IP Catalog (Tools > IP Catalog ), locate and double-click the name of the IP core to customize.The parameter editor appears.2.Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys . Click OK .3.Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.•Optionally select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.•Specify parameters defining the IP core functionality, port configurations, and device-specific features.•Specify options for processing the IP core files in other EDA tools.4.Click Generate HDL , the Generation dialog box appears.5.Specify output file generation options, and then click Generate . The IP variation files generate according to your specifications.6.To generate a simulation testbench, click Generate > Generate Testbench System .4Specifying IP Core Parameters and OptionsUG-310052015.01.23Altera Corporation7.To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > HDL Example.8.ClickFinish . The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files in Project to add the file.9.After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.Figure 5: IP Parameter EditorView IP port and parameter detailsApply preset parameters for specific applicationsSpecify your IP variation name and target device Upgrading IP CoresIP core variants generated with a previous version of the Quartus II software may require upgrading before use in the current version of the Quartus II software. Click Project > Upgrade IP Components to identify and upgrade IP core variants.The Upgrade IP Components dialog box provides instructions when IP upgrade is required, optional, or unsupported for specific IP cores in your design. You must upgrade IP cores that require it before you can compile the IP variation in the current version of the Quartus II software. Many Altera IP cores support automatic upgrade.The upgrade process renames and preserves the existing variation file (.v , .sv , or .vhd ) as <my_variant>_BAK.v , .sv , .vhd in the project directory.UG-310052015.01.23Upgrading IP Cores 5Altera CorporationSend FeedbackTable 1: IP Core Upgrade StatusBefore you begin•Archive the Quartus II project containing outdated IP cores in the original version of the Quartus II software: Click Project > Archive Project to save the project in your previous version of the Quartus II software. This archive preserves your original design source and project files.•Restore the archived project in the latest version of the Quartus II software: Click Project > Restore Archived Project . Click OK if prompted to change to a supported device or overwrite the project database. File paths in the archive must be relative to the project directory. File paths in the archive must reference the IP variation .v or .vhd file or .qsys file (not the .qip file).1.In the latest version of the Quartus II software, open the Quartus II project containing an outdated IP core variation. The Upgrade IP Components dialog automatically displays the status of IP cores in your project, along with instructions for upgrading each core. Click Project > Upgrade IP Components to access this dialog box manually.2.To simultaneously upgrade all IP cores that support automatic upgrade, click Perform Automatic Upgrade . The Status and Version columns update when upgrade is complete. Example designs provided with any Altera IP core regenerate automatically whenever you upgrade the IP core.6Upgrading IP CoresUG-310052015.01.23Altera CorporationFigure 6: Upgrading IP CoresDisplays upgrade status for all IP cores in the Project Upgrades all IP core that support “Auto Upgrade”Upgrades individual IP cores unsupported by “Auto Upgrade”Checked IP coressupport “Auto Upgrade”Successful “Auto Upgrade”Upgrade unavailableDouble-click to individually migrate Example 1: Upgrading IP Cores at the Command LineYou can upgrade IP cores that support auto upgrade at the command line. IP cores that do not support automatic upgrade do not support command line upgrade.•To upgrade a single IP core that supports auto-upgrade, type the following command:quartus_sh –ip_upgrade –variation_files <my_ip_filepath/my_ip>.<hdl> <qii_project>Example:quartus_sh -ip_upgrade -variation_files mega/pll25.v hps_testx•To simultaneously upgrade multiple IP cores that support auto-upgrade, type the following command:quartus_sh –ip_upgrade –variation_files “<my_ip_filepath/my_ip1>.<hdl>; <my_ip_filepath/my_ip2>.<hdl>” <qii_project>Example:quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.v;mega/pll3.v" hps_testxNote:IP cores older than Quartus II software version 12.0 do not support upgrade.Altera verifies that the current version of the Quartus II software compiles the previous version of each IP core. The Altera IP Release Notes reports any verifica‐tion exceptions for Altera IP cores. Altera does not verify compilation for IP cores older than the previous two releases.UG-310052015.01.23Upgrading IP Cores7Altera CorporationSend FeedbackRelated InformationAltera IP Release NotesSimulating Altera IP Cores in other EDA ToolsThe Quartus II software supports RTL and gate-level design simulation of Altera IP cores in supported EDA simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, and running your simulation.You can use the functional simulation model and the testbench or example design generated with your IP core for simulation. The functional simulation model and testbench files are generated in a projectsubdirectory. This directory may also include scripts to compile and run the testbench. For a complete list of models or libraries required to simulate your IP core, refer to the scripts generated with the testbench.You can use the Quartus II NativeLink feature to automatically generate simulation files and scripts.NativeLink launches your preferred simulator from within the Quartus II software.Figure 7: Simulation in Quartus II Design FlowNote:Post-fit timing simulation is not supported for 28nm and later device archetectures. Altera IPsupports a variety of simulation models, including simulation-specific IP functional simulation models and encrypted RTL models, and plain text RTL models. These are all cycle-accurate models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators. For some cores, only the plain text RTL model is generated, and you can simulate that model. Use the simulation models only for simulation and8Simulating Altera IP Cores in other EDA ToolsUG-310052015.01.23Altera Corporationnot for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.Related InformationSimulating Altera DesignsArria 10 DevicesThis section covers the remote system configuration modes, components, parameter, ports, andparameter settings for Arria ® 10 devices.Remote System Configuration ModeArria 10 devices support remote configuration mode only.Remote configuration supports “Direct to application” and “Application to Application” update. Remote configuration only supports 4-bytes address scheme so there is no support for devices with densities smaller than 128Mbit.Figure 8: Transitions Between Factory and Application Configurations in Remote Update ModeStart Address > 0 and not 32Start Address = 32When used with low-voltage quad-serial configuration (EPCQ-L) devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 512 pages in theEPCQ-L256 device and 1024 pages in the EPCQ-L512 device, in which the minimum size of each page is 512Kbits. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.UG-310052015.01.23Arria 10 Devices 9Altera CorporationSend FeedbackRemote System Configuration ComponentsTable 2: Remote System Configuration Components in Arria 10 Devices10Remote System Configuration ComponentsUG-310052015.01.23Altera CorporationParameter SettingsTable 3: Altera Remote Update IP Core Parameters for Arria 10 DevicesPortsTable 4: Altera Remote Update IP Core Ports for Arria 10 DevicesUG-310052015.01.23Parameter Settings 1112Ports UG-310052015.01.23 ArrayAltera CorporationUG-310052015.01.23Ports13Parameters For Arria 10 devices, mapping to each parameter type and corresponding parameter bit width is defined as follow:Table 5: Parameter Type and Corresponding Parameter Bit Width Mapping14Parameters UG-310052015.01.23Altera CorporationArria II, Arria V, Cyclone V, Stratix IV, and Stratix V DevicesThis section covers the remote system configuration modes, components, parameter, ports, and parameter settings for Arria II, Arria V, Cyclone ® V, Stratix ® IV, and Stratix V devices.Remote System Configuration ModeArria II, Arria V, Cyclone V, Stratix IV, and Stratix V devices support remote configuration mode only.UG-310052015.01.23Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices 15Remote Configuration ModeFigure 9: Remote Configuration ModeError When used with serial configuration (EPCS) or quad-serial configuration (EPCQ) devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of each page is 512Kbits. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.Remote System Configuration ComponentsTable 6: Remote System Configuration Components in Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices16Remote System Configuration Components UG-310052015.01.23Altera CorporationParameter SettingsTable 7: Altera Remote Update IP Core Parameters for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V DevicesUG-310052015.01.23Parameter Settings 17POF checking feature detect and verify the existence of an application configuration image before the image is loaded. Loading an invalid application configuration image may lead to unexpected behaviour of the FPGA including system failure. Example of invalid application configuration images are:• A partially programmed application image • A blank application image •An application image assigned with a wrong start addressPortsTable 8: Altera Remote Update IP Core Ports for Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V Devices18Ports UG-310052015.01.23Altera CorporationUG-310052015.01.23Ports1920Ports UG-310052015.01.23 ArrayAltera CorporationUG-310052015.01.23Ports 21Altera CorporationSend Feedback22PortsUG-310052015.01.23Altera CorporationParametersFor Arria II, Arria V, Cyclone V, Stratix IV, and Stratix V devices, mapping to each parameter type and corresponding parameter bit width is defined as follow:Table 9: Parameter Type and Corresponding Parameter Bit Width MappingUG-310052015.01.23Parameters 23Altera CorporationSend FeedbackCyclone III and Cyclone IV DevicesThis section covers the remote system configuration modes, components, parameters, ports, and remote update operation for Cyclone III and Cyclone IV devices.24Cyclone III and Cyclone IV DevicesUG-310052015.01.23Altera CorporationRemote System Configuration ModeCyclone IV devices support remote configuration mode only.Remote Configuration ModeFigure 10: Remote Configuration ModeErrorCyclone IV E devices support the active parallel (AP) configuration scheme for Altera devices.When used with EPCS or EPCQ devices, the remote update mode allows a configuration space to start at any flash sector boundary, allowing a maximum of 128 pages in the EPCS64 device and 32 pages in the EPCS16 device, in which the minimum size of each page is 512Kbits. Additionally, the remote update mode features a user watchdog timer that can detect functional errors in an application configuration.Remote System Configuration ComponentsTable 10: Remote System Configuration Components in Cyclone IV DevicesUG-310052015.01.23Remote System Configuration Mode 25Altera CorporationSend Feedback26Remote System Configuration ComponentsUG-310052015.01.23Altera CorporationParameter SettingsTable 11: Altera Remote Update IP core Parameters for Cyclone IV DevicesUG-310052015.01.23Parameter Settings 27Altera CorporationSend FeedbackPortsTable 12: Altera Remote Update IP Core Ports for Cyclone IV Devices28PortsUG-310052015.01.23Altera CorporationUG-310052015.01.23Ports 29Altera CorporationSend Feedback30PortsUG-310052015.01.23Altera CorporationUG-310052015.01.23Ports3132Ports UG-310052015.01.23 ArrayAltera CorporationUG-310052015.01.23Ports33ParametersFor Cyclone IV devices, mapping to each parameter type and corresponding parameter bit width is defined as follow:Table 13: Mapping to Each Parameter Type and Corresponding Parameter Bit Width34ParametersUG-310052015.01.23Altera CorporationRemote Update OperationNote:read_source specifies whether a parameter value is read from the current or a previous state. Formore information, refer to Table 14.Note:Perform remote update operations in the corresponding master state machine (MSM) mode.UG-310052015.01.23Remote Update Operation 3536Remote Update Operation UG-310052015.01.23 ArrayAltera Corporationread_sourceThe following table lists the details for read_source . read_source specifies whether a parameter value is read from the current or a previous state. When you trigger the read operation, all contents in status register or input register latched to the data_out node in the Altera Remote Update IP core.Table 14: read_sourceState RegisterThe previous state register 1 reflects the current application configuration and the previous state register 2reflects the previous application configuration.UG-310052015.01.23Remote Update Operation 37Figure 11: State RegisterBack to factory(State register 1 reflects to current application which is application 2, while the state register 2 is reflects to previous application which is application 1)Design Example: Factory Image and Application Image Programming SequenceThis design example illustrates the sequence of programming the Factory Image and Application Image by using the programmer in Quartus II.In this example, you will be perform the following activities:•Generate both SRAM object file (.sof ) for Application Image and Factory Image.•Convert Programming file to generate the JTAG indirect configuration file (.jic )•Program the .jic file into the FPGAThe following instructions guide you to perform the design example tasks:1.Unzip the contents of the RSU.zip file to your working directory on your PC.2.In the Quartus II software, click Open Project in the File menu,pile Application Image:38Design Example: Factory Image and Application Image Programming SequenceUG-310052015.01.23Altera Corporationa.Browse to the folder in which you unzipped the files and open the Application_Image.qpf .b.Click Yes in the message box "Do you want to overwrite the database for C:/your workingdirectory/Application_Image.qpf created by Quatus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"c.On the Processing menu, choose Start Compilation .d.Click OK when the full compilation successful dialog box appears.e.Application_Image.sof will be generated in c:\your working directory\output_files .f.Click close project in the file menu.4.4. Compile Factory Image:a.Browse to the folder in which you unzipped the files and open the SVRSU.qpf .b.Click Yes in the message box "Do you want to overwrite the database for C:/your working directory/Application_Image.qpf created by Quatus II 64-Bit Version 13.0.a Build 232 Service Pack 1 SJ Full version?"c.Choose Start Compilation on the Processing menu .d.Click OK when the full compilation successful dialog box appears.e.Factory_Image.sof will be generated in c:\your working directory\output_files .5.On the File Menu, click Convert Programming Files and select the detail as shown below:•Programming File type: JTAG Indirect Configuration File (.jic)•Select Configuration Device: EPCQ 128•Mode: Active Serial x4•File name: c:/your working directory/output_file.jic•Flash loader: click add device and choose 5CEFA7ES•SOFT DATA PAGE_0: click Add File and select the factory image file (SVRSU.sof )•SOFT DATA PAGE_0: click Add File and select the Application image file (Application_Image.sof )•Click Generate .•Click OK when the dialogue box of .jic file successfully generated appears.6.On the Tool Menu, click Programmer:a.Make sure the board is power up and the USB Blaster is connected between computer and the board. This design example uses USB Blaster and JTAG mode.b.Click Auto Detect .c.Right click on the 5CEFA7ES and select change file .d.Browse to the output_file.jic that was generated in previous steps.e.Tick the Program/Configure checkbox and click Start .f.Configuration successful indicates the FPGA is configured successfully.Document Revision HistoryThe following table lists the revision history.UG-310052015.01.23Document Revision History39Table 15: Document Revision History40Document Revision HistoryUG-310052015.01.23Altera CorporationUG-310052015.01.23Document Revision History 41Altera CorporationSend Feedback42Document Revision History UG-310052015.01.23Altera CorporationUG-310052015.01.23Document Revision History 43Altera Corporation Send Feedback。

Altera ASMI Parallel II IP Core User GuideUG-200682017.05.08Last updated for Intel® Quartus® Prime Design Suite: 17.0SubscribeSend FeedbackContents Contents1 Altera ASMI Parallel II IP Core User Guide (3)1.1 Ports (4)1.2 Parameters (5)1.3 Register Map (6)1.4 Operations (8)1.4.1 Control Status Register Operations (8)1.4.2 Memory Operations (9)1.5 Document Revision History (10)Altera ASMI Parallel II IP Core User Guide21 Altera ASMI Parallel II IP Core User GuideThe Altera ASMI Parallel II IP core provides access to the Intel FPGA configurationdevices which are the quad-serial configuration (EPCQ) and low-voltage quad-serialconfiguration (EPCQ-L) device.Other than features supported by Altera ASMI Parallel IP core, the Altera ASMI ParallelII IP core additionally supports:•Direct flash access (write/read) through the Avalon-Memory Map (Avalon-MM) interface.•Control register for other operations through the control status register (CSR) interface in Avalon-MM.The Altera ASMI Parallel II IP core is available for all Intel FPGA device families exceptthe MAX® series.Note: The Altera ASMI Parallel II IP core is supported in Quartus® Prime version 17.0 or laterRelated Links•Introduction to Intel FPGA IP CoresProvides general information about all Intel FPGA IP cores, includingparameterizing, generating, upgrading, and simulating IP cores.•Creating Version-Independent IP and Qsys Simulation ScriptsCreate simulation scripts that do not require manual updates for software or IPversion upgrades.•Project Management Best PracticesGuidelines for efficient management and portability of your project and IP files.•Altera ASMI Parallel IP Core User Guide•AN-720: Simulating the ASMI Block in Your Design1 Altera ASMI Parallel II IP Core User GuideIntel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.ISO 9001:2008 Registered1 Altera ASMI Parallel II IP Core User Guide1.1 PortsFigure 1.Ports Block DiagramTable 1.Ports DescriptionAltera ASMI Parallel II IP Core User Guide4Signal Width Direction Descriptionavl_mem_addrNInputAvalon-MM address bus. The address bus is in word addressing.The width of the address depends on the flash memory density minus 2.If you are using Arria ® 10, then the MSB bits will be used for chip select information. You can select the number of chip select needed in the parameter setting.•If you select 1 chip select in the parameter setting, there will beno extra bit added to avl_mem_addr .•If you select 2 chip selects, there will be one extra bit added to avl_mem_addr :—Chip 1— b’0—Chip 2—b’1•If user select 3 chip selects, there will be two extra bits added to avl_mem_addr :—Chip 1—b’00—Chip 2—b’01—Chip 3—b’10avl_mem_writedata 32Input Avalon-MM write data bus to the memory avl_mem_readddata 32Output Avalon-MM read data bus from the memory.avl_mem_rddata_valid 1Output Avalon-MM read data valid that indicates the memory read data is available.avl_mem_byteenble4InputAvalon-MM write data enable bus to memory. During bursting mode, byteenable bus will be logic high, 4’b1111.Clock and Resetclk 1Input Input clock to clock the IP core.reset_n1InputAsynchronous reset to reset the IP core.1Conduit Interface 2fqspi_dataout 4Bidirectional Input or output port to feed data from the flash device.qspi_dclk 1Output Provides clock signal to the flash device.qspi_scein1/3OutputProvides the ncs signal to the flash device.Related Links •Quad-Serial Configuration (EPCQ) Devices Datasheet •EPCQ-L Serial Configuration Devices Datasheet1.2 ParametersTable 2.Parameter Settings1Hold the signal for at least one clock cycle to reset the IP .2Available when you enable the Disable dedicated Active Serial interface parameter .1 Altera ASMI Parallel II IP Core User GuideAltera ASMI Parallel II IP Core User Guide5Parameter Legal Values DescriptionsEPCQ128,EPCQ256,EPCQ512,EPCQ-L256,EPCQ-L512,EPCQ-L1024Choose I/O mode NORMALSTANDARDDUALQUAD Selects extended data width when you enable the Fast Read operation.Disable dedicated ActiveSerial interface—Routes the ASMIBLOCK signals to the top level of your design.Enable SPI pins interface—Translates the ASMIBLOCK signals to the SPI pin interface.Enable flash simulationmodel—Uses the flash inside the device for simulation model.Number of Chip Select used12333Selects the number of chip select connected to the flash.Related Links•Quad-Serial Configuration (EPCQ) Devices Datasheet•EPCQ-L Serial Configuration Devices Datasheet•AN-720: Simulating the ASMI Block in Your Design1.3 Register MapTable 3.Register Map•Each address offset in the following table represents 1 word of memory address space.•All registers have a default value of 0x0.3Only supported in Arria 10 devices and other devices with Enable SPI pins interface enabled.1 Altera ASMI Parallel II IP Core User GuideAltera ASMI Parallel II IP Core User Guide61 Altera ASMI Parallel II IP Core User Guide4You only need to specify the sector address. The IP core will automatically construct the full address and send to the device.5You only need to specify the subsector address. The IP core will automatically construct the full address and send to the device.6Refer to the EPCQ-L Device Datasheet for information about single or stack-die device.Altera ASMI Parallel II IP Core User Guide71 Altera ASMI Parallel II IP Core User GuideOffset Register Name R/W Field Name Bit Width Description21SECTOR_PROTECT W Sector protect value4:05Value to write to statusregister to protect asector.22RD_MEMORY_CAPACITY_ID R Memory capacity value7:08Contains the informationof memory capacity ID.23 -Reserved32Related Links•Quad-Serial Configuration (EPCQ) Devices Datasheet•EPCQ-L Serial Configuration Devices Datasheet•Avalon Interface Specifications1.4 OperationsThe Altera ASMI Parallel II IP core interfaces are Avalon-MM compliant. For moredetails, please refer to the Avalon specification.Related LinksAvalon Interface Specifications1.4.1 Control Status Register OperationsYou can perform a read or write to a specific address offset using the Control StatusRegister (CSR).To execute the read or read operation for the control status register, perform thefollowing steps:1.Assert the avl_csr_write or avl_csr_read signal while theavl_csr_waitrequest signal is low (if the waitrequest signal is high, theavl_csr_write or avl_csr_read signal must to be kept high until thewaitrequest signal goes low.)2.At the same time, set address value on avl_csr_address bus. If it is a writeoperation, set value data on the avl_csr_writedata bus together with theaddress.3.If it is a read transaction, wait until avl_csr_readdatavalid signal is assertedhigh to retrieve the read data.•For operations that require write value to flash, you must perform write enable operation first.•You must read the flag status register every time you issue a write or erasecommand.•In case of support multiples flash devices, you must write chip select register to select the correct chip select before performing any operation to the specific flashdevice.Altera ASMI Parallel II IP Core User Guide8Figure 2.Read Memory Capacity Register Waveform ExampleFigure 3.Write Enable Register Waveform Example1.4.2 Memory OperationsThe ASMI Parallel II IP core memory interface supports bursting and direct flashmemory access. During direct flash memory access, the IP core performs the following steps to allow you to perform any direct read or write operation:•Write enable for write operation•Check flag status register to make sure the operation has been completed at the flash•Release waitrequest signal when operation completedMemory operations are similar to the Avalon-MM operations. You must set the correct value at address bus, write data if it is write transaction, drive burst count bus 1 if single transaction or desired burst count value and trigger the write or read signal.Figure 4.8-Word Write Burst Waveform ExampleFigure 5.8-Word Reading Burst Waveform ExampleFigure 6.1-Byte Write byteenable = 4’b0001Waveform Example1 Altera ASMI Parallel II IP Core User GuideAltera ASMI Parallel II IP Core User Guide91 Altera ASMI Parallel II IP Core User Guide1.5 Document Revision HistoryDate Version ChangesMay 20172017.05.08Initial release.Altera ASMI Parallel II IP Core User Guide10。