XILINX Virtex-5 FPGA系列

Symbol DescriptionSpeed GradeUnits -2I-1I-1MSequential DelaysT REG Clock to A–D outputs 1.43 1.73 1.73ns, Max T REG_MUX Clock to AMUX–DMUX output 1.55 1.87 1.87ns, Max T REG_M31Clock to DMUX output via M31 output 1.15 1.38 1.38ns, Max Setup and Hold Times Before/After Clock CLKT WS/T WH WE input0.24–0.040.29–0.020.29–0.02ns, MinT CECK/T CKCE CE input to CLK0.27–0.070.33–0.060.33–0.06ns, MinT DS/T DH A–D inputs to CLK 0.660.090.780.110.780.11ns, MinClock CLKT MPW Minimum pulse width0.700.850.85ns, MinNotes:1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” islisted, there is no positive hold time.DSP48E Switching CharacteristicsMaximum Frequency F MAXBlock RAM in all modes500450450MHz F MAX_CASCADE Block RAM in cascade configuration 450400400MHz F MAX_FIFO FIFO in all modes500450450MHz F MAX_ECC Block RAM and FIFO in ECC configuration375325325MHzNotes:1.TRACE will report all of these parameters as T RCKO_DO .2.T RCKO_DOR includes T RCKO_DOW , T RCKO_DOPR , and T RCKO_DOPW as well as the B port equivalent timing parameters.3.These parameters also apply to synchronous FIFO with DO_REG =0.4.T RCKO_DO includes T RCKO_DOP as well as the B port equivalent timing parameters.5.These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG =1.6.T RCKO_FLAGS includes the following parameters: T RCKO_AEMPTY , T RCKO_AFULL , T RCKO_EMPTY , T RCKO_FULL , T RCKO_RDERR , T RCKO_WRERR .7.T RCKO_POINTERS includes both T RCKO_RDCOUNT and T RCKO_WRCOUNT .8.The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.9.T RCKO_DI includes both A and B inputs as well as the parity inputs of A and B.10.These parameters also apply to RDEN.11.T RCO_FLAGS includes the following flags: AEMPTY , AFULL, EMPTY , FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT .Table 69:DSP48E Switching CharacteristicsSymbolDescriptionSpeed Grade Units-2I -1I -1M Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_{AA, BB, ACINA, BCINB}/TDSPCKD_{AA, BB, ACINA, BCINB}{A, B, ACIN, BCIN} input to {A, B} register CLK 0.210.230.260.300.260.30ns TDSPDCK_CC/TDSPCKD_CCC input to C register CLK0.160.310.200.370.200.50nsSetup and Hold Times of Data Pins to the Pipeline Register Clock TDSPDCK_{AM, BM, ACINM, BCINM}/TDSPCKD_{AM, BM, ACINM, BCINM}{A, B, ACIN, BCIN} input to M register CLK1.440.191.710.191.710.19nsSetup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_{AP , BP , ACINP , BCINP}_M/TDSPCKD_{AP , BP , ACINP , BCINP}_M {A, B, ACIN, BCIN} input to P register CLK using multiplier2.74–0.303.25–0.30 3.25–0.30ns TDSPDCK_{AP , BP , ACINP , BCINP}_NM/TDSPCKD_{AP , BP , ACINP , BCINP}_NM {A, B, ACIN, BCIN} input to P register CLK not using multiplier1.54–0.10 1.83–0.10 1.83–0.10ns TDSPDCK_CP/TDSPCKD_CP C input to P register CLK1.42–0.13 1.70–0.13 1.70–0.13ns TDSPDCK_{PCINP , CRYCINP , MULTSIGNINP}/TDSPCKD_{PCINP , CRYCINP , MULTSIGNINP}{PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK1.170.111.310.111.310.11nsSetup and Hold Times of the CE PinsTDSPCCK_{CEA1A, CEA2A, CEB1B,CEB2B}/TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}{CEA1, CEA2A, CEB1B, CEB2B} input to {A,B} register CLK 0.280.250.330.310.330.31nsTDSPCCK_CECC/TDSPCKC_CECC CEC input to C register CLK 0.210.210.260.280.260.28ns TDSPCCK_CEMM/TDSPCKC_CEMMCEM input to M register CLK0.290.210.360.260.360.26nsTable 68:Block RAM and FIFO Switching Characteristics (Cont’d)SymbolDescriptionSpeed Grade Units-2I -1I -1MPLL Switching Characteristics Table 74:PLL SpecificationSymbol DescriptionSpeed GradeUnits -2I-1I-1MF INMAX Maximum Input Clock Frequency710645645MHz F INMIN Minimum Input Clock Frequency191919MHz F INJITTER Maximum Input Clock Period Jitter<20% of clock input period or 1ns Max F INDUTY Allowable Input Duty Cycle: 19—49MHz25/75%Allowable Input Duty Cycle: 50—199MHz30/70%Allowable Input Duty Cycle: 200—399MHz35/65%Allowable Input Duty Cycle: 400—499MHz40/60%Allowable Input Duty Cycle: >500MHz45/55% F VCOMIN Minimum PLL VCO Frequency400400400MHz F VCOMAX Maximum PLL VCO Frequency120010001000MHzF BANDWIDTH Low PLL Bandwidth at T ypical(1)111MHz High PLL Bandwidth at Typical(1)444MHzT ST APHAOFFSET Static Phase Offset of the PLL Outputs120120120ps T OUTJITTER PLL Output Jitter(2)Note 1T OUTDUTY PLL Output Clock Duty Cycle Precision(3)±200±200±200ps T LOCKMAX PLL Maximum Lock Time(4)100100100µs F OUTMAX PLL Maximum Output Frequency for LX30T, LX85, LX110,LX110T, SX50T, and FX70T(I) devices667600N/A MHzPLL Maximum Output Frequency for LX155T, FX70T(M), andFX100T devices600550550MHz PLL Maximum Output Frequency for FX130T devices500450N/A MHzPLL Maximum Output Frequency for LX220T, LX330T, SX95T,SX240T, and FX200T devices500450N/A MHz F OUTMIN PLL Minimum Output Frequency(5) 3.125 3.125 3.125MHz T EXTFDVAR External Clock Feedback Variation<20% of clock input period or 1ns Max RST MINPULSE Minimum Reset Pulse Width555ns F PFDMAX Maximum Frequency at the Phase Frequency Detector500450450MHz F PFDMIN Minimum Frequency at the Phase Frequency Detector191919MHz T FBDELAY Maximum Delay in the Feedback Path3ns Max or one CLKIN cycle Notes:1.The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.2.Values for this parameter are available in the Architecture Wizard.3.Includes global clock buffer.4.The LOCK signal must be sampled after T LOCKMAX. The LOCK signal is invalid after configuration or reset until the T LOCKMAX time hasexpired.5.Calculated as F VCO/128 assuming output duty cycle is 50%.。

ＸｉｌｉｎｘＦＰＧＡ引脚功能详细介绍注：技术交流用，希望对大家有所帮助。

IO_LXXY_# 用户IO引脚XX代表某个Bank内唯一的一对引脚，Y=[P|N]代表对上升沿还是下降沿敏感，#代表bank 号2.IO_LXXY_ZZZ_# 多功能引脚ZZZ代表在用户IO的基本上添加一个或多个以下功能。

Dn：I/O（在readback期间），在selectMAP或者BPI模式下，D[15:0]配置为数据口。

在从SelectMAP读反馈期间，如果RDWR_B=1，则这些引脚变成输出口。

配置完成后，这些引脚又作为普通用户引脚。

D0_DIN_MISO_MISO1：I，在并口模式（SelectMAP/BPI）下，D0是数据的最低位，在Bit-serial模式下，DIN是信号数据的输入；在SPI模式下，MISO是主输入或者从输出；在SPI*2或者SPI*4模式下，MISO1是SPI总线的第二位。

D1_MISO2，D2_MISO3：I，在并口模式下，D1和D2是数据总线的低位；在SPI*4模式下，MISO2和MISO3是SPI总线的MSBs。

An：O，A[25:0]为BPI模式的地址位。

配置完成后，变为用户I/O口。

AWAKE：O，电源保存挂起模式的状态输出引脚。

SUSPEND是一个专用引脚，AWAKE是一个多功能引脚。

除非SUSPEND模式被使能，AWAKE被用作用户I/O。

MOSI_CSI_B_MISO0：I/O，在SPI模式下，主输出或者从输入；在SelectMAP模式下，CSI_B是一个低电平有效的片选信号；在SPI*2或者SPI*4的模式下，MISO0是SPI总线的第一位数据。

FCS_B：O，BPI flash 的片选信号。

FOE_B：O，BPI flash的输出使能信号FWE_B：O，BPI flash 的写使用信号LDC：O，BPI模式配置期间为低电平HDC：O，BPI模式配置期间为高电平CSO_B：O，在并口模式下，工具链片选信号。

fpga加密方法
FPGA（现场可编程门阵列）的加密方法主要有以下几种：
1. 自带加密功能的FPGA：一些FPGA供应商在其产品中集成了加密功能，如Xilinx的Virtex-2~5系列和ALtera的Stratix II~III系列。

这些FPGA 使用特定的加密算法，如DES或AES，对程序进行加密。

当程序被加载到FPGA内部的SRAM时，会被解密并执行。

这种方法的安全性较高，但需要使用特定系列的FPGA。

2. 在系统中增加可加密的MCU：对于没有自带加密功能的FPGA，可以在系统中增加一个可加密的MCU。

用户可以根据自己的需求编写加密算法，对FPGA程序进行加密。

加密后的程序被下载到Flash中，然后由MCU将其解密并加载到FPGA的SRAM中运行。

这种方法提供了更大的灵活性，但需要编写额外的加密和解密代码。

3. 使用DNA功能：某些FPGA芯片具有DNA功能，即每个芯片都有独特的序列号。

这种功能可以在设计中用于增加安全性，例如通过将序列号用于加密算法中，使得每个芯片的加密密钥都是唯一的。

这种方法可以在一定程度上防止程序被复制或克隆。

需要注意的是，无论采用哪种加密方法，都需要确保加密算法的安全性，并采取适当的措施来保护密钥和敏感数据。

同时，加密和解密操作可能会增加系统复杂性和功耗，因此在设计时应权衡利弊。

PCI-e高速数据采集卡的驱动与上位机软件设计孙文硕;赛景波【摘要】为了解决采集卡与上位机之间的海量数据传输问题,结合自行开发的高速数据采集卡,提出了一种基于PCI-e高速数据采集卡的设备驱动与上位机软件的开发方案.该方案对使用WinDriver开发设备驱动的开发步骤以及DMA传输的实现方法进行了介绍,对利用LabWindows/CVI设计上位机软件的方法予以阐述,并利用DLL动态链接库解决了采集卡与应用程序之间的通信.实验结果表明,在PCI-e X1链路下,数据采集速度可达到182MB/s,能够满足高速数据采集的要求.【期刊名称】《电子器件》【年(卷),期】2015(038)005【总页数】5页(P1126-1130)【关键词】高速数据采集;设备驱动;PCI Express;WinDriver;动态链接库【作者】孙文硕;赛景波【作者单位】北京工业大学,电子信息与控制工程学院,北京100022;北京工业大学,电子信息与控制工程学院,北京100022【正文语种】中文【中图分类】TP919EEACC：7210Gdoi：10.3969/j.issn.1005-9490.2015.05.030随着电子技术的高速发展，对数据采集的要求迅速提高。

在实际应用中，海量数据的信息处理、高帧频图像的数据采集以及在线视频的实时显示的实现，均需要以高速率的数据传输作为前提［1］。

如何实现海量数据的高速、实时传输是采集系统设计中需要解决的主要问题。

高速数据采集卡是数据采集和处理的硬件前端，通过总线接口与PC机进行数据通信。

传统的PCI总线不能满足高带宽传输，需要寻求一种新的总线协议，因此出现了PCI Express总线，即PCI-e总线。

PCI-e总线是取代PCI总线的新一代总线技术，采用了点对点串行连接，为每个设备分配独享的通道带宽，充分保证了每个设备的带宽资源，仅X1通道的单向传输速度可达2.5 Gbit/s，并有很大的拓展空间，能够满足海量数据传输的要求［2-3］。

xilinx命名规则Xilinx命名规则：了解Xilinx器件型号命名规则Xilinx是一家全球领先的可编程逻辑器件制造商，其产品广泛应用于通信、计算机、工业控制、医疗、汽车等领域。

Xilinx的产品型号命名规则是非常重要的，因为它能够帮助用户快速了解产品的性能和特点。

本文将介绍Xilinx器件型号命名规则，帮助读者更好地了解Xilinx产品。

Xilinx器件型号命名规则主要由以下几部分组成：1.器件系列：Xilinx的器件系列通常以字母开头，如Virtex、Kintex、Artix等。

不同的系列代表着不同的性能和应用领域。

例如，Virtex 系列是Xilinx最高端的FPGA产品系列，适用于高性能计算、高速通信和图像处理等领域；而Artix系列则是Xilinx的低成本FPGA产品系列，适用于工业控制、医疗和汽车等领域。

2.器件类型：Xilinx的器件类型通常以数字开头，如7、6、5等。

不同的数字代表着不同的器件类型。

例如，7系列是Xilinx的最新一代FPGA产品系列，采用了先进的28nm工艺，具有更高的性能和更低的功耗。

3.器件容量：Xilinx的器件容量通常以数字结尾，如50、100、200等。

不同的数字代表着不同的器件容量。

例如，Virtex-7系列的器件容量从70到2000不等，用户可以根据自己的需求选择不同的容量。

4.器件速度等级：Xilinx的器件速度等级通常以字母结尾，如-1、-2、-3等。

不同的字母代表着不同的器件速度等级。

例如，Virtex-7系列的速度等级从-1到-3不等，速度等级越高，器件的工作频率越高。

Xilinx器件型号命名规则非常简单明了，用户只需要了解器件系列、类型、容量和速度等级即可快速了解产品的性能和特点。

当然，Xilinx的产品还有很多其他的特点，如DSP、RAM、IO等，用户可以根据自己的需求选择不同的产品。

FPGA是ASIC设计者的一道普通难题？作者：Michael Santarini 作者：Michael Santarini摘要：随着开发 ASIC 与 SOC 的掩膜费用、复杂度和工具成本的上升，今天很多设计小组正在选用 FPGA 实现自己的产品设计。

但是，在设计者跨出这一步之前，应从好、坏两个方面着手考虑多种因素。

关键词：ASIC，FPGA随着开发 ASIC 与 SOC 的掩膜费用、复杂度和工具成本的上升，今天很多设计小组正在选用 FPGA 实现自己的产品设计。

但是，在设计者跨出这一步之前，应从好、坏两个方面着手考虑多种因素。

要点：* 设计者应听从 80% 的规则：如果你希望达到高性能目标，就要再以20%购买一种带有LUT（查找表）的 FPGA。

* 最大的 FPGA 可以运行在 550 MHz。

* 最大的 FPGA 有 33 万个逻辑单元，或大约等效于 1200 万个 ASIC 门。

* FPGA 供应商的综合工具效率不及商业 EDA 公司的 FPGA 综合工具。

* 当选择一种 FPGA 时，注意观察布局与硬接线宏结构；这些会带来能影响时序的布局挑战。

过去 10 年来，FPGA 供应商在克服 FPGA 缺点方面取得了很大的进步，并从 ASIC 市场赢得了份额。

在 90 年代末，FPGA 供应商增加了器件的容量，以抗衡中等规模 ASIC。

然后在大约 2001 年，FPGA 供应商改进了器件的性能，与中等规模的 ASIC 竞争。

尽管FPGA 的功耗仍然远远高于密度与性能相当的ASIC，但去年，FPGA 供应商迈出了一大步，稳定了 FPGA 的功耗（参考文献1）。

在实现器件属性的同时，FPGA 价格也在下降。

Actel、Altera、Lattice、Quicklogic 和 Xilinx 都提供范围广泛的器件，从每只几分钱的 CPLD（复杂可编程逻辑器件）到加密的非易失性 FPGA，还有高性能、高 LUT（查寻表）数、基于 SRAM 的 FPGA，它每片价格高达数千美元。

中国军用FPGA领先品牌----成都华微电子科技有限公司FPGA及存储类产品目录（2016版）公司简介成都华微电子科技有限公司（Chengdu Sino Microelectronics Technology Co.Lt d.）中文简称“成都华微”，英文简称“CSMT”，是国家“909”工程集成电路设计公司和国家首批认证的集成电路设计企业，隶属于中国电子信息产业集团下属振华集团。

于2000年3月注册成立，注册资金19250万，由中国振华电子集团有限公司、成都电子科大资产经营有限公司、成都创新风险投资有限公司、成都华微员工团队四家股东共同投资创办。

公司位于四川省成都市高新区益州大道中段1800号天府软件园G1号楼。

成都华微主要产品方向为可编程逻辑器件、高端模拟器件、接口和驱动电路以及存储器，同时为客户提供多重构片上系统（MPSOC）及可编程片上系统（SOPC）定制服务。

其中，在可编程逻辑器件、高速高精度ADC/DAC等领域居于国内领先地位，有显著的比较优势。

其中代表性的千万门级HWD4V系列FPGA、600万门级HWD2V系列FPGA、HWD1400系列CPLD、双路输出HWD703系列LDO、HWD7734/HWD7710/HWD7891/HWD976型多款高精度AD、HWD900高速比较器、16位双向数据传输器HWD164245等产品被航天、航空、中电、船舶、兵器等众多单位大批量应用，形成了长期稳定的供货。

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© 2004-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. Allother trademarks are the property of their respective owners.IntroductionThe LogiCORE™IP 1-Gigabit Ethernet Media Access Controller (GEMAC) core supports full-duplex opera-tion at 1 Gigabit per second (Gbps), and can be used with all Gigabit Ethernet Physical Coding standards.Features•Designed to IEEE 802.3-2002 specification •Single-speed 1-Gbps Ethernet Media Access Controller (MAC)•Full-duplex operation•Internal GMII physical-side interface (PHY) that can be connected to -An embedded PHY core, such as the Xilinx Ethernet 1000BASE-X PCS/PMA or SGMII core or other custom logic -IOBs to provide an external GMII-A shim that includes DDRs and DCMs to provide an external RGMII•Configured and monitored through an optional independent microprocessor-neutral interface •Interfaces directly to the Xilinx Ethernet Statistics core for powerful statistics gathering •Configurable flow control through MAC control pause frames; symmetrically or asymmetrically enabled •Optional MDIO interface to managed objects in PHY layers (MII Management)•Optional Address Filter with a selectable number of Address Table entries •Support of VLAN frames to specification IEEE 802.3-2002•Configurable support for jumbo frames of any length •Configurable in-band FCS field passing on both transmit and receive paths •Available under the terms of the SignOnce IP License1-Gigabit Ethernet MAC v8.4DS200 March 24, 2008Product SpecificationLogiCORE IP FactsCore SpecificsSupported FPGA FamilyVirtex™-5,Virtex-4,Virtex-II Pro,Virtex-II,Spartan™-3,Spartan-3E,Spartan-3A/3AN/3A DSP 1Speed Grade• -1 for Virtex-5•-4 for Virtex-II, Spartan-3,Spartan-3E,Spartan-3A/3AN/3A DSP• -5 for Virtex-II Pro • -10 for Virtex-4Performance1 GbpsCore ResourcesSlices 372-6082 or 585-10233LUTs 623-9552 or 763-12493FFs 651-10232 or 646-10653DCM 0-23BUFG2-73Core HighlightsDesigned to IEEE 802.3Simulation Only EvaluationHardware VerifiedHardware Evaluation Provided with CoreDocumentation Product Specification Getting Started GuideUser GuideDesign File Formats NGC Netlist,HDL Example Design,Demonstration Test Bench,ScriptsConstraints File User Constraints File (.ucf)Demo Example Designs1-Gigabit Ethernet MAC with GMII 1-Gigabit Ethernet MAC with RGMIIDesign Tool RequirementsSupported HDL VHDL and/or VerilogSynthesis XST 10.1Xilinx T ools ISE™10.1Simulation T oolsModelSim®v6.3c Cadence® IUS v6.1Synopsys® vcs_mxY-2006.06-SP141.See Table 19 for supported family configurations.2.Virtex-5 FPGA slices and LUTs are different from previous families.See Tables 20 and 21.3.See Tables 20 and 21; the precise number depends on user configu-ration.4.Scripts provided for listed simulators only.ApplicationsTypical applications for the GEMAC core include:•Ethernet 1000BASE-X Port•Ethernet 1000BASE-T PortEthernet 1000BASE-X PortFigure1 illustrates a typical GEMAC application. The PHY side of the core is connected to internallyintegrated 1000BASE-X logic using the Virtex-II Pro RocketIO™ Multi-Gigabit Transceiver (MGT) toconnect to an external off-the-shelf GBIC or SFP optical transceiver. The 1000BASE-X logic can be pro-vided by the Ethernet 1000BASE-X PCS/PMA or SGMII cores.The client side of the core is shown connected to the 10Mbps, 100 Mbps, 1 Gbps Ethernet FIFO, deliv-ered with the GEMAC core to complete a single Gigabit Ethernet port. This port is shown connected toa Switch or Routing matrix, which may contain several ports.Figure 1: Typical GEMAC 1000BASE-X Application DS200 March 24, 20081-Gigabit Ethernet MAC v8.4Ethernet 1000BASE-T PortFigure2 illustrates a typical application for the GEMAC core. The PHY side of the core is implementing an external GMII by connecting it to IOBs. The external GMII is connected to an off-the-shelf Ethernet PHY device, which performs the 1000BASE-T standard. Alternatively, the external GMII may be replaced with an RGMII using a small logic shim. HDL example designs are provided with the core to demonstrate external GMII or RGMII.The client side of the core is shown connected to the 10 Mbps, 100 Mbps, 1 Gbps Ethernet FIFO, deliv-ered with the GEMAC core, to complete a single Gigabit Ethernet port. This port is shown connected to a Switch or Routing matrix, which may contain several ports.Figure 2: Typical GEMAC 1000BASE-T ApplicationEthernet Architecture OverviewThe GEMAC sublayer provided by this core is part of the Ethernet architecture illustrated in Figure3.The part of this architecture from the MAC to the right is defined in IEEE 802.3 specification. Figure3also illustrates where supported interfaces fit into the architecture.Figure 3: Typical Ethernet ArchitectureMACThe Ethernet Media Access Controller (MAC) is defined in the IEEE 802.3 specification, in clauses 2, 3,and 4. A MAC is responsible for the Ethernet framing protocols and error detection of these frames. TheMAC is independent of, and can connect to, any type of physical layer device (PHY).GMIIThe Gigabit Media Independent Interface (GMII) is defined in IEEE 802.3, clause 35. This is a parallelinterface connecting a 1 Gigabit-capable MAC to the physical sublayers (PCS, PMA, and PMD).RGMIIThe Reduced Gigabit Media Independent Interface (RGMII) is an alternative to the GMII. RGMIIachieves a 50% reduction in the pin count compared with GMII, and is therefore favored over GMII byPCB designers. This is achieved with the use of double-data-rate (DDR) flip-flops.No change in the operation of the core is required to select GMII or RGMII. However, the clock man-agement logic and IOB logic around the core does change. HDL example designs are provided with thecore to implement either the GMII or RGMII protocols.SGMIIThe Serial-GMII (SGMII) is an alternative interface to the GMII that converts the parallel interface of theGMII into a serial format. This radically reduces the I/O count and is therefore often favored by PCBdesigners.The GEMAC core can be extended to include SGMII functionality by internally connecting its PHY-sideGMII to the Ethernet 1000BASE-X PCS/PMA or SGMII core. See the 1-Gigabit Ethernet MAC User Guidefor more information.PCS, PMA, and PMDThe combination of the Physical Coding sublayer (PCS), the Physical Medium Attachment (PMA), andthe Physical Medium Dependent (PMD) sublayer constitute the physical layers for the protocol. Twomain physical standards are specified for Gigabit Ethernet:•1000BASE-X (defined in IEEE 802.3, clauses 36 to 39), provides short and long wavelength laser and short haul copper interfaces•1000BASE-T, (defined in IEEE 802.3 clause 40), provides twisted-pair cabling systems DS200 March 24, 20081-Gigabit Ethernet MAC v8.4The 1000BASE-X architecture illustrated in Figure 1 can be provided by connecting the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core. See the 1-Gi gabi t Ethernet MAC User Gui de for details . The 1000BASE-T architecture illustrated in Figure 2 can be provided with the use of an external 1000BASE-T capable PHY device.Core OverviewFigure 4 shows the major functional blocks and interfaces of the GEMAC core. Descriptions of these functional block and interfaces, along with associated signals are provided in the sections that follow.Transmit EngineThe Transmit Engine accepts Ethernet frame data from the Client Transmitter Interface, adds the pre-amble field to the start of the frame, adds padding bytes if required (to ensure that the frame meets the minimum frame length requirements), and then adds the frame check sequence (when configured to do so). In addition, the transmitter is responsible for ensuring that the interframe spacing between suc-cessive frames always meets the minimum specified. The frame is then converted into a format com-patible with the GMII and sent to the GMII Block.Figure 4: GEMAC Functional Block DiagramDS200 March 24, 2008Client Transmitter Interface SignalsTable 1 defines the GEMAC core client-side transmitter signals. These signals are used to transmit data from the client logic into the GEMAC core. See the 1-Gigabit Ethernet MAC User Guide for more infor-mation.Client Transmitter Interface OperationFigure 5 illustrates the timing of a normal outbound frame transfer. When the client initiates a frame transmission, it places the first column of data onto the tx_data port and asserts a logic 1 onto tx_data_valid .After the GEMAC core reads the first byte of data, it asserts the tx_ack signal. On the next and subse-quent rising clock edges, the client must provide the remainder of the data for the frame. The end of frame is signaled to the GEMAC core by taking tx_data_valid to logic 0.T able 1: Transmitter Client Interface Signal PinsSignal DirectionClock DomainDescriptiongtx_clk Input n/aClock signal provided to the core at 125 MHz. T olerance must be within IEEE 802.3-2002specification. This clock signal is used by all of the transmitter logic.tx_data[7:0]Input gtx_clk Frame data to be transmitted is supplied on this port.tx_data_valid Input gtx_clk Control signal for tx_data port.tx_ifg_delay[7:0]Input gtx_clk Control signal for configurable Inter Frame Gap adjustment.tx_ack Output gtx_clk Handshaking signal asserted when the current data on tx_data has been accepted.tx_underrunInput gtx_clk Asserted by client to force MAC core to corrupt the current frame.tx_statistics_vector[21:0]Output gtx_clk Provides statistical information on the last frame transmitted.tx_statistics_validOutputgtx_clkAsserted at end of frame transmission, indicating that the tx_statistics_vector is valid.1-Gigabit Ethernet MAC v8.4Receive EngineThe Receive Engine accepts Ethernet frame data from the GMII Block, removes the preamble field at the start of the frame, and removes padding bytes and frame check sequence (if required and when configured to do so). In addition, the receiver is responsible for performing error detection on the received frame using information that includes the frame check sequence field, received GMII error codes, and legal frame size boundaries.Client Receiver Interface SignalsTable2 defines the GEMAC core client-side receiver signals. These signals are used by the GEMAC core to transfer data to the client. For a complete description, see the 1-Gigabit Ethernet MAC User Guide.Figure 5: Normal Frame Transmission Across Client InterfaceTable 2: Receive Client Interface Signal PinsSignal DirectionClockDomainDescriptionrx_data[7:0]Output gmii_rx_clk Frame data received is supplied on this port. rx_data_valid Output gmii_rx_clk Control signal for the rx_data port.rx_good_frame Output gmii_rx_clk Asserted at end of frame reception to indicate that the frame should be processed by the MAC client.rx_bad_frame Output gmii_rx_clk Asserted at end of frame reception to indicate that the frame should be discarded by the MAC client.rx_statistics_vector[26:0]Output gmii_rx_clk This provides statistical information on the last frame received.rx_statistics_valid Output gmii_rx_clk Asserted at end of frame reception, indicating thatthe rx_statistics_vector is valid.DS200 March 24, 2008Client Receiver Interface OperationFigure 6 illustrates the timing of a normal inbound frame transfer. The client must be prepared to accept data at any time; there is no buffering within the GEMAC to allow for latency in the receive cli-ent. After frame reception begins, data is transferred on consecutive clock cycles to the receive client until the frame is complete. The GEMAC asserts the rx_good_frame signal to indicate that the frame was successfully received and that the frame should be analyzed by the client.Flow ControlThe Flow Control block is designed to clause 31 of the IEEE 802.3-2002 standard. The GEMAC may be configured to send pause frames and to act upon their reception. These two behaviors can be config-ured asymmetrically. See the 1-Gigabit Ethernet MAC User Guide for more information . Flow Control Interface SignalsTable 3 defines the signals used by the client to request a flow-control action from the transmit engine.Transmitting a PAUSE Control FrameThe client initiates a Flow Control frame by asserting pause_req for a single clock period while the pause value is on the pause_val[15:0] bus. If the GEMAC core is configured to support transmit flow control, this action causes the core to transmit a PAUSE control frame on the link, with the PAUSE parameter set to the value on pause_val[15:0] in the cycle when pause_req was asserted. This does not disrupt any frame transmission in progress, but takes priority over any pending frame trans-mission. This frame will be transmitted even if the transmitter is in a paused state.Figure 6: Normal Frame ReceptionT able 3: Flow Control Interface Signal PinoutSignalDirectionClock DomainDescriptionpause_req Input gtx_clk Pause request Sends a pause frame down the link.pause_val[15:0]Inputgtx_clkPause value Inserted into the parameter field of the transmitted pause frame.1-Gigabit Ethernet MAC v8.4Receiving a Pause Control FrameWhen an error-free frame is received by the GEMAC core, it is evaluated in the following way:1.The destination address field is matched against the MAC Control multicast address or theconfigured source address for the MAC.2.The length/type field is matched against the MAC Control Type code.3.If number 2 is true, the opcode field contents are matched against the PAUSE opcode.If any of the previously listed conditions are false, or the MAC Flow Control logic for the receiver is dis-abled, the frame is ignored by the Flow Control logic and passed to the client with rx_good_frame asserted for interpretation.If the frame passes all of the previously listed conditions, is of minimum legal size, and the MAC Flow Control logic for the receiver is enabled, the pause value parameter in the frame is used to inhibit trans-mitter operation after successful completion of the current packet transmission for the time defined in the IEEE 802.3-2002 specification. Because the received pause frame has been acted on, it is passed to the client with rx_bad_frame asserted to indicate that it should be dropped.Reception of any frame for which condition number 2 is true and is not of legal minimum length is con-sidered an invalid control frame. This will be ignored by the Flow Control logic and passed to the client with rx_bad_frame asserted.Optional Address FilterThe GEMAC core can be implemented with an Address Filter. If the Address Filter is enabled, the device does not pass frames that do not contain one of a set of known addresses to the client.The Address Filter can be programmed to respond to up to five user-defined addresses when the Man-agement Interface is present in the core. These can be stored in a dedicated unicast address register and in a n-address deep table, where n is in the range 0 to 4. If the core is implemented with an Address Fil-ter but the Management Interface is omitted from the core, only the unicast address register can be accessed. Access to the unicast address register is through the input signal unicast_address[47:0] when the Management Interface is not present.In addition to the user-defined addresses, the broadcast and pause multicast addresses defined in the IEEE 802.3-2002 and the pause frame MAC source address are also recognized. For a detailed descrip-tion, see the 1-Gigabit Ethernet MAC User Guide.Optional Management InterfaceThe Management Interface is an optional processor-independent interface with standard address, data, and control signals. It can be used as is, or a wrapper can be applied (not supplied) to interface to com-mon bus architectures such as the CoreConnect bus interfacing to MicroBlaze or the Virtex-II Pro device embedded IBM PowerPC™. For a detailed description, see the 1-Gigabit Ethernet MAC User Guide. This interface is used for the following:•Configuration of the GEMAC core•Access through the MDIO interface to the Management Registers located in the PHY connected to the GEMAC coreDS200 March 24, 2008Client Management Interface SignalsTable 4 defines the optional signals used by the client to access the management features of the GEMAC core.Configuration RegistersAfter a power up or reset, the client can reconfigure the core parameters from the defaults. Configura-tion changes can be written at any time. Both the receiver and transmitter logic will only respond to configuration changes during interframe gaps. The exceptions are the configurable resets, which take effect immediately.Configuration of the GEMAC core is performed through a register bank that is accessed through the Management interface. Table 5 describes the available Configuration Registers. As described, the addresses have some implicit don’t care bits; any access to an address in these performs a 32-bit read or write from the same configuration word.T able 4: Optional Management Interface Signal PinoutSignalDirectionClock DomainDescriptionhost_clkInputn/aClock for the Management Interface; this must in the range of 10 MHz or abovehost_opcode[1:0]Input host_clk Defines operation to be performed over MDIO interface. Bit 1 is also used as a read/write control signal for configuration register access host_addr[9:0]Input host_clk Address of register to be accessed host_wr_data[31:0]Input host_clk Data to write to register host_rd_data[31:0]Output host_clk Data read from registerhost_miim_sel Input host_clk When asserted, the MDIO interface is accessed. When not asserted, the configuration registers are accessed host_req Input host_clk Used to signal a transaction on the MDIO interface host_miim_rdyOutputhost_clkWhen high, the MDIO interface has completed any pending transaction and is ready for a new transactionT able 5: Configuration RegistersAddressDescription0x200-0x23F Receiver Configuration (Word 0)0x240-0x27F Receiver Configuration (Word 1)0x280-0x2BF Transmitter Configuration 0x2C0-0x2FF Flow Control Configuration 0x300-0x33F Reserved0x340-0x37F Management Configuration0x380-0x383Unicast Address (Word 0) (if address filter is present)0x384-0x387Unicast Address (Word 1) (if address filter is present)Tables 6 and 7 define the register contents for the two receiver configuration words.Table 8 defines the register contents for the Transmitter Configuration Word.0x388-0x38B Address T able Configuration (Word 0) (if address filter is present)0x38C-0x38F Address T able Configuration (Word 1) (if address filter is present)0x390-0x393Address Filter Mode (if address filter is present)T able 6: Receiver Configuration Word 0BitDefault ValueDescription31-0All 0sPause frame MAC Source Address[31:0]T able 7: Receiver Configuration Word 1BitDefault ValueDescription15-0All 0s Pause frame MAC Source Address[47:32]23-16n/a Reserved240Control Frame Length Check Disable 250Length/Type Error Check Disable 26n/a Reserved 270VLAN Enable 281Receiver Enable 290In-band FCS Enable 300Jumbo Frame Enable 31Receiver ResetT able 8: Transmitter Configuration WordBitDefault ValueDescription24-0n/a Reserved250Interframe Gap Adjust Enable 26n/a Reserved 270VLAN Enable 281T ransmit Enable 290In-band FCS Enable 300Jumbo Frame Enable 31T ransmitter ResetT able 5: Configuration Registers (Continued)AddressDescriptionDS200 March 24, 2008Table 9 defines the register contents for the Flow Control Configuration Word.Table 10 defines the register contents for the Management Configuration Word.When the GEMAC core is implemented with an Address Filter, registers described in Tables 11 through 15 are used to access the Address Filter configuration. The register contents for the two unicast address registers are described in Tables 11 and 12.Tables 13 and 14 show how the contents of the Address Table are set.T able 9: Flow Control Configuration WordBitDefault ValueDescription28-0n/a Reserved291Receiver Flow Control Enable301T ransmitter Flow Control Enable 31n/aReservedT able 10: Management Configuration WordBitsDefault ValueDescription4-0All 0s Clock Divide[4:0]: This value enters a logical equation which enables the MDC frequency to be set as a divided down ratio of the HOST_CLK frequency.50MDIO Enable 31-6n/aReservedT able 11: Unicast Address (Word 0)BitsDefault ValueDescription31-0All 0sAddress filter unicast address[31:0]T able 12: Unicast Address (Word 1)BitsDefault ValueDescription15-0All 0s Address filter unicast address[47:32]31- 16N/AReservedT able 13: Address Table Configuration (Word 0)BitsDefault ValueDescription31-0All 0sMAC Address[31:0]The contents of the Address Filter mode register are described in Table 15. If Promiscuous mode is set to 1, the Address Filter does not check the addresses of receive frames.MDIO InterfaceThe Management Interface is also used to access the MDIO interface of the GEMAC core; this interface is typically connected to the MDIO port of a PHY to access its configuration and status registers. The MDIO format is defined in IEEE 802.3 clause 22.MDIO Interface SignalsTable 16 defines the MDIO interface signals.T able 14: Address Table Configuration (Word 1)BitsDefault ValueDescription15-0All 0s MAC Address[47:32]17-16All 0s The location in the address table that MAC address is to be read from or written to 22-18N/A Reserved 230Read not write 31-24N/AReservedT able 15: Address Filter ModeBitsDefault ValueDescription30-0N/A Reserved31Promiscuous ModeTable 16: MDIO Interface Signal Pinout SignalDirectionClock DomainDescriptionmdc Output host_clk Management Clock: derived from host_clk on the basis of the Clock Divide[4:0] value in the Management Configuration Word .mdio_in Input host_clk Input data signal for communication with PHY configuration and status. Tie high if unused.mdio_out Output host_clk Output data signal for communication with PHY configuration and status.mdio_triOutputhost_clkT ristate control for MDIO signals; 0 signals that the value on mdio_out should be asserted onto the MDIO bus.Note: mdio_in,mdio_out ,and mdio_tri can be connected to a Tri-state buffer to create a bi-directional mdio signal suitable for connection to an external PHY.DS200 March 24, 2008Configuration VectorIf the optional Management Interface is omitted from the GEMAC core, all relevant configuration set-tings described in Tables 6 through 9 and Table 15 are extracted as signals and bundled into the configuration_vector[67:0] signal. These signals can be permanently set by connecting to logic 0 or 1, or can be driven dynamically by control logic. See the 1-Gigabit Ethernet MAC User Guide .Reset OperationThe optional Management Interface provides independent configurable software driven resets for the receiver and transmitter paths (as defined in Tables 7 and 8.) When the Management interface is omit-ted, these resets are replaced as inputs of the configuration_vector[64:0] signal. In addition, a hardware reset port is provided to the core, described in Table 17.GMII BlockThis implements GMII-style signaling for the physical interface of the core and is typically attached to a PHY, either off-chip or internally integrated. The HDL example design delivered with the core when the GMII is selected connects these signals to IOBs to provide an external GMII. The HDL example design delivered with the core when the RGMII is selected connects these signals to a logic shim that uses double-data-rate (DDR) registers and DCMs to provide an external RGMII.GMII SignalsTable 18 defines the GMII-side interface signals of the core.T able 17: Reset Interface Signal PinoutSignalDirectionClock DomainDescriptionresetInputn/aAsynchronous reset for the entire core. Active High.T able 18: GMII Interface Signal PinoutSignalDirectionClock DomainDescriptiongmii_txd[7:0]Output gtx_clk GMII Transmit data from MAC gmii_tx_en Output gtx_clk GMII Transmit control signal from MAC gmii_tx_er Output gtx_clk GMII Transmit control signal from MACgmii_rx_clk Input n/a GMII Receive clock from an external PHY (125MHz) gmii_rxd[7:0]Input gmii_rx_clk GMII Received data to MAC gmii_rx_dv Input gmii_rx_clk GMII Received control signal to MAC gmii_rx_erInputgmii_rx_clkGMII Received control signal to MACVerificationThe GEMAC core has been verified with extensive simulation and hardware testing, as detailed in this section.SimulationA highly parameterizable transaction-based test bench was used to test the core. Tests include:•Register Access•MDIO Access•Frame Transmission and Error Handling•Frame Reception and Error Handling•Address FilteringHardware VerificationThe GEMAC core has been tested in a variety of hardware test platforms at Xilinx to address specific parameterizations, including the following:•The core has been tested with the Ethernet 1000BASE-X PCS/PMA or SGMII core, which follows the architecture illustrated in Figure1. A test platform was built around these cores, including a back-end FIFO capable of performing a simple ping function and a test pattern generator. Software running on the embedded PowerPC was used to provide access to all configuration, status, and statistical counter registers. Version 3.0 of this core was taken to the University of New Hampshire Interoperability Lab (UNH IOL) where conformance and interoperability testing was performed.•The core has been tested with an external 1000BASE-T PHY device, which follows the architecture illustrated in Figure2. The GEMAC core was connected to the external PHY device using GMII, RGMII and SGMII (in conjunction with the Ethernet 1000BASE-X PCS/PMA or SGMII core). Family SupportT able 19: Family Support for the 1-Gigabit Ethernet MAC CoreDevice FamilyPHY Interface ManagementInterfaceAddress Filter with GMII with RGMIIVirtex-5Supported Supported Supported Supported Virtex-4Supported Supported Supported Supported Virtex-II Pro Supported Supported Supported Supported Virtex-II Supported Supported Supported Supported Spartan-3Supported Supported Supported Supported Spartan-3E Supported Not Supported Supported Supported Spartan-3A/3AN/3ADSPSupported Supported Supported SupportedDS200 March 24, 2008The Virtex-5 device family contains six input LUTs; all other families contain four input LUTs. For this reason, the device utilization for Virtex-5 devices is listed separately. Please refer to either of the follow-ing:•Virtex-5 Devices •Other Device FamiliesVirtex-5 DevicesTable 20 provides approximate utilization figures for various core options when a single instance of the core is instantiated in a Virtex-5 device.Utilization figures are obtained by implementing the block level wrapper for the core. This wrapper is part of the example design and connects the core to the selected physical interface. BUFG usage:•does not consider multiple instantiations of the core, where clock resources can often be shared •does not include the reference clock required for IDELAYCTRL. This clock source can be shared across the entire device and is not core specific Table 20: Device Utilization for Virtex-5 Device FamiliesParameter ValuesDevice ResourcesPhysical InterfaceManagement InterfaceAddress FilterAddr Table EntriesSlice sLUT sFFs18K Block RAMsBUFGsDCMsGMII Y es Y es 4608953102303011.No core-specific DCMs are required if a reference clock for the IDELAYCTRL component is available on-chip.GMII Y es Y es 05618559670301GMII Y es No N/A 4777328330301GMII No Y es N/A 3926727130201GMII No No N/A 3806236610201RGMII Y es Y es 459895*********RGMII Y es Y es 05368589570301RGMII Y es No N/A 4987358230301RGMII No Y es N/A 4016767030201RGMIINoNoN/A372626651201。

Serial Configuration InterfaceNotes relevant to Figure 2-4:1.The DONE pin is by default an open-drain output requiring an external pull-upresistor. For all devices except the first, the active driver on DONE must be disabled.For the first device in the chain, the active driver on DONE can be enabled. See “Guidelines and Design Considerations for Serial Daisy Chains.”2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.3.The BitGen startup clock setting must be set for CCLK for serial configuration.4.The PROM in this diagram represents one or more Xilinx PROMs. Multiple Xilinx PROMs can be cascaded to increase the overall configuration storage capacity.5.The BIT file must be reformatted into a PROM file before it can be stored on the Xilinx PROM. Refer to the “Generating PROM Files” section.6.On some Xilinx PROMs, the reset polarity is programmable. RESET should be configured as active Low when using this setup.7.The CCLK net requires Thevenin parallel termination. See “Board Layout for Configuration Clock (CCLK),” page 73.8.Serial daisy chains are specific to the Platform Flash XCFS and XCFP PROM only.The first device in a serial daisy chain is the last to be configured. CRC checks only include the data for the current device, not for any others in the chain. (See “Cyclic Redundancy Check (Step 7)” in Chapter 1.)After the last device in the chain finishes configuration and passes its CRC check, it enters the Startup sequence. At the Release DONE pin phase in the Startup sequence, the device places its DONE pin in a High-Z state while the next to the last device in the chain isconfigured. After all devices release their DONE pins, the common DONE signal is either pulled High externally or driven High by the first device in the chain. On the next rising CCLK edge, all devices move out of the Release DONE pin phase and complete their startup sequences.It is important that all DONE pins in a Slave serial daisy chain be connected. Only the first device in the serial daisy chain should have the DONE active pull-up driver enabled. Enabling the DONE driver on downstream devices causes contention on the DONE signal.Figure 2-4:Master/Slave Serial Mode Daisy Chain Configuration09PlChapter 2:Configuration InterfacesMixed Serial Daisy ChainsVirtex-5 devices can be daisy-chained with the Virtex, Spartan™-II, Virtex-E, Spartan-IIE,Virtex-II, Virtex-II Pro, Spartan-3, and Virtex-4 families. There are three important designconsiderations when designing a mixed serial daisy chain:∙Many older FPGA devices cannot accept as fast a CCLK frequency as a Virtex-5 devicecan generate. Select a configuration CCLK speed supported by all devices in thechain.∙Virtex-5 devices should always be at the beginning of the serial daisy chain, witholder family devices located at the end of the chain.∙All Virtex device families have similar BitGen options. The guidelines provided forVirtex-5 BitGen options should be applied to all Virtex devices in a serial daisy chain.∙The number of configuration bits that a device can pass through its DOUT pin islimited. This limit varies for different families (Table2-3). The sum of the bitstreamlengths for all downstream devices must not exceed the number in Table2-3 for eachfamily.Table 2-3:Maximum Number of Configuration Bits, Various Device FamiliesArchitecture Maximum DOUT BitsVirtex-5, Virtex-4, Virtex-II Pro, and Virtex-II Devices32 x (227 – 1) = 4,294,967,264Spartan-3 Devices32 x (227 – 1) = 4,294,967,264Virtex, Virtex-E, Spartan-II, and Spartan-IIE Devices32 x (220 – 1) = 33,554,216 Guidelines and Design Considerations for Serial Daisy ChainsThere are a number of important considerations for serial daisy chains:Startup Sequencing (GTS)GTS should be released before DONE or during the same cycle as DONE to ensure theVirtex-5 device is operational when all DONE pins have been released.Active DONE DriverAll devices except the first should disable the driver on the DONE pin (refer to the BitGensection of the Development System Reference Guide for software settings). The first device ina chain is programmed last:∙DriveDone is disabled (all devices except the first)∙DriveDone is enabled (first device)Alternatively, the driver can be disabled for all DONE pins and an external pull-up resistorcan be added to pull the signal High after all devices have released it.Connect All DONE PinsIt is important to connect the DONE pins for all devices in a serial daisy chain. Failing toconnect the DONE pins can cause configuration to fail. For debugging purposes, it is oftenhelpful to have a way of disconnecting individual DONE pins from the common DONEsignal, so that devices can be individually configured through the serial or JTAG interface.Serial Configuration InterfaceDONE Pin Rise TimeAfter all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in oneCCLK cycle. External pull-up resistors are required. If additional time is required for theDONE signal to rise, the BitGen donepipe option can be set for all devices in the serialdaisy chain. (Refer to the BitGen section of the Development System Reference Guide forsoftware settings.)Ganged Serial ConfigurationMore than one device can be configured simultaneously from the same bitstream using aganged serial configuration setup (Figure2-5). In this arrangement, the serial configurationpins are tied together such that each device sees the same signal transitions. One device istypically set for Master serial mode (to drive CCLK) while the others are set for Slave serialmode. For ganged serial configuration, all devices must be identical. Configuration can bedriven from a configuration PROM or from an external configuration controller.u g191_c2_31_090808Figure 2-5:Ganged Serial ConfigurationNotes relevant to Figure2-5:1.For ganged serial configuration, the optional DONE driver must be disabled for alldevices if one device is set for Master mode because each device might not start up onexactly the same CCLK cycle. An external pull-up resistor is required in this case.2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrequired.3.The BitGen startup clock setting must be set for CCLK for serial configuration.Board Layout for Configuration Clock (CCLK)Chapter 2:Configuration Interfaces。