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5,0 mm x 6,4 mmR OUT1R OUT2D IN2D IN1EN END OUT1+D OUT1−D OUT2−D OUT2+R IN2−R IN2+R IN1−R IN1+R R R R D D D D SN65LVDS049SLLS575–AUGUST 2003DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERSThe intended application of this device and signaling FEATUREStechnique is for point-to-point baseband data trans-•DS90LV049Compatiblemission over controlled impedance media of approxi-•Up to 400Mbps Signaling Rates mately 100-Ωcharacteristic impedance.The trans-mission media may be printed-circuit board traces,•Flow-Through Pin-outbackplanes,or cables.(Note:The ultimate rate and •50ps Driver Channel-to-Channel Skew (Typ)distance of data transfer is dependent upon the attenu-•50ps Receiver Channel-to-Channel Skew ation characteristics of the media,the noise coupling to the environment,and other application specific charac-(Typ)teristics)• 3.3-V Power SupplyThe SN65LVDS049is characterized for operation from •High-Impedance Disable for all Outputs –40°C to 85°C•Internal Failsafe Biasing of Receiver Inputs • 1.4ns Driver Propagation Delay (Typ)• 1.9ns Receiver Propagation Delay (Typ)FUNCTIONAL DIAGRAM•High Impedance Bus Pins on Power Down •ANSI TIA/EIA-644-A Compliant•Receiver Input and Driver Output ESD Ex-ceeds 10kV•16-pin TSSOP PackageAPPLICATIONS•Full-duplex LVDS Communications of Clock and Data •PrintersDESCRIPTIONThe SN65LVDS049is a dual flow-through differential line driver-receiver pair that uses low-voltage differen-tial signaling (LVDS)to achieve signaling rates as high as 400Mbps.The TIA/EIA-644-A standard compliant electrical interface provides a minimum differential out-PW PACKAGE (Marked as LVDS049)(TOP VIEW)put voltage magnitude of 250mV into a 100-Ωload and receipt of signals with up to 1V of ground potential difference between a transmitter and receiver.The LVDS receivers have internal failsafe biasing that places the outputs into a known high state for uncon-nected differential inputs.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright ©2003,Texas Instruments IncorporatedProducts conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily in-cludetestingofallparameters.SN65LVDS049SLLS575–AUGUST 2003DRIVER TRUTH TABLEINPUT ENABLESOUTPUTS (1)DIN EN EN D OUT+D OUT-L HL or OPENL H H H L XAll other conditions ZZ(1)H =high level,L =low level,X =irrelevant,Z =high impedance (off)RECEIVER TRUTH TABLEDIFFERENTIAL INPUTENABLESOUTPUT (1)R IN--R IN+EN EN R OUT V ID ≥100mV HL or OPENH V ID ≤-100mV L Open/short or terminatedH XAll other conditions Z(1)H =high level,L =low level,X =irrelevant,Z =high impedance (off)ENABLE FUNCTION TABLEENABLESOUTPUTSEN EN LVDS Out LVCMOS Out L or OpenL or Open DISABLED DISABLED H L or OpenENABLED ENABLED L or OpenH DISABLED DISABLED HHDISABLEDDISABLEDPOWER DISSIPATION RATINGCIRCUIT BOARDT A ≤25°C DERATING FACTOR (1)T A =85°C PACKAGEMODELPOWER RATINGABOVE T A =25°CPOWER RATINGPWLow-K (2)774mW6.2mW/°C402mW(1)This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.(2)In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.2SN65LVDS049SLLS575–AUGUST 2003ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted)(1)UNITSupply voltage range (2),V CC-0.3V to 4V D IN ,R OUT ,EN,or EN-0.3V to (V CC +0.3V)Voltage rangeR IN+or R IN--0.3V to 4V D OUT+or D OUT--0.3V to 3.9VR IN+,R IN-,D OUT+,and D OUT-±10kV Human Body Model (3)ESDAll pins ±2K V Charged-Device Model (4)All pins±500V LVDS output short circuit duration (DOUT+,DOUT-)ContinuousContinuous power dissipation See Dissipation Rating TableStorage temperature range-65°C to 150°CLead temperature 1,6mm (1/16inch)from case for 10seconds 260°C(1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability (2)All voltage values,except differential I/O bus voltages,are with respect to network ground terminal.(3)Tested in accordance with JEDEC Standard 22,Test Method A114-A.(4)Tested in accordance with JEDEC Standard 22,Test Method C101.RECOMMENDED OPERATING CONDITIONS3SN65LVDS049SLLS575–AUGUST 2003DEVICE ELECTRICAL CHARACTERISTICSover recommended operating conditions (unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP (1)MAXUNITINPUT DC SPECIFICATIONS (D IN ,EN,EN)V IH Input high voltage 2.0V CC V V IL Input low voltage GND 0.8V I IH Input high current V IN =V CC -10310µA I IL Input low current V IN =GND -10110µA V CL Input clamp voltage I CL =-18mA-1.5-0.8V LVDS Output DC Specifications (D OUT+,D OUT-)|V OD |Differential output voltage 250350450V Change in magnitude of V OD for ∆|V OD |-35135mV complimentary output states R L =100Ω,See Figure 1V OS Offset voltage1.125 1.2 1.375V Change in magnitude of V OS for ∆V OS -25125mV complimentary output states EnabledI OS Output short circuit currentD IN =V CC and D OUT+=0V,or -4.5-9mA D IN =GND and D OUT-=0V I OSD Differential output short circuit current (2)Enabled,V OD =0V -3.6-9mA I OFF Power-off leakageV CC =0V or Open;-20020µA VO =0or 3.6V I OZOutput high-impedance currentEN =0V and EN =V CC ,-1010µAV O =0or V CCLVDS Input DC Specifications (R IN+,R IN-)V IT+Differential input high threshold 100mV V CM =1.2V,0.05V,2.35V V IT-Differential input low threshold -100mV V CMR Common-mode voltage range V ID =±100mV0.05 2.35V V CC =3.6V,V IN =0V or 2.8V -2020µA I INInput currentV CC =0V,V IN =0V,2.8V,or 3.6V -2020µA Outputs DC Specifications (R OUT )V OH Output high voltage I OH =-0.4mA,V ID =200mV 2.73.3V V OL Output Low voltageI OL =2mA,V ID =-200mV 0.050.25V I OZ Output high-impedance current Disabled,V OUT =0V or V CC-10010µA Device DC SpecificationsI CC Power supply current EN =3.3V,D IN =V CC or Gnd,100-Ω1735mA (LVDS loaded,enabled)differential LVDS loads I CCZ High impedance supply current (disabled)No loads,EN =0V125mA(1)All typical values are at 25°C and with a 3.3V supply.(2)Output short circuit current (IOS)is specified as magnitude only,the minus sign indicates direction only4 SN65LVDS049 SLLS575–AUGUST2003SWITCHING CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP(1)MAX UNIT LVDS Outputs(D OUT+,D OUT-)t PLHD Differential propagation delay low to high R L=100Ω, 1.3 2.0nsC L=15pF distributed,t PHLD Differential propagation delay high to low 1.4 2.0nsSee Figure2t sk(p)Differential pulse skew(|t PHL-t PLH|)00.150.4ns t sk(o)Differential channel-to-channel skew(2)00.050.5ns t sk(pp)Differential part-to-part skew(3)01ns t r Differential rise time0.20.51ns t f Differential fall time0.20.51ns t PHZ Disable time,high level to high impedance R L=100Ω, 2.74nsC L=15pF distributed,t PLZ Disable time,low level to high impedance 2.74nsSee Figure3t PZH Enable time,high impedance to high level158ns t PZL Enable time,high impedance to low level158ns f MAX Maximum operating frequency(4)250MHz LVCMOS Outputs(R OUT)t PLH Propagation delay low to high V ID=200mV,0.5 1.9 3.5nsC L=15pF distributed,t PHL Propagation delay high to low0.5 1.7 3.5nsSee Figure4t sk(p)Pulse skew(|t PHL-t PLH|)00.20.4ns t sk(o)Channel-to-channel skew(5)00.050.5ns t sk(pp)Part-to-part skew(6)01ns t r Rise time0.30.5 1.4ns t f Fall time0.30.5 1.4ns t PHZ Disable time,high level to high impedance C L=15pF distributed,37.29nsSee Figure5t PLZ Disable time,low level to high impedance 2.548ns t PZH Enable time,high impedance to high level 2.5 4.27ns t PZL Enable time,high impedance to low level2 3.37nsf MAX Maximum operating frequency(7)200250MHz(1)All typical values are at25°C and with a3.3V supply.(2)tsk(o)is the magnitude of the time difference between the t PLH or t PHL of all drivers of a single device with all of their inputs connectedtogether.(3)tsk(pp)is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages,at the same temperature,and have identical packages and test circuits.(4)f(MAX)generator input conditions:t r=t f<1ns(0%to100%),50%duty cycle,0V to3V.Output Criteria:duty cycle=45%to55%,V OD>250mV,all channels switching.(5)tsk(lim)is the maximum delay time difference between drivers over temperature,V CC,and process.(6)tsk(pp)is the magnitude of the difference in propagation delay times between any specified terminals of two devices when bothdevices operate wf(MAX)generaith the same supply voltages,at the same temperature,and have identical packages and test circuits(7)f(MAX)generator input conditions:t r=t f<1ns(0%to100%),50%duty cycle,V ID=200mV,V CM=1.2V.Output criteria:duty cycle=45%to55%,V OH>2.7V,V OL<0.25V,all channels switching.5V CC GNDODSN65LVDS049SLLS575–AUGUST 2003EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMSPARAMETER MEASUREMENT INFORMATIONFigure 1.Driver V OD and V OS Test Circuit6Oscilloscope3 V 0 VV OH V OLD D OUT-D VV OHV OL0 V 3 V0 V 3 V1.2 V1.2 V t t EN When EN = GND or OpenD OUT+ When D IN = GND D OUT- When D IN = V CCEN When EN = V CCD OUT- When D IN = GND D OUT+ When D IN = V CC SN65LVDS049SLLS575–AUGUST 2003Figure 2.Driver Propagation Delay and Rise/Fall Time Test Circuit and WaveformsFigure 3.Driver High-Impedance State Delay Test Circuit and Waveforms71.3 V1.1 VV OHV OLR IN-R IN+R OUTV OHV OL0 V3 VV CC /2V CC /20 V 3 Vt t EN When EN = GND or OPENEN When EN = V CCR OUT for R IN+ = 1.4 Vand R IN- = 1 VR OUT for R IN+ = 1 V and R IN- = 1.4 VSN65LVDS049SLLS575–AUGUST 2003Figure 4.Receiver Propagation Delay and Rise/Fall Test Circuit and WaveformsFigure 5.Receiver High-Impedance State Delay Test Circuit and Waveforms(Note,V CC =3.3V)8100200300400500600406080100120140160|V O D - D i f f e r e n t i a l O u t p u t V o l t a g e - m V|R L - Load Resistance - Ω01020304050600.11101001000I C C - S u p p l y C u r r e n t - m Af - Frequency - MHzSN65LVDS049SLLS575–AUGUST 2003TYPICAL CHARACTERISTICSPower Supply CurrentV vs.Load Resistancevs.FrequencyFigure 6.Figure 7.9PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)SN65LVDS049PW ACTIVE TSSOP PW 1690Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN65LVDS049PWG4ACTIVE TSSOP PW 1690Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN65LVDS049PWR ACTIVE TSSOP PW 162000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN65LVDS049PWRG4ACTIVETSSOPPW162000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledgeand belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM4-Nov-2005Addendum-Page 1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. 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辛迪莱SN65LVDS4评估模块的用户指南说明书

辛迪莱SN65LVDS4评估模块的用户指南说明书

User's GuideSLLU151–July2011SN65LVDS4Evaluation Module The Texas Instruments SN65LVDS4Evaluation Module board is used to evaluate the SN65LVDS4LVDS receiver with selectable output levels.Contents1Introduction (2)2SN65LVDS4EVM Kit Contents (2)3SN65LVDS4EVM Board Configuration (2)4Power Supply Configuration (3)5Test Setup (3)6Schematic,Bill of Materials,and Board Layouts (4)6.1Schematic (4)6.2Bill of Materials (5)6.3Board Layouts (6)List of Figures1SN65LVDS4EVM Board (2)2SN65LVDS4Schematic (4)3SN65LVDS4EVM Board Layout,Top–Layer1 (6)4SN65LVDS4EVM Board Layout,GND–Layer2 (7)5SN65LVDS4EVM Board Layout,POWER–Layer3 (8)6SN65LVDS4EVM Board Layout,Bottom–Layer4 (9)List of Tables1Power Supply Acceptable Combinations (3)2EVM and Device Connections (3)3SN65LVDS4EVM Bill of Materials (5)4SN65LVDS4EVM Printed-Circuit Board Layer Construction (6)1 SLLU151–July2011SN65LVDS4Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedIntroduction 1IntroductionThe Texas Instruments SN65LVDS4Evaluation Module(EVM)board is used to evaluate the SN65LVDS4 LVDS receiver.The device can provide output voltage logic levels based on an external VDD pin,thus eliminating the need for external level translation.The board enables the system designer to connect50-Ωcoaxial cables via SMA connectors at the inputs and an SMA or high-impedance probe at the output.2SN65LVDS4EVM Kit ContentsThe SN65LVDS4EVM kit contains the following:•SN65LVDS4EVM board•SN65LVDS4EVM User’s Guide(this document)3SN65LVDS4EVM Board ConfigurationThe SN65LVDS4input differential pair(J1,J3)and single-ended output(J2)are available through theedge launch SMA connectors.Figure1.SN65LVDS4EVM Board2SN65LVDS4Evaluation Module SLLU151–July2011Submit Documentation FeedbackCopyright©2011,Texas Instruments Incorporated Power Supply Configuration 4Power Supply ConfigurationTwo power supplies are needed to bias the SN65LVDS4–VCC,the core power supply,and VDD,the output drive power supply.For proper device operation,it is recommended that VCC is powered up first and then VDD or VCC applied at the same time as VDD(In the later case,VCC and VDD are tiedtogether).Further,it is also recommended that VCC is equal to or less than VDD as shown in Table1.Table1.Power Supply Acceptable CombinationsVCC(V)VDD(V)Recommended1.8 1.8Yes1.82.5Yes1.8 3.3Yes2.5 1.8No2.5 2.5Yes2.53.3Yes5Test SetupMeasuring the output signal on J2with a50-Ωcable terminated into50Ωat the scope attenuates thesignal due to the453-Ωresistor(R1)in series with the receiver output on the EVM board.The resistor is installed as a current limit for termination into a50-Ωload,thus providing a10x attenuation on themeasured output signal.Measuring the output signal with a high-impedance probe on JMP1requires removing R1,the453-Ωresistor,and installing a0-Ωresistor on R4(0402).Measuring the output signal on JMP1allows the user to see absolute signal levels out of the device.See Table2for input and output connections.Table2.EVM and Device ConnectionsPinEVM Connection I/O DescriptionName No.J1A2I LVDS input,positiveJ3B3I LVDS input,negativeP2GND1,7—Ground—NC4,6,9—No connectJ2R8O 1.8/2.5LVCMOS/3.3LVTTL outputP1VCC5—Core supply voltageP3VDD10—Output supply voltage3 SLLU151–July2011SN65LVDS4Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments Incorporated6Schematic,Bill of Materials,and Board Layouts6.1SchematicFigure2.SN65LVDS4Schematic4SN65LVDS4Evaluation Module SLLU151–July2011Submit Documentation FeedbackCopyright©2011,Texas Instruments Incorporated6.2Bill of MaterialsTable3.SN65LVDS4EVM Bill of MaterialsQty Reference Value Part Part Number Manufacturer2C1,C40.01µF CC0201GRM033R70J103KA01D Murata2C2,C50.1µF CC0201GRM033R60J104KE19D Murata1C310pF CC0402ECD-G0E100C Panasonic-ECG2C6,C1068µF CT7343TAJE686K025R AVX2C7,C1147µF CC1210EMK325BJ476MM-T Taiyo Yuden2C8,C1222µF CC1206C1206X5R6R3-226KNE Venkel2C9,C1310µF CT7343C1206X7R160-106KNE Venkel1JMP13Pin Berg Jumper HDR1X3HTSW-150-07-G-S Samtec3J1,J2,J3sma_edge JOHNSON_142-0701-801142-0701-801EF Johnson3P1,P2,P3Banana-Jack JOHNSON_108-0740-001108-0740-001Emerson Network Power 1R1453R0402RMCF0402FT453R Stackpole Electronics 1R2100R0201ERJ-1GEJ101C Panasonic-ECG1R30R0402RMCF0402ZT0R00Stackpole Electronics 1R4DNI_0R0402RMCF0402ZT0R00Stackpole Electronics 1U1SN65LVDS410-pin RSE SN65LVDS4Texas Instruments5 SLLU151–July2011SN65LVDS4Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments Incorporated6.3Board LayoutsTable4.SN65LVDS4EVM Printed-Circuit Board Layer Construction Subclass Thickness Conductivity Dielectric Loss Width Impedance Type Material ArtworkName(mil)(mho/cm)Constant Tangent(mil)(Ω)(1) SURFACE AIRMASK LPIFINISH ENIG 1.29TOP CONDUCTOR COPPER0.68959590010POSITIVE1050 DIELECTRIC FR-460 4.20.035L2_GND PLANE COPPER 1.37859590010POSITIVEDIELECTRIC FR-4100 4.20.035L3_POWER CONDUCTOR COPPER 1.37859590010POSITIVEDIELECTRIC FR-460 4.20.035BOTTOM CONDUCTOR COPPER0.68959590010POSITIVE N/AFINISH ENIG 1.29MASK LPISURFACE AIR(1)Always consult with your board manufacturer for their process/design requirements to ensure the desired impedance isachieved.Figure3.SN65LVDS4EVM Board Layout,Top–Layer16SN65LVDS4Evaluation Module SLLU151–July2011Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedFigure4.SN65LVDS4EVM Board Layout,GND–Layer27 SLLU151–July2011SN65LVDS4Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedFigure5.SN65LVDS4EVM Board Layout,POWER–Layer38SN65LVDS4Evaluation Module SLLU151–July2011Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedFigure6.SN65LVDS4EVM Board Layout,Bottom–Layer49 SLLU151–July2011SN65LVDS4Evaluation Module Submit Documentation FeedbackCopyright©2011,Texas Instruments IncorporatedEvaluation Board/Kit Important NoticeTexas Instruments(TI)provides the enclosed product(s)under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,DEMONSTRATION,OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use.Persons handling the product(s)must have electronics training and observe good engineering practice standards.As such,the goods being provided are not intended to be complete in terms of required design-,marketing-,and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards.This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility,restricted substances(RoHS),recycling(WEEE),FCC,CE or UL,and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide,the board/kit may be returned within30 days from the date of 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protection against radio frequency interference.Operation of this equipment in other environments may cause interference with radio communications,in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.EVM Warnings and RestrictionsIt is important to operate this EVM within the input voltage range of1.62V to2.75V and the output voltage range of1.62V to3.6 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM.If there are questions concerning the input range,please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output.If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation,some circuit components may have case temperatures greater than40°C.The EVM is designed to operate properly with certain components above40°C as long as the input and output ranges are maintained.These components include but are not limited to linear regulators,switching transistors,pass transistors,and current sense resistors.These types of devices can be identified using the EVM schematic located in the EVM User's Guide.When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2011,Texas Instruments IncorporatedIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant 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SN65HVD1781DR中文资料

SN65HVD1781DR中文资料

Open-circuit bus Short-circuit bus Idle (terminated) bus
RECEIVER FUNCTION TABLE
Enable RE L L L H
OPEN L L L
Output R H ? L Z Z H H H
Receiver State
Receive valid bus High Indeterminate bus state Receive valid bus Low Receiver disabled (1) Receiver disabled by default (1) Fail-safe high output Fail-safe high output Fail-safe high output
(1) When both the driver and receiver are disabled, the device enters a low-power standby mode.
Differential Input VID = VA – VB VIT+ < VID
VIT– < VID < VIT+ VID < VIT– X X
This device combines a differential driver and a differential receiver, which operate from a single power supply. The driver differential outputs and the receiver differential inputs are connected internally to form a bus port suitable for half-duplex (two-wire bus) communication. This port features a wide common-mode voltage range, making the devices suitable for multipoint applications over long cable runs. This device is characterized from –40°C to 125°C. The SN65HVD1781 is pin-compatible with the industry-standard SN75176 transceiver, making it a drop-in upgrade for most devices.
SN65LVDS84AQ中文资料

SN65LVDS84AQ中文资料


Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
D3 D2 GND D1 D0 NC LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D20
DGG PACKAGE (TOP VIEW)
D4 VCC D5 D6 GND D7 D8 VCC D9 D10 GND D11 D12 NC D13 D14 GND D15 D16 D17 VCC D18 D19 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
NC – Not Connected
description
The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
SN65MLVD080DGGR中文资料

SN65MLVD080DGGR中文资料


This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. In accordance with the Low-K thermal metric definitions of EIA/JESD51-3. In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2003–2005, Texas Instruments Incorporated
元器件交易网
SN65MLVD080 SN65MLVD082
SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005

LOGIC DIAGRAM (POSITIVE LOGIC)
SN65MLVD080, SN65MLVD082 Channel 1 1DE 1A 1D 1B
DESCRIPTION
The SN65MLVD080 and SN65MLVD082 provide eight half-duplex transceivers for transmitting and receiving Multipoint-Low-Voltage Differential Signals in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. The driver outputs have been designed to support multipoint buses presenting loads as low as 30-Ω and incorporates controlled transition times to allow for stubs off of the backbone transmission line.