A high-speed comparator design technique
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1
10 MHz
I,ud 100 MHz
1,,
IGHz
gain distribution was arranged for similar rolloff points in each stage, although the limiting factor is the interstage level shift, which introduces width. both an attenuation and a reduction in bandoutput stages Level shifting and the ECL-compatible
drive circuit
and gain peaking.
The input transistors QI and input emitter followers, while
Q2 operate at low collector
currents, about 0.5 mA, to ensure
a low input bias current without pacitance terms.
respect
to the input
0018 -9200/82/0600
-0529 $00.75
@ 1982 IEEE
Authorized licensed use limited to: Tsinghua University Library. Downloaded on October 28, 2008 at 22:51 from IEEE Xplore. Restrictions apply.
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u. 1/? IF Rsf. Analog
u
Analogue GND
Digital .GND
Further
work in this area is being supported by have conventionally used Schottky
interests in nucleonics and high-speed data conversion. High-speed comparators diode clamping [2] or similar techniques to avoid transistor
v,,
Fig. 2. Full
tion delay and the variation
comparator circuit. All transistors have minimum 3 X 8 ~m emitters except where stated.
size
drive by adopting large signal linear circuit some circumstances specifically
II. CIRCUIT
The Fig. 1. front The end circuit configuration
CONFIGURATION comparator from long-tailed is shown in cell
of the new is derived
a Gilbert-type
Manuscript received September 24, 1981. This work was performed under contract to British Telecom Research Limited, Martlesham, England. The author is with the Allen Clark Research Centre, Plessey Research (Caswell) Limited, Caswell, Towcester, Northhamptonshire, NN12 8EQ England.
530
IEEE JOURNAL 70 t
60 50 40 ~ 30 20 10 10MHz d 100MH2 Frequency
OF SOLID-STATE
CIRCUITS,
VOL. SC-17, NO. 3, JUNE 1982
lGHz
Fig. 3. SPICE prediction of gain versus frequency. 14Байду номын сангаас MHz, gain 40 dB at 400 MHz.
are an essential feature of many new
v..
T
T
circuit applications, inchrdmg optical fiber ~mks, nucleonics, and data converters. This paper will describe a design approach based on large signal linear circuitry which is capable of providing high gain ( >55 dB), low propagation delay (1.5 ns) comparators, either singly or for use in arrays. Outstanding features of the circuit are high gain at high fre. quency and the minimal variation of delay with overdrive conditions. A junction isolated bipolar process is used which has 3 ~m minimum feature size and 5 GHz transistor ~T’s.
L ‘Q
%6
A A=min. emitter size — Approximate gain distribution— x8.4 — xO.8 — x7.2 —x12,8 UXO.94 (Load dependent )
saturation. Improvements in performance were achieved by going to the transconductance amplifier followed by transresistance amplifier configuration [3] and this forms the basis of the fastest comparators that a further improvement currently available. It will be shown can be achieved in both propagaof propagation delay with overdesign techniques.
10 has been power, significant; However,
is not
[4] with
the addition
of a conventional
pair current
in the case of a single comparator the criterion in Fig. is absolute of the gain distribution very carefully
the cascode devices Q5 and Q6 reduce Miller effect input caThe cross-coupled pair Q3 and Q4 raise the small signal gain to 8.4, while maintaining a 3 dB rolloff frequency over 400 MHz, assisted by the peaking effect of the pole-zero cancellation resistors R3 and R4 [5]. The input configuration has some similarity process, of in and pole-zero achieved. and to some to that of [6], but by the use of an improvement without cost, this is speed. on in power-delay a faster factor primarily product. not An width usually cancellation, This extent applied 2.
The use of a latched stage, as in [3], could be an advantage in for a general-purpose comparator, but was for a excluded here by the system requirements
v,., — 03cb
I. INTRODUCTION
I All transistors minimum II size 3P x 8P emitters , ~A R3= R4- rb i] il
—
“to E.C,L, output stsges
and integrated with other components. One particular application area is the optical fiber link receiver [1], where a wide dynamic range input comparator with the right characteristics can ease or even remove the requirement for automatic gain control systems. The motivation for this particular design was for such a proposed receiver, but the parts produced and the design techniques requirements. described are equally applicable to other
