8051 Microcontroller Instruction Set

1API Program ExamplesReferences•Atmel 8051 Microcontrollers Hardware Manual1. IntroductionThis Application Note provides to customers C program examples for Api usages.24365A–80C51–07/0434365A–80C51–07/042. API for Standard C512.1 flash_eeprom_api.c/*C************************************************************************ NAME: flash_eeprom_api.c*-------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*-------------------------------------------------------------------------* RELEASE:* REVISION: 1.0*-------------------------------------------------------------------------* PURPOSE:* Read/Write flash* CAUTTION : add #define ONCHIP_EEPROM for on-chip eeprom products* (defined by default in the standard delivery)**************************************************************************//*_____ I N C L U D E - F I L E S _______________________________________*/#include "reg_C51.h"/*_____ D E C L A R A T I O N ___________________________________________*/#define ONCHIP_EEPROM //define it only for on-chip eeprom products/*---- API for FLASH access --------------------------------------------*//*************************************************************************/#define __api_rd_code_byte(address) (*((unsigned char code*) (address)))unsigned char__api_wr_code_byte(int , unsigned char)small;unsigned char__api_wr_code_page(int , int, unsigned char)small;/*---- API for EEPROM access -------------------------------------------*//*************************************************************************/#ifdef ONCHIP_EEPROMvoid __api_wr_eeprom_byte(unsigned int adr, unsigned char value);unsigned char __api_rd_eeprom_byte(unsigned int adr);#endif/*_____ G L O B A L S ___________________________________________________*/sfr16 DPTR = 0x82;/*_____ L O C A L S _____________________________________________________*/#define MSK_AUXR1_ENBOOT0x20#define MSK_AUXR_M00x20#define MAP_BOOT AUXR1 |= MSK_AUXR1_ENBOOT;#define UNMAP_BOOTAUXR1 &= ~MSK_AUXR1_ENBOOT;/*_____ EXTERNAL - F U N C T I O N S - D E C L A R A T I O N ____________*/extern void ASM_MOV_R1_A(void);extern void __API_FLASH_ENTRY_POINT(void);/*F************************************************************************ NAME: __api_wr_code_byte*-------------------------------------------------------------------------* PARAMS:* int address : address to program* unsigned char value : data to write* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* Program data byte in Flash memory**************************************************************************/unsigned char __api_wr_code_byte (int address, unsigned char value) small{bit ea_save;ea_save = EA;EA = 0;DPTR = address;ACC = 0x02;ASM_MOV_R1_A();ACC = value;MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn (ACC);}/*F************************************************************************ NAME: __api_wr_code_page*-------------------------------------------------------------------------* PARAMS:* int add_flash : address of the first byte to program in the Flash* int add_xram : address in XRAM of the first data to program* unsigned char nb_data : number of bytes to program*unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* Program until 128 Datas in Flash memory.* Number of bytes to program is limited such as the Flash write remains in a* single 128 bytes page.**************************************************************************/unsigned char __api_wr_code_page (int add_flash, int add_xram, unsigned charnb_data) small{unsigned char save_auxr1;bit ea_save;44365A–80C51–07/0454365A–80C51–07/04ea_save = EA;EA = 0;save_auxr1 = AUXR1;AUXR1 &= ~0x01; // Set DPTR=DPTR0DPTR = add_flash;AUXR1++; // DPTR = DPTR1DPTR = add_xram;ACC = 0x09;ASM_MOV_R1_A();ACC = nb_data;AUXR1 &= ~0x01; // Set DPTR = DPTR0MAP_BOOT__API_FLASH_ENTRY_POINT();UNMAP_BOOT;AUXR1 = save_auxr1;EA = ea_save; // restore interrupt statereturn (ACC);}/*F************************************************************************ NAME: __api_rd_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int adr: The EEDATA memory location to read* return: value*-------------------------------------------------------------------------* PURPOSE:* This function reads one byte in the on-chip EEPROM data.*-------------------------------------------------------------------------* EXAMPLE:* val=__api_rd_eeprom_byte(128);*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_rd_eeprom_byte(unsigned int adr){unsigned char val;bit ea_save;while (EECON&1);//Eeprom_busy()ea_save=EA;EA=0;EECON |= 0x02;//Enable eeprom data;val=*(unsigned char xdata*)adr;EECON &= ~0x02;//Disable eeprom data;EA=ea_save;return val;}/*F************************************************************************ NAME: __api_wr_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int adr: The EEDATA memory location to read* unsigned char value: The data byte to write* return: none*-------------------------------------------------------------------------* PURPOSE:* This function writes one byte in the on-chip EEPROM data.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/void __api_wr_eeprom_byte(unsigned int adr, unsigned char value){bit ea_save;while(EECON & 0x01);// wait bit busyea_save=EA;EA=0;EECON |= 0x02;//Enable eeprom data*(unsigned char xdata*)adr=value;EECON &= ~0x02;//Disable eeprom dataEA=ea_save;}64365A–80C51–07/0474365A–80C51–07/042.2 flash_lib.a51NAME FLASH_LIB;;*A51********************************************************************; FILE_NAME : FLASH_LIB.a51 ;------------------------------------------------------------------------ ;------------------------------------------------------------------------; FILE_PURPOSE: low level function for API;************************************************************************USING 0PUBLIC ASM_MOV_R1_APUBLIC __API_FLASH_ENTRY_POINTAUXR1 EQU0A2hSTART SEGMENT CODERSEG START;************************************************************************; FUNCTION_NAME: ASM_MOV_A_R1;************************************************************************ASM_MOV_R1_A:Mov R1, ARet;************************************************************************; FUNCTION_NAME: __API_FLASH_ENTRY_POINT;************************************************************************__API_FLASH_ENTRY_POINT:PUSHAR2PUSHAR4PUSHAR6LCALL 0FFF0hPOPAR6POPAR4POPAR2RetEND3. API for USB products3.1 flash_eeprom_api.c/*C************************************************************************ NAME: flash_eeprom_api.c*-------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*-------------------------------------------------------------------------* RELEASE:* REVISION:*-------------------------------------------------------------------------* PURPOSE:* This file contains whole of functions to access AT89C5131 Flash and* EEPROM and AT89C51SND1.* CAUTTION : add #define ONCHIP_EEPROM for on-chip eeprom products* (defined by default in the standard delivery)**************************************************************************//*_____ I N C L U D E S _________________________________________________*/#include "reg_C51.h"/*_____ D E F I N I T I O N _____________________________________________*/#define ONCHIP_EEPROM //define it only for build-in eeprom chipsunsigned char data api_command _at_ 0x1C;unsigned char data api_value _at_ 0x1D;#define MSK_AUXR1_ENBOOT 0x20#define MAP_BOOT AUXR1 |= MSK_AUXR1_ENBOOT;#define UNMAP_BOOT AUXR1 &= ~MSK_AUXR1_ENBOOT;#define __API_FLASH_ENTRY_POINT (*((const void(code*)(void)) 0xFFC0 ))/*_____ D E C L A R A T I O N ___________________________________________*//*---- API for FLASH access --------------------------------------------*//*************************************************************************/unsigned char __api_rd_code_byte (unsigned char code * pt_address);unsigned char __api_wr_code_byte (unsigned char xdata* , unsigned char);unsigned char __api_wr_code_page (unsigned char xdata* pt_code,unsigned char xdata* pt_xram,unsigned char nb_data);/*---- API for EEPROM access -------------------------------------------*//*************************************************************************/#ifdef ONCHIP_EEPROMunsigned char __api_rd_eeprom_byte(unsigned char xdata *);unsigned char __api_wr_eeprom_byte(unsigned char xdata *, unsigned char);#endif84365A–80C51–07/0494365A–80C51–07/04/*F************************************************************************ NAME: __api_rd_code_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int address : address in flash memory to read* return:* unsigned char device : read value*-------------------------------------------------------------------------* PURPOSE:* This function allows to read a flash memory byte.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_rd_code_byte (unsigned char code * pt_address){return(*pt_address);}/*F************************************************************************ NAME: __api_wr_code_byte*-------------------------------------------------------------------------* PARAMS:* unsigned int address : address to program* unsigned char value : data to write* return:* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* This function allows to program data byte in Flash memory.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_wr_code_byte (unsigned char xdata * pt_address, unsigned char value){bit ea_save;ea_save = EA;EA = 0;api_command = 0x0D; //_COMMAND_WR_CODE_BYTE;FCON = 0x08;*pt_address = value;MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn(api_value);}/*F************************************************************************ NAME: __api_wr_code_page*-------------------------------------------------------------------------* PARAMS:* unsigned int add_flash : address of the first byte to program* in the Flash* unsigned int add_xram : address in XRAM of the first data to program* unsigned char nb_data : number of bytes to program* return:* unsigned char return :* return = 0x00 -> pass* return != 0x00 -> fail*-------------------------------------------------------------------------* PURPOSE:* This function allows to program until 128 Datas in Flash memory.* Number of bytes to program is limited such as the Flash write remains* in a single 128 bytes page.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:* This function used Dual Data Pointer DPTR0&1. At the end of this* function.* DPTR = DPTR0.*-------------------------------------------------------------------------* REQUIREMENTS:**************************************************************************/unsigned char __api_wr_code_page (unsigned char xdata * pt_code,unsigned char xdata * pt_xram,unsigned char nb_data){unsigned char data i, temp, temp_nb_data;bit ea_save;unsigned int data add_pt_code, add_pt_xram;add_pt_xram = pt_xram;add_pt_code = pt_code;temp_nb_data = nb_data;104365A–80C51–07/04114365A–80C51–07/04ea_save = EA;EA = 0;api_command = 0x0D;for (i=0 ; i< temp_nb_data; i++,add_pt_xram++,add_pt_code++){temp = *(unsigned char xdata *)add_pt_xram;FCON = 0x08;*(unsigned char xdata *)add_pt_code = temp;FCON = 0x00;}MAP_BOOT;__API_FLASH_ENTRY_POINT();UNMAP_BOOT;EA = ea_save; // restore interrupt statereturn(api_value);}#ifdef ONCHIP_EEPROM/*F************************************************************************ NAME: api_rd_eeprom*-------------------------------------------------------------------------* PARAMS:* unsigned char xdata *address : address to read* return:*-------------------------------------------------------------------------* PURPOSE:* This function allows to read a byte in Eeprom.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS: The EEPROM mustn't be busy to perform the read access.* eeprom status :(EECON & 0x01)=1 busy, =0 free**************************************************************************/unsigned char __api_rd_eeprom_byte(unsigned char xdata *address){unsigned char val;bit ea_save;ea_save = EA;EA = 0;EECON = 0x02;val = *address;EECON = 0x00;EA = ea_save;return (val);}/*F************************************************************************ NAME: api_wr_eeprom_byte*-------------------------------------------------------------------------* PARAMS:* unsigned char xdata* address : address to read* unsigned char value : data to write* return:*-------------------------------------------------------------------------* PURPOSE:* This function allows to program a byte in Eeprom.*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS: The EEPROM mustn't be busy to perform the read access.* eeprom status :(EECON & 0x01)=1 busy, =0 free**************************************************************************/unsigned char __api_wr_eeprom_byte (unsigned char xdata *address,unsigned char value){bit ea_save;while(EECON & 0x01);// wait bit busyea_save = EA;EA = 0;EECON = 0x02;*address = value;/* addr is a pointer to external data mem */EECON = 0x50;EECON = 0xA0;EA = ea_save;return (1);}#endif124365A–80C51–07/04134365A–80C51–07/044. Example4.1 test_api.c/*C*********************************************************************** NAME: test_api.c*------------------------------------------------------------------------* Copyright (c) 2004 Atmel.*------------------------------------------------------------------------* RELEASE:* REVISION: 1.0*------------------------------------------------------------------------* PURPOSE: usage example of flash_eeprom_api.c*************************************************************************//*_____ I N C L U D E S ________________________________________________*/#include "flash_eeprom_api.c"/*F************************************************************************ NAME: main*-------------------------------------------------------------------------* PARAMS:*-------------------------------------------------------------------------* PURPOSE: usage example of flash_eeprom_api.c*-------------------------------------------------------------------------* EXAMPLE:*-------------------------------------------------------------------------* NOTE:*-------------------------------------------------------------------------* REQUIREMENTS:*************************************************************************/void main (void){int adress;char i=0;char data_tmp;/* write code page example */for(adress=0x0000;adress<0x007F;adress++){/* write 0x55 between 0x0000 and 0x007F of xram */*((unsigned char xdata*) adress)=0x55;}/* copy xram page to flash at 0x1100 */__api_wr_code_page(0x1100,0x0000,0x7F);/* write code byte example */i=0;for(adress=0x1000;adress<0x1006;adress++){/* write "ABCDEF" at 0x1000 */__api_wr_code_byte(adress,0x41+i++);}/* read and write code byte example */for(adress=0x1000;adress<0x1006;adress++){/* copy 0x1000-0x1006 to 0x1010-0x1016 in flash memory */data_tmp = __api_rd_code_byte(adress);__api_wr_code_byte(adress+0x0010,data_tmp);}#ifdef ONCHIP_EEPROM/* write eeprom byte example */i=0;for (adress=0x000;adress<0x400;adress++) /* write 1Ko of eeprom */{/* write a byte, write time = 10ms to 20ms */__api_wr_eeprom_byte(adress,i++);}/* read eeprom byte example */for (adress=0x000;adress<0x400;adress++){/* copy previous writed data from eeprom to flash at 0x1200 */data_tmp=__api_rd_eeprom_byte(adress);__api_wr_code_byte(0x1200+adress,data_tmp);}#endifwhile(1); /* endless */}144365A–80C51–07/04154365A–80C51–07/044.2 SFR Register Definition/*H**************************************************************************** NAME: AT89C51XD2.h*----------------------------------------------------------------------------* PURPOSE: SFR Description file for AT89C51xD2 products* ON KEIL compiler*****************************************************************************/#define Sfr(x, y) sfr x = y#define Sbit(x, y, z) sbit x = y^z#define Sfr16(x,y) sfr16 x = y/*----------------------------------------*//* Include file for 8051 SFR Definitions *//*----------------------------------------*//* BYTE Register */Sfr (P0 , 0x80);Sbit (P0_7 , 0x80, 7);Sbit (P0_6 , 0x80, 6);Sbit (P0_5 , 0x80, 5);Sbit (P0_4 , 0x80, 4);Sbit (P0_3 , 0x80, 3);Sbit (P0_2 , 0x80, 2);Sbit (P0_1 , 0x80, 1);Sbit (P0_0 , 0x80, 0);Sfr (P1 , 0x90);Sbit (P1_7 , 0x90, 7);Sbit (P1_6 , 0x90, 6);Sbit (P1_5 , 0x90, 5);Sbit (P1_4 , 0x90, 4);Sbit (P1_3 , 0x90, 3);Sbit (P1_2 , 0x90, 2);Sbit (P1_1 , 0x90, 1);Sbit (P1_0 , 0x90, 0);Sfr (P2 , 0xA0);Sbit (P2_7 , 0xA0, 7);Sbit (P2_6 , 0xA0, 6);Sbit (P2_5 , 0xA0, 5);Sbit (P2_4 , 0xA0, 4);Sbit (P2_3 , 0xA0, 3);Sbit (P2_1 , 0xA0, 1);Sbit (P2_0 , 0xA0, 0);Sfr (P3 , 0xB0);Sbit (P3_7 , 0xB0, 7);Sbit (P3_6 , 0xB0, 6);Sbit (P3_5 , 0xB0, 5);Sbit (P3_4 , 0xB0, 4);Sbit (P3_3 , 0xB0, 3);Sbit (P3_2 , 0xB0, 2);Sbit (P3_1 , 0xB0, 1);Sbit (P3_0 , 0xB0, 0);Sbit (RD , 0xB0, 7);Sbit (WR , 0xB0, 6);Sbit (T1 , 0xB0, 5);Sbit (T0 , 0xB0, 4);Sbit (INT1 , 0xB0, 3);Sbit (INT0 , 0xB0, 2);Sbit (TXD , 0xB0, 1);Sbit (RXD , 0xB0, 0);Sfr (P4 , 0xC0);Sbit (P4_7 , 0xC0, 7);Sbit (P4_6 , 0xC0, 6);Sbit (P4_5 , 0xC0, 5);Sbit (P4_4 , 0xC0, 4);Sbit (P4_3 , 0xC0, 3);Sbit (P4_2 , 0xC0, 2);Sbit (P4_1 , 0xC0, 1);Sbit (P4_0 , 0xC0, 0);Sfr (P5 , 0xE8);Sbit (P5_7 , 0xE8, 7);Sbit (P5_6 , 0xE8, 6);Sbit (P5_5 , 0xE8, 5);Sbit (P5_4 , 0xE8, 4);Sbit (P5_3 , 0xE8, 3);Sbit (P5_2 , 0xE8, 2);Sbit (P5_1 , 0xE8, 1);Sbit (P5_0 , 0xE8, 0);Sfr (PSW , 0xD0);Sbit (CY , 0xD0 , 7);Sbit (AC , 0xD0 , 6);164365A–80C51–07/04174365A–80C51–07/04Sbit (RS1 , 0xD0 , 4);Sbit (RS0 , 0xD0 , 3);Sbit (OV , 0xD0 , 2);Sbit (UD , 0xD0 , 1);Sbit (P , 0xD0 , 0);Sfr (ACC , 0xE0);Sfr (B , 0xF0);Sfr (SP , 0x81);Sfr (DPL , 0x82);Sfr (DPH , 0x83);Sfr (PCON , 0x87);Sfr (CKCON0 , 0x8F);Sfr (CKCON1 , 0xAF);/*------------------ TIMERS registers ---------------------*/Sfr (TCON , 0x88);Sbit (TF1 , 0x88, 7);Sbit (TR1 , 0x88, 6);Sbit (TF0 , 0x88, 5);Sbit (TR0 , 0x88, 4);Sbit (IE1 , 0x88, 3);Sbit (IT1 , 0x88, 2);Sbit (IE0 , 0x88, 1);Sbit (IT0 , 0x88, 0);Sfr (TMOD , 0x89);Sfr (T2CON , 0xC8);Sbit (TF2 , 0xC8, 7);Sbit (EXF2 , 0xC8, 6);Sbit (RCLK , 0xC8, 5);Sbit (TCLK , 0xC8, 4);Sbit (EXEN2 , 0xC8, 3);Sbit (TR2 , 0xC8, 2);Sbit (C_T2 , 0xC8, 1);Sbit (CP_RL2, 0xC8, 0);Sfr (T2MOD , 0xC9);Sfr (TL0 , 0x8A);Sfr (TL1 , 0x8B);Sfr (TL2 , 0xCC);Sfr (TH0 , 0x8C);Sfr (TH1 , 0x8D);Sfr (TH2 , 0xCD);Sfr (RCAP2L , 0xCA);Sfr (RCAP2H , 0xCB);Sfr (WDTRST , 0xA6);/*------------------- UART registers ------------------------*/Sfr (SCON , 0x98);Sbit (SM0 , 0x98, 7);Sbit (FE , 0x98, 7);Sbit (SM1 , 0x98, 6);Sbit (SM2 , 0x98, 5);Sbit (REN , 0x98, 4);Sbit (TB8 , 0x98, 3);Sbit (RB8 , 0x98, 2);Sbit (TI , 0x98, 1);Sbit (RI , 0x98, 0);Sfr (SBUF , 0x99);Sfr (SADEN , 0xB9);Sfr (SADDR , 0xA9);/*-------------------- Internal Baud Rate Generator --------*/Sfr (BRL , 0x9A);Sfr (BDRCON , 0x9B);/*-------------------- IT registers -----------------------*/Sfr (IEN0 , 0xA8);Sfr (IEN1 , 0xB1);Sfr (IPH0 , 0xB7);Sfr (IPH1 , 0xB3);Sfr (IPL0 , 0xB8);Sfr (IPL1 , 0xB2);/* IEN0 */Sbit (EA , 0xA8, 7);Sbit (EC , 0xA8, 6);Sbit (ET2 , 0xA8, 5);Sbit (ES , 0xA8, 4);Sbit (ET1 , 0xA8, 3);Sbit (EX1 , 0xA8, 2);Sbit (ET0 , 0xA8, 1);Sbit (EX0 , 0xA8, 0);/*--------------------- PCA registers -----------------------------*/Sfr (CCON , 0xD8);Sfr (CMOD , 0xD9);Sfr (CH , 0xF9);184365A–80C51–07/04194365A–80C51–07/04Sfr (CCAP0H , 0xFA);Sfr (CCAP0L , 0xEA);Sfr (CCAPM0 , 0xDA);Sfr (CCAP1H , 0xFB);Sfr (CCAP1L , 0xEB);Sfr (CCAPM1 , 0xDB);Sfr (CCAP2H , 0xFC);Sfr (CCAP2L , 0xEC);Sfr (CCAPM2 , 0xDC);Sfr (CCAP3H , 0xFD);Sfr (CCAP3L , 0xED);Sfr (CCAPM3 , 0xDD);Sfr (CCAP4H , 0xFE);Sfr (CCAP4L , 0xEE);Sfr (CCAPM4 , 0xDE);/* CCON */Sbit (CF , 0xD8, 7);Sbit (CR , 0xD8, 6);Sbit (CCF4 , 0xD8, 4);Sbit (CCF3 , 0xD8, 3);Sbit (CCF2 , 0xD8, 2);Sbit (CCF1 , 0xD8, 1);Sbit (CCF0 , 0xD8, 0);/*------------------ T W I registers ------------------------------*/Sfr ( SSCON , 0x93);Sfr ( SSCS , 0x94);Sfr ( SSDAT , 0x95);Sfr ( SSADR , 0x96);Sfr ( PI2, 0xF8);Sbit (PI2_1 , 0xF8, 1);Sbit (PI2_0 , 0xF8, 0);/*-------------------- OSC control registers ----------------------*/Sfr ( CKSEL , 0x85 );Sfr ( OSCCON , 0x86 );Sfr ( CKRL , 0x97 );/*-------------------- Keyboard control registers -----------------*/Sfr ( KBLS , 0x9C );Sfr ( KBE , 0x9D );Sfr ( KBF , 0x9E );/*-------------------- SPI ---------------------- -----------------*/Sfr ( SPCON, 0xC3 );Sfr ( SPSTA, 0xC4 );Sfr ( SPDAT, 0xC5 );/*------ Misc ----------------------------------------------------*/Sfr( AUXR , 0x8E);Sfr ( AUXR1, 0xA2);Sfr ( FCON, 0xD1);/*------ E data --------------------------------------------------*/Sfr ( EECON, 0xD2 );204365A–80C51–07/04Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. 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○ Unlimited number of software watch-points
Internal (direct) Data Memory Special Function Registers (SFRs) External Data Memory
○ Unlimited number of software breakpoints
CONFIGURATION
The following parameters of the DP8051 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.
Besides mentioned above parameters all available peripherals and external interrupts can be excluded from the core by changing appropriate constants in package file.
•
Internal type
Program
Memory
- synchronous - asynchronous
•
Internal Program Memory size
ROM
-
0 - 64kB
•

Validation and Testing of Design Hardening for Single Event Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries, new and novel techniques are being developed for hardening designs using non-dedicated foundry services. In this paper, we will discuss the implications of validating these methods for the single event effects (SEE) in the space environment. Topics include the types of tests that are required and the design coverage (i.e., design libraries: do they need validating for each application?). Finally, an 8051 microcontroller core from NASA Institute of Advanced Microelectronics (IAμE) CMOS Ultra Low Power Radiation Tolerant (CULPRiT) design is evaluated for SEE mitigative techniques against two commercial 8051 devices.Index TermsSingle Event Effects, Hardened-By-Design, microcontroller, radiation effects.I. INTRODUCTIONNASA constantly strives to provide the best capture of science while operating in a space radiation environment using a minimum of resources [1,2]. With a relatively limited selection of radiation-hardened microelectronic devices that are often two or more generations of performance behind commercialstate-ofthe-art technologies, NASA’s performance of this task is quite challenging. One method of alleviating this is by the use of commercial foundry alternatives with no or minimally invasive design techniques for hardening. This is often called hardened-by-design (HBD).Building custom-type HBD devices using design libraries and automated design tools may provide NASA the solution it needs to meet stringent science performance specifications in a timely,cost-effective, and reliable manner.However, one question still exists: traditional radiation-hardened devices have lot and/or wafer radiation qualification tests performed; what types of tests are required for HBD validation?II. TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices through standards and organizations such as ASTM, JEDEC, and MIL-STD- 883. Typically, TID (Co-60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices?As opposed to a “regular” commercial-off-the-shelf (COTS) device or application specific integrated circuit (ASIC) where no hardening has been performed, one needs to determine how validated is the design library as opposed to determining the device hardness. That is, by using test chips, can we “qualify” a future device using the same library?Consider if Vendor A has designed a new HBD library portable to foundries B and C. A test chip is designed, tested, and deemed acceptable. Nine months later a NASA flight project enters the mix by designing a new device using Vendor A’s library. Does this device require complete radiation qualification testing? To answer this, other questions must be asked.How complete was the test chip? Was there sufficient statistical coverage of all library elements to validate each cell? If the new NASA design uses a partially or insufficiently characterized portion of the design library, full testing might be required. Of course, if part of the HBD was relying on inherent radiation hardness of a process, some of the tests (like SEL in the earlier example) may be waived.Other considerations include speed of operation and operating voltage. For example, if the test chip was tested statically for SEE at a power supply voltage of 3.3V, is the data applicable to a 100 MHz operating frequency at 2.5V? Dynamic considerations (i.e., nonstatic operation) include the propagated effects of Single Event Transients (SETs). These can be a greater concern at higher frequencies.The point of the considerations is that the design library must be known, the coverage used during testing is known, the test application must be thoroughly understood and the characteristics of the foundry must be known. If all these are applicable or have been validated by the test chip, then no testing may be necessary. A task within NASA’s Electronic Parts and Packaging (NEPP) Program was performed to explore these types of considerations.III. HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption, microcontrollers are increasingly being used in NASA and DOD system designs. There are existing NASA and DoD programs that are doing technology development to provide HBD. Microcontrollers are one such vehicle that is being investigated to quantify the radiation hardness improvement. Examples of these programs are the 8051 microcontroller being developed by Mission Research Corporation (MRC) and the IAμE (the focus of this study). As these HBD technologies become available, validation of the technology, in the natural space radiation environment, for NASA’s use in spaceflight systems is required.The 8051 microcontroller is an industry standard architecture that has broad acceptance, wide-ranging applications and development tools available. There are numerous commercial vendors that supply this controller or have it integrated into some type of system-on-a-chip structure. Both MRC and IAμE chose this device to demonstrate two distinctly different technologies for hardening. The MRC example of this is to use temporal latches that require specific timing to ensure that single event effects are minimized. The IAμE technology uses ultra low power, and layout and architecture HBD design rules to achieve their results. These are fundamentally different than the approach by Aeroflex-United Technologies Microelectronics Center (UTMC), the commercial vendor of a radiation–hardened 8051, that built their 8051 microcontroller using radiationhardened processes. This broad range of technology within one device structure makes the 8051an ideal vehicle for performing this technology evaluation.The objective of this work is the technology evaluation of the CULPRiT process [3] from IAμE. The process has been baselined against two other processes, the standard 8051 commercial device from Intel and a version using state-of-the-art processing from Dallas Semiconductor. By performing this side-by-side comparison, the cost benefit, performance, and reliability trade study can be done.In the performance of the technology evaluation, this task developed hardware and software for testing microcontrollers. A thorough process was done to optimize the test process to obtain as complete an evaluation as possible. This included taking advantage of the available hardware and writing software that exercised the microcontroller such that all substructures of the processor were evaluated. This process is also leading to a more complete understanding of how to test complex structures, such as microcontrollers, and how to more efficiently test these structures in the future.IV. TEST DEVICESThree devices were used in this test evaluation. The first is the NASA CULPRiT device, which is the primary device to be evaluated. The other two devices are two versions of a commercial 8051, manufactured by Intel and Dallas Semiconductor, respectively.The Intel devices are the ROMless, CMOS version of the classic 8052 MCS-51 microcontroller. They are rated for operation at +5V, over a temperature range of 0 to 70 °C and at a clock speeds of 3.5 MHz to 24 MHz. They are manufactured in Intel’s P629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052 microcontrollers, but they are enhanced in various ways. They are rated for operation from 4.25 to 5.5 Volts over 0 to 70 °C at clock speeds up to 25 MHz. They have a second full serial port built in, seven additional interrupts, a watchdog timer, a power fail reset, dual data pointers and variable speed peripheral access. In addition, the core is redesigned so that the machine cycle is shortened for most instructions, resulting in an effective processing ability that is roughly 2.5 times greater (faster) than the standard 8052 device. None of these features, other than those inherent in the device operation, were utilized in order to maximize the similarity between the Dallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatible C8051 HDL core licensed from the Ultra Low Power (ULP) process foundry. The CULPRiT technology C8051 device is designed to operate at a supply voltage of 500 mV and includes an on-chip input/output signal level-shifting interface with conventional higher voltage parts. The CULPRiT C8051 device requires two separate supply voltages; the 500 mV and the desired interface voltage. The CULPRiT C8051 is ROMless and is intended to be instruction set compatible with the MSC-51 family.V. TEST HARDWAREThe 8051 Device Under Test (DUT) was tested as a component of a functional computer. Aside from DUT itself, the other componentsof the DUT computer were removed from the immediate area of the irradiation beam.A small card (one per DUT package type) with a unique hard-wired identifier byte contained the DUT, its crystal, and bypass capacitors (and voltage level shifters for the CULPRiT DUTs). This "DUT Board" was connected to the "Main Board" by a short 60-conductor ribbon cable. The Main Board had all other components required to complete the DUT Computer, including some which nominally are not necessary in some designs (such as external RAM, external ROM and address latch). The DUT Computer and the Test Control Computer were connected via a serial cable and communications were established between the two by the Controller (that runs custom designed serial interface software). This Controller software allowed for commanding of the DUT, downloading DUT Code to the DUT, and real-time error collection from the DUT during and post irradiation. A 1 Hz signal source provided an external watchdog timing signal to the DUT, whose watchdog output was monitored via an oscilloscope. The power supply was monitored to provide indication of latchup.VI. TEST SOFTWAREThe 8051 test software concept is straightforward. It was designed to be a modular series of small test programs each exercising a specific part of the DUT. Since each test was stand alone, they were loaded independently of each other for execution on the DUT. This ensured that only the desired portion of the 8051 DUT was exercised during the test and helped pinpoint location of errors that occur during testing. All test programs resided on the controller PC until loaded via the serial interface to the DUT computer. In this way, individual tests could have been modified at any time without the necessity of burning PROMs. Additional tests could have also been developed and added without impacting the overall test design. The only permanent code, which was resident on the DUT, was the boot code and serial code loader routines that established communications between the controller PC and the DUT.All test programs implemented:• An external Universal Asynchronous Receive and Transmit device (UART) for transmission of error information and communication to controller computer.• An external real-time clock for data error tag.•A watchdog routine designed to provide visual verification of 8051 health and restart test code if necessary.• A "foul-up" routine to reset program counter if it wanders out of code space.• An external telemetry data storage memory to provide backup of data in the event of an interruption in data transmission.The brief description of each of the software tests used is given below. It should be noted that for each test, the returned telemetry (including time tag) was sent to both the test controller and the telemetry memory, giving the highest reliability that all data is captured.Interrupt –This test used 4 of 6 available interrupt vectors (Serial, External, Timer0 Overflow, and Timer1 Overflow) to trigger routines that sequentially modified a value in the accumulator which was periodically compared to a known value. Unexpected values were transmitted with register information.Logic –This test performed a series of logic and math computations and provided three types of error identifications: 1) addition/subtraction, 2) logic and 3) multiplication/division. All miscompares of computations and expected results were transmitted with other relevant register information.Memory – This test loaded internal data memory at locations D:0x20 through D:0xff (or D:0x20 through D:0x080 for the CULPRiT DUT), indirectly, with an 0x55 pattern. Compares were performed continuously and miscompares were corrected while error information and register values were transmitted.Program Counter -The program counter was used to continuously fetch constants at various offsets in the code. Constants were compared with known values and miscompares were transmitted along with relevant register information. Registers – This test loaded each of four (0,1,2,3) banks of general-purpose registers with either 0xAA (for banks 0 and 2) or 0x55 (for banks 1 and 3). The pattern was alternated in order to test the Program Status Word (PSW) special function register, which controls general-purpose register bank selection. General-purpose register banks were then compared with their expected values. All miscompares were corrected and error information was transmitted.Special Function Registers (SFR) – This test used learned static values of 12 out 21 available SFRs and then constantly compared the learned value with the current one. Miscompares were reloaded with learned value and error information was transmitted.Stack – This test performed arithmetic by pushing and popping operands on the stack. Unexpected results were attributed to errors on the stack or to the stack pointer itself and were transmitted with relevant register information.VII. TEST METHODOLOGYThe DUT Computer booted by executing the instruction code located at address 0x0000. Initially, the device at this location was an EPROM previously loaded with "Boot/Serial Loader" code. This code initialized the DUT Computer and interface through a serial connection to the controlling computer, the "Test Controller". The DUT Computer downloaded Test Code and put it into Program Code RAM (located on the Main Board of the DUT Computer). It then activated a circuit which simultaneously performed two functions: held the DUT reset line active for some time (~10 ms); and, remapped the Test Code residing in the Program Code RAM to locate it to address 0x0000 (the EPROM will no longer be accessible in the DUT Computer's memory space). Upon awaking from the reset, the DUT computer again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code.The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer's functionality. Thus, if the test ran without a Single Event Functional Interrupt (SEFI) either the DUT Computer itselfor the Test Controller could have terminated the test and allowed the post-test functions to be executed. If a SEFI occurred, the Test Controller forced a reboot into Boot/Serial Loader code and then executed the post-test functions. During any test of the DUT, the DUT exercised a portion of its functionality (e.g., Register operations or Internal RAM check, or Timer operations) at the highest utilization possible, while making a minimal periodic report to the Test Control Computer to convey that the DUT Computer was still functional. If this reportceased, the Test Controller knew that a SEFI had occurred. This periodic data was called "telemetry". If the DUT encountered an error that was not interrupting the functionality (e.g., a data register miscompare) it sent a more lengthy report through the serial port describing that error, and continued with the test.VIII.DISCUSSIONA. Single Event LatchupThe main argument for why latchup is not an issue for the CULPRiT devices is that the operating voltage of 0.5 volts should be below the holding voltage required for latchup to occur. In addition to this, the cell library used also incorporates the heavy dual guard-barring scheme [4]. This scheme has been demonstrated multiple times to be very effective in rendering CMOS circuits completely immune to SEL up to test limits of 120 MeV-cm2/mg. This is true in circuits operating at 5, 3.3, and 2.5 Volts, as well as the 0.5 Volt CULPRiT circuits. In one case, a 5 Volt circuit fabricated on noncircuits wafers even exhibited such SEL immunity.B. Single Event UpsetThe primary structure of the storage unit used in the CULPRiT devices is the Single Event Resistant Topology (SERT) [5]. Given the SERT cell topology and a single upset node assumption, it is expected that the SERT cell will be completely immune to SEUs occurring internal to the memory cell itself. Obviously there are other things going on. The CULPRiT 8051 results reported here are quite similar to some resultsobtained with a CULPRiT CCSDS lossless compression chip (USES) [6]. The CULPRiT USES was synthesized using exactly the same tools and library as the CULPRiT 8051.With the CULPRiT USES, the SEU cross section data [7] was taken as a function of frequency at two LET values, 37.6 and 58.5 MeV-cm2/mg. In both cases the data fit well to a linear model where cross section is proportional to clock. In the LET 37.6 case, the zero frequency intercept occurred essentially at the zero cross section point, indicating that virtually all of these SEUs are captured SETs from the combinational logic. The LET 58.5 data indicated that the SET (frequency dependent) component is sitting on top of a "dc-bias" component –presumably a second upset mechanism is occurring internal to the SERT cells only at a second, higher LET threshold.The SET mitigation scheme used in the CULPRiT devices is based on the SERT cell's fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of combinational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated place-and-route of the combinatorial logic paths may have placed dual sensitive nodes close enough.At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the combinatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 40-60 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this 0.35 μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at 0.5 Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the per-bit memory upset cross section for the CULPRiT devices and the commercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has become sensitive to upset.IX. SUMMARYA detailed comparison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been completed. This paper discusses the test methodology used and presents a comparison of the commercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the commercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results.This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a real-world device structure (i.e., not just a test chip), and comparing results to equivalent commercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application.ACKNOWLEDGEMENTSThe authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA).。

其后16个数据单元（Bit Addressable Area: 20H～2FH）
既可作为一般的数据单元使用，也可按位对每个单元进行操作 又称为位寻址区：共计128位，其位地址为00H～0FH bits 0-7 can also be referred to as bits 20.0-20.7, and bits 8FH are the same as 21.0-21.7 and so on.
Direct addresses higher than 7FH access one memory space, and indirect addresses higher than 7FH access a different memory space. Thus the Upper 128 and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities.
MOV One-byte addresses are often used in conjunction with one or more other I/O lines to page the RAM. Two-byte addresses can also be used, in which case the high address byte is emitted at Port 2.
8位 微控制器
16位 微控制器 32位 微控制器
8051系列
Intel公司于1980年开始推出MCS-51系列单片机 Siemens、Philips和Fujitsu等公司也相继推出与之兼容的单片