EP3C25-引脚信息

Bank

NumberVREFB

GroupPin Name /

FunctionOptional

Function(s)Configuration

FunctionE144

(4)Q240F256/

U256F324DQS for x8/x9 in

E144DQS for x8/x9 in Q240DQS for x8/x9 in

F256/U256DQS for x16/x18 in

F256/U256DQS for x8/x9 in

F324DQS for x16/x18 in

F324

B1VREFB1N0VCCD_PLL311D4F5

B1VREFB1N0GNDA322E5E5

B1VREFB1N0VCCA333F5E4

B1VREFB1N0IODIFFIO_L1p4B2DQ1LDQ1L

B1VREFB1N0IODIFFIO_L1n5B1

B1VREFB1N0IODIFFIO_L2p6C2

B1VREFB1N0IODIFFIO_L2nC1DQ1LDQ1L

B1VREFB1N0VCCIO17

B1VREFB1N0IOnRESETC3

B1VREFB1N0GND8

B1VREFB1N0IO49B1D3DQS2L/CQ3L,CDPCLK0DQS2L/CQ3L,CDPCLK0DQS2L/CQ3L,CDPCLK0DQS2L/CQ3L,CDPCLK0DQS2L/CQ3L,CDPCLK0

B1VREFB1N0VCCINT510

B1VREFB1N0IODIFFIO_L3pC2D2DQ1LDQ1L

B1VREFB1N0GND11

B1VREFB1N0IODIFFIO_L3nDATA1, ASDO612C1D1

B1VREFB1N0IOVREFB1N0713F3F3

B1VREFB1N0IODIFFIO_L4pFLASH_nCE, nCSO814D2E2

B1VREFB1N0VCCIO115

B1VREFB1N0IODIFFIO_L4nD1E1DQ1LDQ1L

B1VREFB1N0GND16

Power Consumption

Power

ConsumptionAltera® offers two ways to calculate power for a design: the Excel-based PowerPlay Early Power Estimator power calculator and the Quartus®II PowerPlay Power Analyzer feature.

The interactive Excel-based PowerPlay Early Power Estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The QuartusII PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The Power Analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.

In both cases, these calculations should only be used as an estimation of power, not as a specification.

fFor more information about PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Early Power Estimator and PowerPlay Power Analyzer chapters in volume 3 of the QuartusII Handbook.

Chapter 9:Using User Flash Memory in MAX II DevicesSoftware Support for UFM Block

MAX II Device Handbook4.An 8-bit data is transmitted through SI.5.nCS is pulled back to high to indicate the end of transmission.

Figure9–29 shows the WRITE operation sequence for Base mode.

SECTOR-ERASESECTOR-ERASE is the instruction of erasing one sector of the UFM block. Each sector contains 256 words. WEN bit and the sector must not be protected for SE operation to be successful. nCS must be driven high before the instruction is executed internally. You may poll the nRDY bit in the software status register for the completion of the internal self-timed SECTOR-ERASE cycle. For SPI Extended mode, the SE operation is performed in the following sequence, as shown in Figure9–30:1.nCS is pulled low.2.Opcode 00100000 is transmitted into the interface.3.The 16-bit address is sent. The eighth bit (the first seven bits will be discarded) ofthe address indicates which sector is erased; a 0 means sector 0 (UFM0) is erased,and a 1 means sector 1 (UFM1) is erased.Figure9–28.WRITE Operation Sequence for Extended Mode12345678910111213141516171819nCS

EP3C40的引脚

ClockandPLLPins

引脚名称第一功能，第

二功能，以此

类推。。。描述

CLK[0,2,4,6,9,11,13,15],DIFFCLK_[0..7]pClock,Input1、专用全局时钟输入脚

2、差分全局时钟正输入

3、用户输入

CLK[1,3,5,7,8,10,12,14],DIFFCLK_[0..7]nClock,Input1、专用全局时钟输入脚

2、差分全局时钟负输入

3、用户输入

PLL[1..4]_CLKOUT[p,n]I/O,OutputIO脚，可被用于两个单端

时钟输出，可被用为一对

差分时钟输出对，若由

PLL供给，则只能用差分

IO标准

可选的，双用途引脚

DCLKInput(PS,FPP)

I/O,

Output(AS,AP)可配置时钟脚。

1、在PS、FPP配置模式

下，此脚被用于从外部给

FPGA供应配置数据。

2、在AS、AP模式下，此

脚被用于从FPGA向外部

接口供给定时。

3、可用作一般IO

nCEOI/O,Output设备配置完毕后置低

FLASH_nCE,nCSOI/O,OutputAP模式下用作

FLASH_nCE，AS模式下

用作nCSO。此脚有个内

部一直处于使能状态的上

拉电阻。

FLASH_nCE：在AP模式

下向并行FLASH发送使

能信号

nCSO：在AS模式下向配

置设备发送使能信号。

DATA1,ASDOInput(FPP)

Output(AS)

Bidirectional

（双向作用

的）open-drain

(AP)在PS，FPP，AP模式下用

做DATA1，在AS模式下

用作ASDO。

DATA1：非AS模式下用

做数据输入。Byte-wide或

word-wide的配置数据分

别被DATA[7..0]或

DATA[15..0]送到目标设备。在PS配置方案下，被

用于用户I/O，是三态的。

在FPP模式，被用作用户

I/O,其状态由

Dual-PurposePinsettings.

决定。在AP模式，被专

用作双向备选控制脚。