Lenovo E43L
- 格式：pdf
- 大小：1.27 MB
- 文档页数：45
Cantiga
DDRII 800/1066 MHz
PCI-Express 16X
DDR III (TPS51116REGR) 1.5VSUS/SMDDR_VTERM /SMDDR_VREF PAGE
DDRIII-SODIMM2 39 PAGE 12
NVIDIA N10M-NS
CRT
B
PAGE 23
PAGE 13~18 NBSRCCLK, NBSRCCLK#
02
ON S0~S2
X X X X X X X X X X X X X X
ON S3
ON S4
ON S5
Control signal
VRON MAINON MAINON S5_ON SUSON MAINON MAINON LAN_ON VL VL
D
D
X X X
X X X
X X X
Power On Sequencing Timing Diagram VID VRON
A
+1.05V PROJECT : LE9E
Ta=VCC and VCCP asseration to VID[6:0] vaild Tb=VID[6:0] stable to VCC vaild Tc=BCLK stable to PWRGOOD assertion Td=PWRGOOD to RESET# de-assertion time Te=Vcc,boot vaild to PWRGOOD assertion time
C
Tsft_star_vcc Vboot Vid
C
VCC_CORE CPU_UP Vccp Vccp_UP Vccgmch GMCHPWRGD CLK_ENABLE# IMVP6_PWRGD
Tboot Tboot-vid-tr Tcpu_up
Tvccp_up
ACIN
Tgmch_pwrgd ACIN 5VPCU/3VPCU Tcpu_pwrgd NBSWON#
+CK_VDD_MAIN2 0.1U/10V/X5R_4 C346 1 +CK_VDD_MAIN 16 9 2 61 39 55 12 20 26 45 36 49 48
U8 VDDPLL3 VDD48 VDDPCI VDDREF VDDSRC VDDCPU VDD96I/O VDDPLL3I/O VDDSRCI/O VDDSRCI/O VDDSRCI/O VDDCPU_IO NC X1 X2 CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUT2_ITP/SRCT8 CPUT2_ITP/SRCC8 DOTT_96/SRCT0 DOTC_96/SRCC0 27MHz_Nonss/SRCCLK1/SE1 27Mhz_ss/SRCCLC1/SE2 SRCCLKT2/SATACL SRCCLKC2/SATACL SRCCLKT3/CR#_C SRCCLKC3/CR#_D SRCCLKT4 SRCCLKC4 54 53 51 50 47 46 13 14 17 18 21 22 24 25 27 28 38 37 41 40 44 43 30 31 34 35 33 32 1 3 4 5 6 R_DOT96 R_DOT96# R_DREFSSCLK R_DREFSSCLK# CLK_PCIE_SATA CLK_PCIE_SATA# R_CLK_PCIE_VGA RP17 2 R_CLK_PCIE_VGA# 4 CLK_PCIE_LAN CLK_PCIE_LAN# PM_STPPCI# PM_STPCPU# CLK_PCIE_ICH CLK_PCIE_ICH# CLK_PCIE_MINI CLK_PCIE_MINI# CLK_PCIE_3GPLL CLK_PCIE_3GPLL# CLK_PCIE_NEW CLK_PCIE_NEW# NEW-CARD_CLK_REQ#_R R223 CLK_3GPLLREQ#_R R189 R_PCLK_8512 PCLK_MINI_LPC RPCI_CLK_SIO FCTSEL1 R186 R180 R194 R179 R184 475/F_4 475/F_4 1 EV@4P2R-S-0 3 RP14 2 4 RP13 2 4 1 *IV@4P2R-S-0 3 1 *IV@4P2R-S-0 3 DREFCLK (7) DREFCLK# (7) DREFSSCLK (7) DREFSSCLK# (7) CLK_PCIE_SATA (19) CLK_PCIE_SATA# (19) CLK_PCIE_VGA (13) CLK_PCIE_VGA# (13) CLK_PCIE_LAN (31) CLK_PCIE_LAN# (31) PM_STPPCI# (21) PM_STPCPU# (21) CLK_PCIE_ICH (20) CLK_PCIE_ICH# (20) CLK_PCIE_MINI (35) CLK_PCIE_MINI# (35) CLK_PCIE_3GPLL (7) CLK_PCIE_3GPLL# (7) CLK_PCIE_NEW (33) CLK_PCIE_NEW# (33) NEW-CARD_CLK_REQ# CLK_MCH_OE# 33_4 475/F_4 33_4 33_4 33_4 NEW-CARD_CLK_REQ# (33) CLK_MCH_OE# (7) CLK_CPU_BCLK CLK_CPU_BCLK# CLK_MCH_BCLK CLK_MCH_BCLK# CLK_CPU_BCLK (4) CLK_CPU_BCLK# (4) CLK_MCH_BCLK (6) CLK_MCH_BCLK# (6)
L20 1 HI0805R800R_8
2 10U/6.3V/X5R_8 C354 0.1U/10V/X5R_4 C384 0.1U/10V/X5R_4 0.1U/10V/X5R_4 C386 C386 0.1U/10V/X5R_4 0.1U/10V/X5R_4 C383 0.1U/10V/X5R_4 C343 0.1U/10V/X5R_4 C344 1 1 1 1 1
VCCP +1.5V AND GMCH 1.05V(RT8204)
PAGE 43
CPU Penryn
478P (uPGA)/35W PAGE 4,5
CPU THERMAL SENSOR PAGE 5
CLK_CPU_BCLK,CLK_CPU_BCLK# CLK_MCH_BCLK,CLK_MCH_BCLK# DREFCLK,DREFCLK#
1
2
3
4
5
6
7
8
PCB STACK UP 8L
LAYER 1 : TOP LAYER 2 : SGND1
A
LE9E BLOCK DIAGRAM
CPU CORE(ISL6266A)
01
14.318MHz
A
LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : IN3 LAYER 7 : SGND2 LAYER 8 : BOT
Size Document Number Custom Date: Rev
LE9E BLOCK DIAGRAM
Sheet 1
8
1B
of 45
Friday, March 27, 2009
7
1
2
3
4
5
6
5
4
3
2
1
Board Stack up Description
PCB Layers
Layer Layer Layer Layer Layer Layer Layer Layer 1 2 3 4 5 6 7 8
5 4 3 2
Quanta Computer Inc.
Size Document Number Custom Date: Rev
SYSTEM INFORMMATION
Sheet
1
1A
of 45
Friday, March 27, 2009
2
1
2
3
4
5
6
7
8
+3V L23 1 HI0805R800R_8 +3V 2 10U/6.3V/X5R_8 C370 0.1U/10V/X5R_4 C388 0.1U/10V/X5R_4 0.1U/10V/X5R_4 C355 C355 0.1U/10V/X5R_4 0.1U/10V/X5R_4 C387 0.1U/10V/X5R_4 C347 1 1 1 1 +CK_VDD_MAIN 0.1U/10V/X5R_4 C345 1 CLK_MCH_OE# NEW-CARD_CLK_REQ# Y3 CG_XIN 2 1 10U/6.3V/X5R_8 C381 0.1U/10V/X5R_4 C385 VDDCPU 1 1 2 1 CG_XOUT PCIE_LANREQ# R188 R222 R177 1 10K_4 1 10K_4 1 10K_4
03
A
2 2 2
2
2
2
2
A
L26 1 HI0805R800R_8
2
14.318MHZ+/- 10ppm C372 27P/50V/NPO_4
C369 27P/50V/NPO_4 R_DREFSSCLK R_DREFSSCLK# RP11 EV@4P2R-S-33 2 1 4 3
2
2
2
27M_NONSS (15) 27M_SS (15)
X1 X1 X1 Express Card X1
C
SATA - CD-ROM
SATA1 150MB
24.576Hz
PAGE 30
C
PAGE 19,20,21,22
SYSTEM POWER(ISL6237)
