ATtiny24技术资料

1Features•Utilizes the AVR ® RISC Architecture•AVR – High-performance and Low-power RISC Architecture–90 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General-purpose Working Registers –Up to 4 MIPS Throughput at 4 MHz •Nonvolatile Program Memory–2K Bytes of Flash Program Memory –Endurance: 1,000 Write/Erase Cycles–Programming Lock for Flash Program Data Security •Peripheral Features–Interrupt and Wake-up on Low-level Input–One 8-bit Timer/Counter with Separate Prescaler –On-chip Analog Comparator–Programmable Watchdog Timer with On-chip Oscillator–Built-in High-current LED Driver with Programmable Modulation •Special Microcontroller Features–Low-power Idle and Power-down Modes –External and Internal Interrupt Sources–Power-on Reset Circuit with Programmable Start-up Time –Internal Calibrated RC Oscillator •Power Consumption at 1 MHz, 2V , 25°C –Active: 3.0 mA –Idle Mode: 1.2 mA–Power-down Mode: <1 µA •I/O and Packages–11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver –28-lead PDIP , 32-lead TQFP , and 32-pad MLF •Operating Voltages–V CC : 1.8V - 5.5V for the ATtiny28V –V CC : 2.7V - 5.5V for the ATtiny28L •Speed Grades–0 - 1.2 MHz for the ATtiny28V –0 - 4 MHz For the ATtiny28LPin ConfigurationsPDIPTQFP/QFN/MLF8-bit Microcontroller with 2K Bytes of ATtiny28L ATtiny28V SummaryNote: This is a summary document. A complete documentis available on our Web site at .2ATtiny28L/V1062FS–AVR–07/06DescriptionThe ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly con-nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architec-ture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.Block DiagramFigure 1. The ATtiny28 Block DiagramThe ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops the CPU while allowing the timer/counter and interrupt system to continue functioning.The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The wake-up or inter-3ATtiny28L/V1062FS–AVR–07/06rupt on low-level input feature enables the ATtiny28 to be highly responsive to external events, still featuring the lowest power consumption while in the power-down modes.The device is manufactured using Atmel’s high-density, nonvolatile memory technology.By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. The ATtiny28 AVR is supported with a full suite of program and system development tools including: macro assemblers, pro-gram debugger/simulators, in-circuit emulators and evaluation kits.Pin DescriptionsVCC Supply voltage pin.GNDGround pin.Port A (PA3..PA0)Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED driver. At V CC = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port B (PB7..PB0)Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B pins that are externally pulled low will source current if the pull-ups are activated.Port B also serves the functions of various special features of the ATtiny28 as listed on page 27. If any of the special features are enabled, the pull-up(s) on the corresponding pin(s) is automatically disabled. The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.Port D (PD7..PD0)Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The port pins are tri-stated when a reset condition becomes active, even if the clock is not running.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.4ATtiny28L/V1062FS–AVR–07/06Notes:1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesshould never be written.2.Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on allbits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page$3F SREG ITHSVNZCpage 6$3E Reserved ...Reserved $20Reserved $1F Reserved $1E Reserved $1D Reserved $1C Reserved $1B PORTA ----PORTA3PORTA2PORTA1PORTA0page 32$1A PACR ----DDA3PA2HCDDA1DDA0page 32$19PINA ----PINA3-PINA1PINA0page 32$18Reserved $17Reserved $16PINB PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0page 32$15Reserved $14Reserved $13Reserved $12PORTD PORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0page 33$11DDRD DDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD0page 33$10PIND PIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND0page 33$0F Reserved $0E Reserved $0D Reserved $0C Reserved $0B Reserved $0A Reserved $09Reserved $08ACSR ACD -ACO ACI ACIE -ACIS1ACIS0page 44$07MCUCS PLUPB -SE SM WDRF -EXTRF PORF page 19$06ICR INT1INT0LLIE TOIE0ISC11ISC10ISC01ISC00page 22$05IFR INTF1INTF0-TOV0----page 23$04TCCR0FOV0--OOM01OOM00CS02CS01CS00page 35$03TCNT0Timer/Counter0 (8-bit)page 36$02MODCR ONTIM4ONTIM3ONTIM2ONTIM1 ONTIM0MCONF2MCONF1MCONF0page 43$01WDTCR ---WDTOEWDEWDP2WDP1WDP0page 37$00OSCCALOscillator Calibration Registerpage 95ATtiny28L/V1062FS–AVR–07/06Instruction Set SummaryMnemonicOperandsDescriptionOperationFlags# ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add Two RegistersRd ← Rd + Rr Z,C,N,V,H 1ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1SUB Rd, Rr Subtract Two Registers Rd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z,C,N,V,H 1AND Rd, Rr Logical AND RegistersRd ← Rd • Rr Z,N,V 1ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1OR Rd, Rr Logical OR RegistersRd ← Rd v Rr Z,N,V 1ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,H 1SBR Rd, K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1CBR Rd, K Clear Bit(s) in Register Rd ← Rd • (FFh - K)Z,N,V 1INC Rd Increment Rd ← Rd + 1Z,N,V 1DEC Rd DecrementRd ← Rd - 1 Z,N,V 1TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd Set Register Rd ← $FF None 1BRANCH INSTRUCTIONSRJMP k Relative JumpPC ← PC + k + 1None 2RCALL kRelative Subroutine Call PC ← PC + k + 1None 3RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACKI 4CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3None 1/2CP Rd, Rr CompareRd - Rr Z,N,V,C,H 1CPC Rd, Rr Compare with CarryRd - Rr - C Z,N,V,C,H 1CPI Rd, K Compare Register with Immediate Rd - KZ N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3None 1/2SBRS Rr, b Skip if Bit in Register is Set if (Rr(b) = 1) PC ← PC + 2 or 3None 1/2SBIC P, b Skip if Bit in I/O Register Cleared if (P(b) = 0) PC ← PC + 2 or 3None 1/2SBIS P, b Skip if Bit in I/O Register is Set if (P(b) = 1) PC ← PC + 2 or 3None 1/2BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1None 1/2BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1None 1/2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1/2BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1None 1/2BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1/2BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1/2BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1/2BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1/2BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1/2BRPL k Branch if Plusif (N = 0) then PC ← PC + k + 1None 1/2BRGE k Branch if Greater or Equal, Signed if (N ⊕ V = 0) then PC ← PC + k + 1None 1/2BRLT k Branch if Less than Zero, Signed if (N ⊕ V = 1) then PC ← PC + k + 1None 1/2BRHS k Branch if Half-carry Flag Set if (H = 1) then PC ← PC + k + 1None 1/2BRHC k Branch if Half-carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1/2BRTS k Branch if T-flag Set if (T = 1) then PC ← PC + k + 1None 1/2BRTC k Branch if T-flag Cleared if (T = 0) then PC ← PC + k + 1None 1/2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1/2BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1None 1/2BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1None 1/2BRIDkBranch if Interrupt Disabledif (I = 0) then PC ← PC + k + 1None1/26ATtiny28L/V1062FS–AVR–07/06DATA TRANSFER INSTRUCTIONSLD Rd, Z Load Register Indirect Rd ← (Z)None 2ST Z, Rr Store Register Indirect (Z) ← Rr None 2MOV Rd, Rr Move between Registers Rd ← Rr None 1LDI Rd, K Load Immediate Rd ←K None 1IN Rd, P In Port Rd ← P None 1OUT P, RrOut PortP ← Rr None 1LPMLoad Program MemoryR0 ← (Z)None3BIT AND BIT-TEST INSTRUCTIONS SBI P, b Set Bit in I/O Register I/O(P,b) ← 1None 2CBI P, b Clear Bit in I/O Register I/O(P,b) ←None 2LSL Rd Logical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V 1ROL Rd Rotate Left through Carry Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)Z,C,N,V 1ROR Rd Rotate Right through Carry Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0..6Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)None 1BSET s Flag Set SREG(s) ← 1SREG(s)1BCLR s Flag Clear SREG(s) ← 0SREG(s)1BST Rr, b Bit Store from Register to T T ← Rr(b)T 1BLD Rd, bBit Load from T to Register Rd(b) ← T None 1SEC Set Carry C ← 1C 1CLC Clear Carry C ←0C 1SEN Set Negative Flag N ← 1N 1CLN Clear Negative Flag N ← 0N 1SEZ Set Zero Flag Z ←1Z 1CLZ Clear Zero Flag Z ← 0Z1SEI Global Interrupt Enable I ← 1I 1CLI Global Interrupt Disable I ←I 1SES Set Signed Test FlagS ← 1S 1CLS Clear Signed Test Flag S ←0S 1SEV Set Two’s Complement OverflowV ←1V 1CLV Clear Two’s Complement Overflow V ← 0V 1SET Set T in SREG T ← 1T 1CLT Clear T in SREG T ← 0T 1SEH Set Half-carry Flag in SREG H ← 1H 1CLH Clear Half-carry Flag in SREG H ←H 1NOP No Operation None 1SLEEP Sleep(see specific descr. for Sleep function)None 1WDRWatchdog Reset(see specific descr. for WDR/timer)None1Instruction Set Summary (Continued)MnemonicOperandsDescriptionOperationFlags# Clocks7ATtiny28L/V1062FS–AVR–07/06Notes:1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities.2.Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-tive).Also Halide free and fully Green.Ordering InformationSpeed (MHz)Power Supply (Volts)Ordering Code Package (1)Operation Range 42.7 - 5.5A Ttiny28L-4AC A Ttiny28L-4PC A Ttiny28L-4MC32A 28P332M1-A Commercial (0°C to 70°C)A Ttiny28L-4AI A Ttiny28L-4AU (2)A Ttiny28L-4PI A Ttiny28L-4PU (2)A Ttiny28L-4MI A Ttiny28L-4MU (2)32A 32A 28P328P332M1-A 32M1-A Industrial (-40°C to 85°C)1.21.8 - 5.5A Ttiny28V-1AC A Ttiny28V-1PC A Ttiny28V-1MC32A 28P332M1-A Commercial (0°C to 70°C)A Ttiny28V-1AI A Ttiny28V-1AU (2)A Ttiny28V-1PI A Ttiny28V-1PU (2)A Ttiny28V-1MI A Ttiny28V-1MU (2)32A 32A 28P328P332M1-A 32M1-AIndustrial (-40°C to 85°C)Package Type32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)28P328-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)32M1-A32-pad, 5x5x1.0 body, Lead Pitch 0.50mm, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)8ATtiny28L/V1062FS–AVR–07/06Packaging Information32A9ATtiny28L/V1062FS–AVR–07/0628P310ATtiny28L/V1062FS–AVR–07/0632M1-A11ATtiny28L/V1062FS–AVR–07/06ErrataAll revisionsNo known errata.12ATtiny28L/V1062FS–AVR–07/06Datasheet Revision HistoryPlease note that the referring page numbers in this section are referred to this docu-ment. The referring revision in this section are referring to the document revision.Rev – 01/06G 1.Updated chapter layout.2.Updated “Ordering Information” on page 7.Rev – 01/06G1.Updated description for “Port A” on page 25.2.Added note 6 in “DC Characteristics” on page 54.3.Updated “Ordering Information” on page 7.4.Added “Errata” on page 11.Rev – 03/05F1.Updated “Electrical Characteristics” on page 54.2.MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame PackageQFN/MLF”.3.Updated “Ordering Information” on page 7.1062FS–AVR–07/06© 2006 Atmel Corporation . All rights reserved. ATMEL ®, logo and combinations thereof, Everywhere You Are ®, AVR ®, AVR Studio ®, and oth-ers, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of oth-ers.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABIL ITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBIL ITY OF SUCH DAMAGES. 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Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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Atmel芯片新命名型号对照表ATTINY28L ATMEL ATMLU701 DIP ATTINY26L ATMEL ATMLU702 DIP ATTINY26 ATMEL ATMLU703 DIP ATTINY24 ATMEL ATMLU704 DIP ATTINY2313V ATMEL ATMLU705 DIP ATTINY2313 ATMEL ATMLU706 DIP ATTINY15L ATMEL ATMLU707 DIP ATTINY13V ATMEL ATMLU708 DIP ATTINY13 ATMEL ATMLU709 DIP ATTINY11L ATMEL ATMLU710 DIP ATMEGA8L ATMEL ATMLU711 DIP ATMEGA88V ATMEL ATMLU712 DIP ATMEGA88 ATMEL ATMLU713 DIP ATMEGA8535L ATMEL ATMLU714 DIP ATMEGA8535 ATMEL ATMLU715 DIP ATMEGA8515L ATMEL ATMLU716 DIP ATMEGA8515 ATMEL ATMLU717 DIP ATMEGA8 ATMEL ATMLU718 DIP ATMEGA64L ATMEL ATMLU719 DIP ATMEGA64 ATMEL ATMLU720 DIP ATMEGA640V ATMEL ATMLU721 DIP ATMEGA48V ATMEL ATMLU722 DIP ATMEGA48 ATMEL ATMLU723 DIP ATMEGA32L ATMEL ATMLU724 DIP ATMEGA325V ATMEL ATMLU725 DIP ATMEGA32 ATMEL ATMLU726 DIP ATMEGA16L ATMEL ATMLU727 DIP ATMEGA169V ATMEL ATMLU728 DIP ATMEGA169PV ATMEL ATMLU729 DIP ATMEGA169P ATMEL ATMLU730 DIP ATMEGA168V ATMEL ATMLU731 DIP ATMEGA168 ATMEL ATMLU732 DIP ATMEGA162V ATMEL ATMLU733 DIP ATMEGA162 ATMEL ATMLU734 DIP ATMEGA16 ATMEL ATMLU735 DIP ATMEGA128L ATMEL ATMLU736 DIP ATMEGA128 ATMEL ATMLU737 DIP ATMEGA1280V ATMEL ATMLU738 DIP ATJTAGICE2 ATMEL ATMLU739 DIPATF20V8B ATMEL ATMLU740 DIPATF16V8BQL ATMEL ATMLU741 DIP ATF16V8B ATMEL ATMLU742 DIPATF1508AS ATMEL ATMLU743 DIP ATF1502AS ATMEL ATMLU744 DIP ATAVRISP2 ATMEL ATMLU745 DIP ATAVRDRAGON ATMEL ATMLU746 DIP AT93C66A ATMEL ATMLU747 DIPAT93C56A ATMEL ATMLU748 DIPAT93C46DN ATMEL ATMLU749 DIPAT93C46DH ATMEL ATMLU750 DIPAT93C46 ATMEL ATMLU751 DIPAT91SAM ATMEL ATMLU752 DIPAT91SAM9263 ATMEL ATMLU801 DIP AT91SAM9261S ATMEL ATMLU802 DIP AT91SAM9261 ATMEL ATMLU803 DIP AT91SAM9260 ATMEL ATMLU804 DIP AT91SAM7X ATMEL ATMLU805 DIPAT91SAM7X256 ATMEL ATMLU806 DIP AT91SAM7SE32 ATMEL ATMLU807 DIP AT91SAM7S64 ATMEL ATMLU808 DIP AT91SAM7S32 ATMEL ATMLU809 DIP AT91SAM7S321 ATMEL ATMLU810 DIP AT91SAM7S256 ATMEL ATMLU811 DIP AT91RM9200 ATMEL ATMLU812 DIP AT91M55800A ATMEL ATMLU813 DIP AT91M40800 ATMEL ATMLU814 DIPAT90CAN32 ATMEL ATMLU815 DIPAT90CAN128 ATMEL ATMLU816 DIP AT89S8253 ATMEL ATMLU817 DIPAT89S58 ATMEL ATMLU818 DIPAT89S54 ATMEL ATMLU819 DIPAT89S52 ATMEL ATMLU820 DIPAT89S51 ATMEL ATMLU821 DIPAT89LV51 ATMEL ATMLU822 DIPAT89LS52 ATMEL ATMLU823 DIPAT89C55WD ATMEL ATMLU824 DIPAT89C52 ATMEL ATMLU825 DIPAT89C51RD2 ATMEL ATMLU826 DIP AT89C51RC2 ATMEL ATMLU827 DIP AT89C51RC ATMEL ATMLU828 DIPAT89C51RC2 ATMEL ATMLU829 DIPAT89C51ED2 ATMEL ATMLU831 DIPAT89C51CC01UA ATMEL ATMLU832 DIP AT89C51CC01CA ATMEL ATMLU833 DIP AT89C51AU2 ATMEL ATMLU834 DIPAT89C5131A ATMEL ATMLU835 DIPAT89C51 ATMEL ATMLU836 DIPAT89C4051 ATMEL ATMLU837 DIPAT89C2051 ATMEL ATMLU838 DIPAT88SC153 ATMEL ATMLU839 DIPAT88SC0104C ATMEL ATMLU840 DIP AT49BV512 ATMEL ATMLU841 DIPAT49BV322DT ATMEL ATMLU842 DIP AT49BV040B ATMEL ATMLU843 DIPAT47BV163A ATMEL ATMLU844 DIPAT45DB642DU ATMEL ATMLU845 DIP AT45DB321DU ATMEL ATMLU846 DIP AT45DB321D ATMEL ATMLU847 DIPAT45DB161DU ATMEL ATMLU848 DIP AT45DB161D ATMEL ATMLU849 DIPAT45DB081D ATMEL ATMLU850 DIPAT45DB041D ATMEL ATMLU851 DIPAT45DB021B ATMEL ATMLU852 DIPAT29LV512 ATMEL ATMLU901 DIPAT29LV040A ATMEL ATMLU902 DIPAT29LV020 ATMEL ATMLU903 DIPAT29C040A ATMEL ATMLU904 DIPAT29C020 ATMEL ATMLU905 DIPAT29C010A ATMEL ATMLU906 DIPAT28C64B ATMEL ATMLU907 DIPAT28C256 ATMEL ATMLU908 DIPAT28BV256 ATMEL ATMLU909 DIPAT27C512R ATMEL ATMLU910 DIPAT27C256R ATMEL ATMLH701 SOPAT27C040 ATMEL ATMLH702 SOPAT27C010 ATMEL ATMLH703 SOPAT27BV256 ATMEL ATMLH704 SOPAT26DF321 ATMEL ATMLH705 SOPAT26DF161 ATMEL ATMLH706 SOPAT26DF081A ATMEL ATMLH707 SOPAT25F512AN ATMEL ATMLH708 SOPAT25F1024AN ATMEL ATMLH709 SOPAT25256AN ATMEL ATMLH711 SOP AT25128A ATMEL ATMLH712 SOPAT24C64CN ATMEL ATMLH713 SOP AT24C64AN ATMEL ATMLH714 SOP AT24C64A ATMEL ATMLH715 SOP AT24C512N ATMEL ATMLH716 SOP AT24C512B ATMEL ATMLH717 SOP AT24C512BN ATMEL ATMLH718 SOP AT24C512 ATMEL ATMLH719 SOPAT24C32CN ATMEL ATMLH720 SOP AT24C32AN ATMEL ATMLH721 SOP AT24C32A ATMEL ATMLH722 SOP AT24C256N ATMEL ATMLH723 SOP AT24C256B ATMEL ATMLH724 SOP AT24C256BN ATMEL ATMLH725 SOP AT24C256B ATMEL ATMLH726 SOP AT24C16BN ATMEL ATMLH727 SOP AT24C16AN ATMEL ATMLH728 SOP AT24C16A ATMEL ATMLH729 SOP AT24C128N ATMEL ATMLH730 SOP AT24C128 ATMEL ATMLH731 SOPAT24C08AN ATMEL ATMLH732 SOP AT24C08A ATMEL ATMLH733 SOP AT24C04N ATMEL ATMLH734 SOP AT24C04BN ATMEL ATMLH735 SOP AT24C04 ATMEL ATMLH736 SOPAT24C02B ATMEL ATMLH737 SOP AT24C02BN ATMEL ATMLH738 SOP AT24C02B ATMEL ATMLH739 SOP AT24C01B ATMEL ATMLH740 SOP AT24C01BN ATMEL ATMLH741 SOP ATTINY28L ATMEL ATMLU701 SOP ATTINY26L ATMEL ATMLU702 SOP ATTINY26 ATMEL ATMLU703 SOP ATTINY24 ATMEL ATMLU704 SOP ATTINY2313V ATMEL ATMLU705 SOP ATTINY2313 ATMEL ATMLU706 SOP ATTINY15L ATMEL ATMLU707 SOP ATTINY13V ATMEL ATMLU708 SOP ATTINY13 ATMEL ATMLU709 SOP ATTINY11L ATMEL ATMLU710 SOPATMEGA88V ATMEL ATMLU712 SOP ATMEGA88 ATMEL ATMLU713 SOP ATMEGA8535L ATMEL ATMLU714 SOP ATMEGA8535 ATMEL ATMLU715 SOP ATMEGA8515L ATMEL ATMLU716 SOP ATMEGA8515 ATMEL ATMLU717 SOP ATMEGA8 ATMEL ATMLU718 SOP ATMEGA64L ATMEL ATMLU719 SOP ATMEGA64 ATMEL ATMLU720 SOP ATMEGA640V ATMEL ATMLU721 SOP ATMEGA48V ATMEL ATMLU722 SOP ATMEGA48 ATMEL ATMLU723 SOP ATMEGA32L ATMEL ATMLU724 SOP ATMEGA325V ATMEL ATMLU725 SOP ATMEGA32 ATMEL ATMLU726 SOP ATMEGA16L ATMEL ATMLU727 SOP ATMEGA169V ATMEL ATMLU728 SOP ATMEGA169PV ATMEL ATMLU729 SOP ATMEGA169P ATMEL ATMLU730 SOP ATMEGA168V ATMEL ATMLU731 SOP ATMEGA168 ATMEL ATMLU732 SOP ATMEGA162V ATMEL ATMLU733 SOP ATMEGA162 ATMEL ATMLU734 SOP ATMEGA16 ATMEL ATMLU735 SOP ATMEGA128L ATMEL ATMLU736 SOP ATMEGA128 ATMEL ATMLU737 SOP ATMEGA1280V ATMEL ATMLU738 SOP ATJTAGICE2 ATMEL ATMLU739 SOP ATF20V8B ATMEL ATMLU740 SOPATF16V8BQL ATMEL ATMLU741 SOP ATF16V8B ATMEL ATMLU742 SOPATF1508AS ATMEL ATMLU743 SOP ATF1502AS ATMEL ATMLU744 SOP ATAVRISP2 ATMEL ATMLU745 SOP ATAVRDRAGON ATMEL ATMLU746 SOP AT93C66A ATMEL ATMLU747 SOPAT93C56A ATMEL ATMLU748 SOPAT93C46DN ATMEL ATMLU749 SOPAT93C46DH ATMEL ATMLU750 SOPAT93C46 ATMEL ATMLU751 SOPAT91SAM ATMEL ATMLU752 SOPAT91SAM9261S ATMEL ATMLU802 SOP AT91SAM9261 ATMEL ATMLU803 SOP AT91SAM9260 ATMEL ATMLU804 SOP AT91SAM7X ATMEL ATMLU805 SOPAT91SAM7X256 ATMEL ATMLU806 SOP AT91SAM7SE32 ATMEL ATMLU807 SOP AT91SAM7S64 ATMEL ATMLU808 SOP AT91SAM7S32 ATMEL ATMLU809 SOP AT91SAM7S321 ATMEL ATMLU810 SOP AT91SAM7S256 ATMEL ATMLU811 SOP AT91RM9200 ATMEL ATMLU812 SOPAT91M55800A ATMEL ATMLU813 SOP AT91M40800 ATMEL ATMLU814 SOPAT90CAN32 ATMEL ATMLU815 SOPAT90CAN128 ATMEL ATMLU816 SOPAT89S8253 ATMEL ATMLU817 SOPAT89S58 ATMEL ATMLU818 SOPAT89S54 ATMEL ATMLU819 SOPAT89S52 ATMEL ATMLU820 SOPAT89S51 ATMEL ATMLU821 SOPAT89LV51 ATMEL ATMLU822 SOPAT89LS52 ATMEL ATMLU823 SOPAT89C55WD ATMEL ATMLU824 SOPAT89C52 ATMEL ATMLU825 SOPAT89C51RD2 ATMEL ATMLU826 SOPAT89C51RC2 ATMEL ATMLU827 SOPAT89C51RC ATMEL ATMLU828 SOPAT89C51RC2 ATMEL ATMLU829 SOPAT89C51RB2 ATMEL ATMLU830 SOPAT89C51ED2 ATMEL ATMLU831 SOPAT89C51CC01UA ATMEL ATMLU832 SOP AT89C51CC01CA ATMEL ATMLU833 SOP AT89C51AU2 ATMEL ATMLU834 SOPAT89C5131A ATMEL ATMLU835 SOPAT89C51 ATMEL ATMLU836 SOPAT89C4051 ATMEL ATMLU837 SOPAT89C2051 ATMEL ATMLU838 SOPAT88SC153 ATMEL ATMLU839 SOPAT88SC0104C ATMEL ATMLU840 SOP AT49BV512 ATMEL ATMLU841 SOPAT49BV322DT ATMEL ATMLU842 SOPAT47BV163A ATMEL ATMLU844 SOP AT45DB642DU ATMEL ATMLU845 SOP AT45DB321DU ATMEL ATMLU846 SOP AT45DB321D ATMEL ATMLU847 SOP AT45DB161DU ATMEL ATMLU848 SOP AT45DB161D ATMEL ATMLU849 SOP AT45DB081D ATMEL ATMLU850 SOP AT45DB041D ATMEL ATMLU851 SOP AT45DB021B ATMEL ATMLU852 SOP AT29LV512 ATMEL ATMLU901 SOP AT29LV040A ATMEL ATMLU902 SOP AT29LV020 ATMEL ATMLU903 SOP AT29C040A ATMEL ATMLU904 SOP AT29C020 ATMEL ATMLU905 SOPAT29C010A ATMEL ATMLU906 SOP AT28C64B ATMEL ATMLU907 SOPAT28C256 ATMEL ATMLU908 SOPAT28BV256 ATMEL ATMLU909 SOP AT27C512R ATMEL ATMLU910 SOP AT27C256R ATMEL ATMLH701 DIPAT27C040 ATMEL ATMLH702 DIPAT27C010 ATMEL ATMLH703 DIPAT27BV256 ATMEL ATMLH704 DIPAT26DF321 ATMEL ATMLH705 DIPAT26DF161 ATMEL ATMLH706 DIPAT26DF081A ATMEL ATMLH707 DIP AT25F512AN ATMEL ATMLH708 DIP AT25F1024AN ATMEL ATMLH709 DIP AT25DF041A ATMEL ATMLH710 DIP AT25256AN ATMEL ATMLH711 DIPAT25128A ATMEL ATMLH712 DIPAT24C64CN ATMEL ATMLH713 DIPAT24C64AN ATMEL ATMLH714 DIPAT24C64A ATMEL ATMLH715 DIPAT24C512N ATMEL ATMLH716 DIPAT24C512B ATMEL ATMLH717 DIPAT24C512BN ATMEL ATMLH718 DIP AT24C512 ATMEL ATMLH719 DIPAT24C32CN ATMEL ATMLH720 DIPAT24C32AN ATMEL ATMLH721 DIPAT24C32A ATMEL ATMLH722 DIPAT24C256B ATMEL ATMLH724 DIP AT24C256BN ATMEL ATMLH725 DIP AT24C256B ATMEL ATMLH726 DIP AT24C16BN ATMEL ATMLH727 DIP AT24C16AN ATMEL ATMLH728 DIP AT24C16A ATMEL ATMLH729 DIP AT24C128N ATMEL ATMLH730 DIP AT24C128 ATMEL ATMLH731 DIP AT24C08AN ATMEL ATMLH732 DIP AT24C08A ATMEL ATMLH733 DIP AT24C04N ATMEL ATMLH734 DIP AT24C04BN ATMEL ATMLH735 DIP AT24C04 ATMEL ATMLH736 DIPAT24C02B ATMEL ATMLH737 DIP AT24C02BN ATMEL ATMLH738 DIP AT24C02B ATMEL ATMLH739 DIP AT24C01B ATMEL ATMLH740 DIP AT24C01BN ATMEL ATMLH741 DIP 不全，不过我可是第一个回答的啊。

BDTIC /ATMELAppendix B - ATtiny24V/ATtiny44V/ATtiny84VAutomotive Specification at 1.8VThis document contains information specific to devices operating at voltage between1.8V and 3.6V. Only deviations with standard operating characteristics are covered inthis appendix, all other information can be found in the complete Automotivedatasheet. The complete ATtiny24/ATtiny44/ATtiny84 automotive datasheet can be8-bit found on Microcontrollerwith 2/4/8KBytes In-SystemProgrammableATtiny24VATtiny44V27819A–AVR–01/09ATtiny24V/ATtiny44V/ATtiny84V [Preliminary]1.Electrical Characteristics1.1Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ParametersValue Unit Operating temperature –40 to +85°C Storage temperature–65 to +175°C Voltage on any pin except RESET with respect to ground –0.5 to V CC + 0.5V Maximum operating voltage 6.0V DC current per I/O pin 30.0mA DC current V CC and GND pins200.0mA1.2DC CharacteristicsT A = –40°C to +85°C, V CC = 1.8V to 3.6V (unless otherwise noted)Symbol ParametersConditionMin.Typ.Max.Unit V IL Input low voltage, except XT AL1 andRESET pinV CC = 1.8V to 3.6V–0.5+0.2V CC (1)V V IH Input high voltage, except XTAL1 and RESET pinsV CC = 1.8V to 3.6V 0.7V CC (2)V CC + 0.5V V IL1Input low voltage, XT AL1 pin V CC = 1.8V to 3.6V –0.5+0.2V CC (1)V V IH1Input high voltage, XT AL1 pin V CC = 1.8V to 3.6V 0.9V CC (2)V CC + 0.5V V IL2Input low voltage, RESET pin V CC = 1.8V to 3.6V –0.5+0.2V CC (1)V V IH2Input high voltage, RESET pin V CC = 1.8V to 3.6V 0.9V CC (2)V CC + 0.5V V OL Output low voltage (3), I/O pin except RESET I OL = 2mA, V CC = 1.8V 0.2V V OHOutput high voltage (4), I/O pin except RESET I OH = –2mA, V CC = 1.8V 1.2V I CCPower supply currentActive 4MHz, V CC = 3V 0.8 2.5mA Idle 4MHz, V CC = 3V 0.20.5mA Power-down modeWDT disabled, V CC = 3V WDT enabled, V CC = 3V 0.242430µA V ACIO Analog comparator Input offset voltage V CC = 2.7V V in = V CC /2<1040mV I ACLK Analog comparator Input leakage currentV CC = 2.7V V in = V CC /2–50+50nANotes:1.“Max” means the highest value where the pin is guaranteed to be read as low2.“Min” means the lowest value where the pin is guaranteed to be read as high3.Although each I/O port can sink more than the test conditions (2mA at VCC = 1.8V) under steady state conditions (nontran-sient), the following must be observed: (1) The sum of all IOL, for all ports, should not exceed 50mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.4.Although each I/O port can source more than the test conditions (0.5mA at VCC = 1.8V) under steady state conditions(nontransient), the following must be observed: (1) The sum of all IOL, for ports B0 to B5, should not exceed 50mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.37819A–AVR–01/09ATtiny24V/ATtiny44V/ATtiny84V [Preliminary]1.3Maximum Speed versus V CCMaximum frequency is dependent on V CC. As shown in Figure 1-1, the Maximum Frequency vs.V CC curve is linear between 1.8V < V CC < 3.6V.Figure 1-1.Maximum Frequency versus V CC1.4Clock CharacterizationsTable 1-1.Calibration Accuracy of Internal RC OscillatorFrequencyV CC Temperature Accuracy User Calibration7.3 MHz to 8.1 MHz1.8V to 3.6V–40°C to +85°C±25%47819A–AVR–01/09ATtiny24V/ATtiny44V/ATtiny84V [Preliminary]1.5ADC CharacteristicsT A = –40°C to +85°C, V CC = 1.8V to 3.6V (unless otherwise noted)SymbolParameters Test Conditions Min.Typ.Max.Unit ResolutionSingle ended conversion 10Bits Absolute accuracy (Including INL, DNL, quantization error, gain and offset error)V CC = 1.8V , V Ref = 1.8V , ADC clock =200kHz 2 4.0LSB V CC = 1.8V , V Ref = 1.8V , ADC clock =200kHz Noise Reduction Mode 2 4.0LSB Integral Non-Linearity (INL)V CC = 1.8V , V Ref = 1.8V , ADC clock =200kHz 0.5 1.5LSB Differential Non-Linearity (DNL)V CC = 1.8V , V Ref = 1.8V , ADC clock =200kHz 0.20.7LSB Gain error V CC = 1.8V , V Ref = 1.8V , ADC clock =200kHz –7.0–3.0+5.0LSB Offset errorV CC = 1.8V , V Ref = 1.8V , ADC clock =200kHz–3.5+1.5+3.5LSB V REFReference voltage1.8AV CC V1.6ADC CharacteristicsT A = –40°C to +85°C, V CC = 1.8V to 3.6V (unless otherwise noted)SymbolParameters Test ConditionsMin.Typ.Max.Unit ResolutionDifferential conversion, gain = 1x BIPOLAR mode only8Bits Absolute accuracy (Including INL, DNL, quantization error, gain and offset error)Gain = 1x, V CC = 1.8V , V Ref =1.3V , ADC clock =125kHz 1.65.0LSBIntegral Non-Linearity (INL)Gain = 1x, V CC = 1.8V , V Ref = 1.3V ,ADC clock = 125kHz 0.7 2.5LSBDifferential Non-Linearity (DNL)Gain = 1x, V CC = 1.8V ,V Ref = 1.3V ,ADC clock = 125kHz 0.3 1.0LSBGain Error Gain = 1x, V CC = 1.8V ,V Ref = 1.3V ,ADC clock = 125kHz –7.0+1.50+7.0LSBOffset ErrorGain = 1x, V CC = 1.8V .V Ref = 1.3V ,ADC clock = 125kHz–4.00.0+4.0LSB V REFReference Voltage1.30AVCC – 0.5V57819A–AVR–01/09ATtiny24V/ATtiny44V/ATtiny84V [Preliminary]3.Package Information2.Ordering InformationPower Supply Speed (MHz)ISP Flash Ordering Code Package Operation Range 1.8V to 3.6V 4-82KB A Ttiny24V-15SST TU Automotive (–40°C to +85°C)1.8V to 3.6V 4-82KB A Ttiny24V-15MT PN Automotive (–40°C to +85°C)1.8V to 3.6V 4-84KB A Ttiny44V-15SST TU Automotive (–40°C to +85°C)1.8V to 3.6V 4-84KB A Ttiny44V-15MT PN Automotive (–40°C to +85°C)1.8V to 3.6V4-88KBA Ttiny84V-15MTPNAutomotive (–40°C to +85°C)Table 3-1.Package TypesPackage TypeDescriptionTU TU 14-Lead, 0.150” Body WidthPlastic Gull Wing Small Outline Package (SOIC)PNPN 32-Lead, 5.0 x 5.0 mm Body, 0.50 mm Pitch Quad Flat No Lead ackage (QFN)67819A–AVR–01/09ATtiny24V/ATtiny44V/ATtiny84V [Preliminary]77819A–AVR–01/09ATtiny24V/ATtiny44V/ATtiny84V [Preliminary]7819A–AVR–01/09HeadquartersInternationalAtmel Corporation 2325 Orchard Parkway San Jose, CA 95131USATel: 1(408) 441-0311Fax: 1(408) 487-2600Atmel AsiaUnit 1-5 & 16, 19/FBEA Tower, Millennium City 5418 Kwun Tong Road Kwun Tong, Kowloon Hong KongTel: (852) 2245-6100Fax: (852) 2722-1369Atmel Europe Le Krebs8, Rue Jean-Pierre Timbaud BP 30978054Saint-Quentin-en-Yvelines Cedex FranceTel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11Atmel Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Product ContactWeb SiteTechnical Support *************Sales Contact/contactsLiterature Requests /literatureDisclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL ’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL ’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.© 2009 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, AVR ® and others are registered trademarks or trade-marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.。

ATTINY24A-SSU中文资料FeaturesHigh Performance, Low Power AVR? 8-Bit MicrocontrollerAdvanced RISC Architecture–120 Powerful Instructions –Most Single Clock Cycle Execution–32 x 8 General Purpose Working Registers–Fully Static OperationHigh Endurance, Non-Volatile Memory Segments–2K/4K Bytes of In-System, Self-Programmable Flash Program MemoryEndurance: 10,000 Write/Erase Cycles–128/256 Bytes of In-System Programmable EEPROMEndurance: 100,000 Write/Erase Cycles–128/256 Bytes of Internal SRAM–Data retention: 20 years at 85°C / 100 years at 25°C–Programming Lock for Self-Programming Flash & EEPROM Data Security ?Peripheral Features–One 8-Bit and One 16-Bit Timer/Counter with Two PWM Channels, Each–10-bit ADC8 Single-Ended Channels12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)–Programmable Watchdog Timer with Separate On-chip Oscillator–On-Chip Analog Comparator–Universal Serial InterfaceSpecial Microcontroller Features–debugWIRE On-chip Debug System–In-System Programmable via SPI Port–Internal and External Interrupt SourcesPin Change Interrupt on 12 Pins–Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes –Enhanced Power-on Reset Circuit–Programmable Brown-Out Detection Circuit with Software Disable Function –Internal Calibrated Oscillator–On-Chip Temperature SensorI/O and Packages–Available in 20-Pin QFN/MLF & 14-Pin SOIC and PDIP–Twelve Programmable I/O LinesOperating Voltage:–1.8 – 5.5VSpeed Grade:–0 –********– 5.5V–0 –*********– 5.5V–0 –*********– 5.5VIndustrial Temperature Range: -40°C to +85°CLow Power Consumption–Active Mode:210 μA at 1.8V and 1MHz–Idle Mode:33 μA at 1.8V and 1MHz–Power-Down Mode:0.1 μA at 1.8V and 25°C 8-bit Microcontrollerwith 2K/4KBytes In-System ProgrammableATtiny24A (Preliminary)ATtiny44A28183AS–AVR–12/08ATtiny24A/44A1.Pin ConfigurationsFigure 1-1.Pinout of ATtiny24A/44A1.1Pin Descriptions1.1.1VCCSupply voltage.1.1.2GNDGround.1.1.3Port B (PB3...PB0)Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source RES ET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.1234567141312111098VCC(PCINT 8/XT AL1/CLKI) PB0(PCINT9/XTAL2) PB1(PCINT11/RE S ET/dW) PB 3(PCINT10/INT0/OC0A/CKOUT) PB2(PCINT7/ICP/OC0B/ADC7) PA7(PCINT6/OC1A/S DA/MO S I/DI/ADC6) PA6GNDPA0 (ADC0/AREF/PCINT0)PA1 (ADC1/AIN0/PCINT1)PA2 (ADC2/AIN1/PCINT2)PA 3 (ADC 3/T0/PCINT 3)PA4 (ADC4/U S CK/S CL/T1/PCINT4)P A5 (ADC5/DO/MI S O/OC1B/PCINT5)PDIP/S OIC12345QFN/MLF15141312112019181716678910NOTEBottom p a d s ho u ld b e s oldered to gro u nd.DNC: Do Not ConnectD N C D N C G N D V C C D N CPA7 (PCINT7/ICP/OC0B/ADC7)PB2 (PCINT10/INT0/OC0A/CKOUT)PB 3 (PCINT11/RE S ET/dW)PB1 (PCINT9/XTAL2)PB0 (PCINT 8/XTAL1/CLKI)P A 5D N C D N C D N C P A 6Pin 16: P A6 (PCINT6/OC1A/S DA/MO S I/DI/ADC6)Pin 20: P A5 (ADC5/DO/MI S O/OC1B/PCINT5)(ADC4/U S CK/S CL/T1/PCINT4) PA4(ADC 3/T0/PCINT 3) PA 3(ADC2/AIN1/PCINT2) PA2(ADC1/AIN0/PCINT1) PA1(ADC0/AREF/PCINT0) PA038183AS–AVR–12/08ATtiny24A/44APort B also serves the functions of various special features of the ATtiny24A/44A as listed in Section 10.2 “Alternate Port Functions” on page 57.Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The min-imum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to generate a reset.The reset pin can also be used as a (weak) I/O pin.1.1.5Port A (PA7...PA0)Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,even if the clock is not running.Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter,SPI and pin change interrupt as described in “Alternate Port Functions” on page 57.48183AS–AVR–12/08ATtiny24A/44A2.OverviewATtiny24A/44A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A achieves throughputs approaching 1 MIPS per MHz allowing thesystem designer to optimize power consumption versus processing speed.Figure 2-1.Block DiagramThe AVR core combines a rich instruction set with 32 general purpose working registers. All 32registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con-ventional CISC microcontrollers.58183AS–AVR–12/08ATtiny24A/44AThe ATtiny24A/44A provides the following features: 2K/4K byte of In-System Programmable Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/coun-ter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software select-able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O mod-ules except the ADC. In Power-down mode registers keep their contents and all chip functionsare disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption.The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core.The ATtiny24A/44A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.68183AS–AVR–12/08ATtiny24A/44A3.About3.1ResourcesA comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at /doc/fb6038e319e8b8f67c1cb9ea.html/avr.3.2Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is includedbefore compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-tation for more details.For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” co mbined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.3.3Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.3.4DisclaimerTypical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized.78183AS–AVR–12/08ATtiny24A/44A4.Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page0x3F (0x5F)SREG I T H S V N Z C Page 80x3E (0x5E)SPH ––––––SP9SP8Page 100x3D (0x5D)SPL SP7SP6SP5SP4SP3SP2SP1SP0Page 100x3C (0x5C)OCR0B Timer/Counter0 – Output Compare Register B Page 830x3B (0x5B)GIMSK –INT0PCIE1PCIE0––––Page 490x3A (0x5A GIFR –INTF0PCIF1PCIF0––––Page 500x39 (0x59)TIMSK0–––––OCIE0B OCIE0A TOIE0Page 830x38 (0x58)TIFR0––––OCF0BOCF0A TOV0Page 830x37 (0x57)SPMCSR ––RSIG CTPB RFLB PGWRTPGERS SPMEN Page 1560x36 (0x56)OCR0A Timer/Counter0 – Output Compare Register A Page 820x35 (0x55)MCUCR BODS PUD SE SM1SM0BODSE ISC01ISC00Pages 35, 49, and 65 0x34 (0x54)MCUSR ––––WDRF BORF EXTRF PORF Page 430x33 (0x53)TCCR0B FOC0A FOC0B ––WGM02CS02CS01CS00Page 810x32 (0x52)TCNT0Timer/Counter0Page 820x31(0x51)OSCCAL CAL7CAL6CAL5CAL4CAL3CAL2CAL1CAL0Page290x30 (0x50)TCCR0A COM0A1COM0A0COM0B1COM0B0–WGM01WGM00Page 780x2F (0x4F)TCCR1A COM1A1COM1A0COM1B1COM1B0–WGM11WGM10Page 1060x2E (0x4E)TCCR1B ICNC1ICES1–WGM13WGM12CS12CS11CS10Page 1080x2D (0x4D)TCNT1H Timer/Counter1 –Counter Register High Byte Page 1100x2C (0x4C)TCNT1L Timer/Counter1 –Counter Register Low Byte Page 1100x2B (0x4B)OCR1AH Timer/Counter1 – Compare Register A High Byte Page 1100x2A (0x4A)OCR1AL Timer/Counter1 – Compare Register A Low Byte Page 1100x29 (0x49)OCR1BH Timer/Counter1 –Compare Register B High Byte Page 1100x28 (0x48)OCR1BL Timer/Counter1 – Compare Register B Low BytePage 1100x27 (0x47)DWDR DWDR[7:0]Page 1510x26 (0x46)CLKPR CLKPCE–––CLKPS3CLKPS2CLKPS1CLKPS0Page 300x25 (0x45)ICR1H Timer/Counter1 - Input CaptureRegister High Byte Page 1110x24 (0x44)ICR1L Timer/Counter1 - Input Capture Register Low BytePage 1110x23 (0x43)GTCCR TSM ––––––PSR10Page 1140x22 (0x42)TCCR1C FOC1A FOC1B ––––––Page 1090x21 (0x41)WDTCSR WDIF WDIE WDP3WDCE WDE WDP2WDP1WDP0Page 430x20 (0x40)PCMSK1––––PCINT11 PCINT10PCINT9PCINT8Page 500x1F (0x3F)Reserved ––––––––0x1E (0x3E)EEARL EEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0Page 200x1D (0x3D)EEDR EEPROM Data RegisterPage 210x1C (0x3C)EECR ––EEPM1EEPM0EERIE EEMPE EEPE EERE Page 210x1B (0x3B)PORTA PORTA7PORTA6PORTA5PORTA4PORTA3PORTA2PORTA1PORTA0 Page 650x1A (0x3A)DDRA DDA7DDA6DDA5DDA4DDA3DDA2DDA1DDA0Page 650x19 (0x39)PINAPINA7PINA6PINA5PINA4PINA3PINA2PINA1PINA0Page 660x18 (0x38)PORTB ––––PORTB3PORTB2PORTB1PORTB0Page 660x17 (0x37)DDRB ––––DDB3DDB2DDB1DDB0Page 660x16 (0x36)PINB ––––PINB3PINB2PINB1PINB0Page 660x15 (0x35)GPIOR2General Purpose I/O Register 2Page 220x14 (0x34)GPIOR1General Purpose I/O Register 1Page 220x13 (0x33)GPIOR0General Purpose I/O Register 0 Page 220x12 (0x32)PCMSK0PCINT7PCINT6PCINT5PCINT4PCINT3PCINT2PCINT1PCINT0Page 510x11 (0x31))Reserved –0x10 (0x30)USIBR USI Buffer Register Page 1270x0F (0x2F)USIDR USI Data RegisterPage 1230x0E (0x2E)USISR USISIF USIOIF USIPF USIDC USICNT3USICNT2USICNT1USICNT0Page 1280x0D (0x2D)USICR USISIE USIOIE USIWM1USIWM0USICS1USICS0USICLK USITC Page 1280x0C (0x2C)TIMSK1––ICIE1––OCIE1B OCIE1A TOIE1Page 1110x0B (0x2B)TIFR1––ICF1––OCF1BOCF1ATOV1Page 1120x0A (0x2A)Reserved –0x09 (0x29)Reserved –0x08 (0x28)ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1ACIS0Page 1290x07 (0x27)ADMUX REFS1REFS0MUX5MUX4MUX3MUX2MUX1MUX0Page 1440x06 (0x26)ADCSRA ADENADSCADATEADIFADIEADPS2ADPS1ADPS0Page 1460x05 (0x25)ADCH ADC Data Register High Byte Page 1480x04 (0x24)ADCL ADC Data Register Low Byte Page 1480x03 (0x23)ADCSRB BIN ACME –ADLAR–ADTS2ADTS1ADTS0Page 130, Page 1480x02 (0x22)Reserved –0x01 (0x21)DIDR0ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Page 131, Page 1490x00 (0x20)PRR––––PRTIM1PRTIM0PRUSIPRADCPage 3688183AS–AVR–12/08ATtiny24A/44ANote:1.For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.2.I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In theseregisters, the value of single bits can be checked by using the SBIS and SBIC instructions.3.Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBIinstructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.98183AS–AVR–12/08ATtiny24A/44A5.Instruction Set SummaryMnemonicsOperandsDescriptionOperation Flags#ClocksARITHMETIC AND LOGIC INSTRUCTIONSADD Rd, Rr Add two RegistersRd ← Rd + RrZ,C,N,V,H 1ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1SBCI Rd, K Subtract with Carry Constant from Reg.Rd ← Rd - K - C Z,C,N,V,H 1SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2AND Rd, Rr Logical AND RegistersRd ← Rd ? Rr Z,N,V 1ANDI Rd, K Logical AND Register and Constant Rd ← Rd ? K Z,N,V 1OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1COM Rd One’s Complement Rd ← 0xFF ? Rd Z,C,N,V 1NEG Rd Two’s Complement Rd ← 0x00 ? Rd Z,C,N,V,H 1SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1CBR Rd,K Clear Bit(s) in Register Rd ← Rd ? (0xFF - K) Z,N,V 1INC Rd Incremen t Rd ← Rd + 1Z,N,V 1DEC Rd DecrementRd ← Rd ? 1 Z,N,V 1TST Rd Test for Zero or Minus Rd ← Rd ? Rd Z,N,V 1CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1SER Rd Set Register Rd ← 0xFF None 1BRANCH INSTRUCTIONSRJMP kRelative Jump PC ← PC + k + 1None 2IJMP Indi rect Jump to (Z)PC ← Z None 2RCALL kRelative Subroutine Call PC ← PC + k + 1None 3ICALL Indirect Call to (Z)PC ←Z None 3RET Subroutine Return PC ← STACK None 4RETI Interrupt Return PC ← STACKI 4CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC +2 or 3None 1/2/3CP Rd,Rr CompareRd ? Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with CarryRd ? Rr ? C Z, N,V,C,H 1CPI Rd,K Compare Register with Immediate Rd ? KZ, N,V,C,H 1SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3None 1/2/3SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3None 1/2/3BRBS s, k Branc h if Status Flag Set if (SREG(s) = 1) then PC ←PC+k + 1None 1/2BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ←PC+k + 1None 1/2BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1None 1/2BRNE k Branch if Not Equal if (Z = 0) then PC ← P C + k + 1None 1/2BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1None 1/2BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1None 1/2BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1None 1/2BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1None 1/2BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1None 1/2BRPL k Branch if Plusif (N = 0) then PC ← PC + k + 1None 1/2BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1None 1/2BRLT k Branch if Le ss Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1None 1/2BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1None 1/2BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1None 1/2BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1None 1/2BRTCk Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1None 1/2BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1None 1/2BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1None 1/2BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1None 1/2BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1None 1/2BIT AND BIT-TEST INSTRUCTIONSSBI P,b Set Bit in I/O Register I/O(P,b) ←1None 2CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None 2LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V 1LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V 1ROLRd Rotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C ←Rd(7)Z,C,N,V1108183AS–AVR–12/08ATtiny24A/44AROR Rd Rotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C ←Rd(0)Z,C,N,V 1ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6Z,C,N,V 1SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)None 1BSET s Flag Set SREG(s) ← 1SREG(s)1BCLR s Flag ClearSREG(s) ← 0 SREG(s)1BST Rr, b Bit Store from Register to T T ← Rr(b)T 1BLD Rd, bBit load from T to Register Rd(b) ← T None 1SEC Set Carry C←1C 1CLC Clear Carry C ← 0 C 1SEN Set Negative Flag N ←1N 1CLN Clear Negative Flag N ← 0 N 1SEZ Set Z ero Flag Z ← 1Z 1CLZ Clear Zero Flag Z ← 0 Z 1SEI Global Interrupt Enable I ←1I 1CLI Global Interrupt Disable I ← 0 I 1SES Set Signed Test Flag S ← 1S 1CLS Clear Signed Test FlagS ← 0 S 1SEV Set Twos Complement Overflow.V ← 1V 1CLV Clear Twos Complement Overflow V ← 0 V 1SET Set T in SREG T ←1T 1CLT Clear T in SREGT ← 0T 1SEH Set Half Carry Flag in SREGH ←1H 1CLHClear Half Carry Flag in SREGH ← 0H 1DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between RegistersRd ← Rr None 1MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1LDI Rd, K Load Immediate Rd ← KNone 1LD Rd, X Load Indirect Rd ← (X)None 2LD Rd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None 2LD Rd, - X Load Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None 2LD Rd, Y Load IndirectRd ← (Y)None 2LD Rd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None 2LD Rd, - Y Load Indirect and Pre-Dec.Y ← Y - 1, Rd ←(Y)None 2LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q)None 2LD Rd, Z Load Indirect Rd ← (Z)None 2LD Rd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None 2LD Rd, -Z Load Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None 2LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q)None 2LDS Rd, k Load Direct from SRAM Rd ← (k)None 2ST X, Rr Store Indirect(X) ← RrNone 2ST X+, Rr Store Indirect and Post-Inc.(X) ← Rr, X ← X + 1None 2ST - X, Rr Store Indirect and Pre-Dec.X ← X - 1, (X) ← Rr None 2ST Y, Rr Store Indirect(Y) ← RrNone 2ST Y+, Rr Store Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None 2ST - Y, Rr Store Indirect and Pre-Dec.Y ← Y - 1, (Y) ← Rr None 2STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2ST Z, Rr Store Indirect(Z) ← RrNone 2ST Z+, Rr Store Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None 2ST -Z, Rr Store Indirect and Pre-Dec.Z ← Z - 1, (Z) ← Rr None 2STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2STS k, RrStore Direct to SRAM (k) ← Rr None 2LPM Load Program Memory R0 ← (Z)None 3LPM Rd, Z Load Program Memory Rd ← (Z)None 3LPM Rd, Z+Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1None 3SPM Store Program Memory (z) ← R1:R0None IN Rd, P In Port Rd ←P None 1OUT P, Rr Out PortP ← Rr None 1PUSH Rr Push Register on Stack STACK ← Rr None 2POP Rd Pop Register from Stack Rd ← STACKNone 2MCU CONTROL INSTRUCTIONSNOP No Operation None1SLEEP Sleep(see specific descr. for Sleep function)None 1WDR Watchdog Reset (see specific descr. for WDR/Timer)None 1BREAK BreakFor On-chip Debug Only NoneN/AMnemonicsOperandsDescriptionOperationFlags#Clocks118183AS–AVR–12/08ATtiny24A/44A6.Ordering InformationNotes:1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities.2.Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). AlsoHalide free and fully Green.6.1ATtiny24ASpeed (MHz)Power SupplyOrdering Code (1)Package (2)Operational Range 201.8 - 5.5VA Ttiny24A-SSU A Ttiny24A-PU A Ttiny24A-MU A Ttiny24A-MMH14S114P320M120M2Industrial (-40°C to 85°C)Package Type14S114-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)14P314-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)20M120-pad, 4 x 4 x 0.8 mm Body, Quad Flat No Lead / Micro Lead Frame Package (QFN/MLF)20M220-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)128183AS–AVR–12/08ATtiny24A/44ANotes:1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informationand minimum quantities.2.Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). AlsoHalide free and fully Green.6.2ATtiny44ASpeed (MHz)Power SupplyOrdering Code (1)Package (2)Operational Range 201.8 - 5.5VA Ttiny44A-SSU A Ttiny44A-PU A Ttiny44A-MU A Ttiny44A-MMH14S114P320M120M2Industrial (-40°C to 85°C)Package Type14S114-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)14P314-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)20M120-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)20M220-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)138183AS–AVR–12/08ATtiny24A/44A7.Packaging Information7.120M1148183AS–AVR–12/08ATtiny24A/44A7.220M2158183AS–AVR–12/08ATtiny24A/44A7.314P3168183AS–AVR–12/08ATtiny24A/44A7.414S1178183AS–AVR–12/08ATtiny24A/44A8.ErrataThe revision letters in this section refer to the revision of the corresponding ATtiny24A/44A device.8.1ATtiny24A8.1.1Rev. GNot sampled.8.1.2Rev. FNot sampled.188183AS–AVR–12/08ATtiny24A/44A8.2ATtiny44A8.2.1Rev. FNo known errata.8.2.2Rev. ENot sampled.198183AS–AVR–12/08ATtiny24A/44A9.Datasheet Revision History9.1Rev A. 12/081.Initial revision. Created from document 8006H.2.Updated "Ordering Information" on page 17 and page 18. Pb-plated packages are nolonger offered and there are no separate ordering codes for commercial operation range, the only available option now is industrial. Also, updated some order codes to reflect changes in leadframe composition and added VQFN package option.3.Updated data sheet template.4.Removed all references to 8K device.5.Updated characteristic plots of section “Typical Characteristics”, starting on page 182.6.Added characteristic plots:–“Internal Bandgap Voltage vs. Supply Voltage” on page 202–“Internal Bandgap Voltage vs. Temperature” on page 2027.Updated sections:–“Features” on page 1–“Power Reduction Register” on page 34–“AnalogComparator” on page 128–“Features” on page 132–“Operation” on page 133–“Starting a Conversion” on page 134–“ADC Voltage Reference” on page 139–“Speed Grades” on page 1748.Updated Figures:–“Program Memory Map” on page 15–“Data Memory Map” on page 169.Update Tables:–“Device Signature Bytes” on page 161–“DC Characteristics. T A = -40°C to +85°C” on page 173–“Additional Current Consumption for the different I/O modules (absolute values)” on page 182–“Additional Current Consumption (percentage) in Active and Idle mode” on page 183。