A Flexible Interconnect Technology Demonstrated on a Wafer-Level Chip Scale Package

A Flexible Interconnect Technology Demonstrated on a Wafer-Level Chip Scale PackageS.C. Yang, C.J. Wu, Y.L. Hsiao, C.H. Tung, Doug C.H. Yu,TSMC R & D, Taiwan Semiconductor Manufacturing Company, Hsinchu 30844, Taiwan,Email: chtungc@AbstractIn this paper, a flexible interconnect technology, including Cu wire bonding and pre-solder was proposed and demonstrated in 200 mm2WLCSP. Flexible interconnects were fabricated by a modified industry wire bonder with good position accuracy and height uniformity. Different wire geometries were created. In addition, influence of wire material, die thickness and solder volume is also investigated. Chips with more than 1000 interconnects were directly mounted on PCB and underfill is not used after assembly process. All assembled units were subjected to the board level reliability thermal cycling test according to JEDEC standard. Some of them were also subjected to drop tests. Both experimental and finite element analysis have demonstrated that flexible interconnects can greatly improve the thermal mechanical reliability and survived over 500 cycles without underfill. In the drop test, N-shape interconnects have better performance than I-shape interconnects and pass over 30 drops. This flexible interconnection technology can lead to excellent reliability in larger WLCSPs without the use of underfill. In addition, this flexible interconnect could be applied in a fine pitch PoP and the number of I/O pads can be increased without modifying the package structure. IntroductionWafer-level chip-scale package (WLCSP) offers competitive packaging solutions for cost and space constrained mobile and new wearable devices. WLCSP allow die to be attached to printed circuit boards (PCB) without the use of underfill materials or packaged units, such as PBGA, QFP/QFN. Today, many devices with die sizes of approximately 6ⅹ6 mm are in mass production using WLCSP. The size of die that can be mounted on PCB is limited due to the thermal expansion mismatch between Si (CTE~2.6 ppm/℃) and FR-4 board (CTE~18 ppm/℃). As dies get larger, warpage is exacerbated and the ball fatigue reliability risk becomes more critical. To improve solder joint reliability, underfill is especially required to mitigate the thermal expansion mismatch when die size is large [1-3]. Additional process requirements, increased cost, reduced manufacturing throughputs, and the inability to rework defective parts are drawbacks of underfill.In order to improve board-level reliability of non-underfilled WLCSP, a lot of researches were done to enhance solder ball reliability performance through structure design optimization [4-12]. For ball on polymer (BOP) structures, the compliance of the polymer film is attributed to be the reason for thermal-mechanical performance improvement in solder joint [4-5]. The solder ball is placed over a layer of polymer dielectric material which offers improved capacitance, reliability and better compatibility to polyimide passivation. In encapsulated Cu post WLP technology [6], electroplated Cu posts instead of pads to virtually increase the height of solder balls. Increasing solder ball height will make whole WLP structure more flexible, therefore the thermal cycling performance can be improved. Other approaches to increasing the stand-off bump height have been developed. Double-bump WLP technologies [7-9] and stretched solder interconnects [10-12] could increase the stand-off height and redistribute stress on the joint. However, none of the aforementioned approaches could sustain reliability test in WLCSP with chip size larger than 10 x 10 mm2.In this paper, a revolutionary contact technology combined of Cu wire bonding and surface mount technology (SMT) soldering to replace traditional BGA is reported and demonstrated in large die WLCSP, as shown in Fig.1. Innovative wire geometry was fabricated and reliability stressing was performed to optimize interconnect structure and material design. The reliability performance and fatigue behavior of the flexible interconnect were compared with traditional BGA joint. This technique can be used not only for WLCSP but for 3D stacked package, such as PoP.Figure 1. SEM image of (a) as-fabricated BGA joint and (b) as-fabricated flexible interconnect.Experimental proceduresTo test the flexible interconnects in this research, a WLCSP with chip size 200 mm2 with more than 1150 full ball grid array is selected. The package is designed with pads at 400 μm pitch and 240 μm UBM (Under Bump Metallurgy) size. In addition, test chips with two die thicknesses, 31 mil and 13 mil were prepared.Wire bonding was used to replace the conventional BGA joint for forming interconnects. A modified industry wire bonder is developed by Kaijo and two wire configurations (I-shape and N-shape) were designed and fabricated, as shown in Fig. 2. The wire bonds have good positioning accuracy (x and y) and uniform height (z), as shown in Fig. 3. The position accuracy for all direction is within ± 10 μm. The key wire bonding materials include the Palladium-coated Cu and Bare Cu. The influence of wire material was investigatedthrough reliability test. Different wire shape (I- and N- shape), wire diameter (1.2 and 1.5 mil), horizontal length (150 and 200 μm), and stand-off height (300 and 400 μm) were tested for optimized interconnect structure.Figure 2.Micrograph image of flexible interconnects fabricated on 200 mm2 test chips. (a) I-shape and (b) N-shape interconnects.Figure 3.Micrograph image of flexible interconnects after assembly process. (a) I-shape and (b) N-shape interconnects.Test chips with wire bonds were directly mounted on PCB board with standard SMT assembly process, including pre-solder screen-printing, pick & place and reflow. Reflow profile was adjusted with low peak temperature and short dwell time to minimize the solder climbing up wire surface. In addition, pre-solder volume needs to be controlled to achieve proper soldering shape. The as-fabricated sample was shown in Fig. 4. Underfill is not used after assembly process. Daisy chain design is integrated through silicon RDL, flexible interconnect and PCB to monitor the flexible interconnect electrical continuity during thermal cycling loading.Thermal-cycling test condition refers to JEDEC standard with a temperature range of -40℃to 125℃at 1 hour per cycle. Board level drop tests with the peak acceleration 1500 G, pulse duration 0.5 ms and drop height 90 cm were performed to evaluate the reliability performance of the novel flexible structure.Figure 4.Micrograph image of flexible interconnects after assembly process. (a) I-shape and (b) N-shape interconnects. Results and AnalysisAfter assembly the boards were subjected to drop tests and thermal cycling tests. Weibull analysis was performed on the drop test and temperature cycling data. The results of these tests were discussed in this section.A.Drop reliability performanceThe drop test results for I-shape with Ø1.2mil and N-shape interconnects with Ø1.2/1.5mil are summarized in Fig.5. Die thickness is 13mil. It should be noted that the underfill was not used in this study.Early failure was observed in samples with Ø1.2 I-shape interconnects. The failure position occurred on Cu wire near chip side [Fig. 6 (a)]. There is no electrical failure for Ø1.2 N-shape interconnects after 30 drops. It means N-CST could sustain board level drop test requirement. Moreover, drop performance could be improved with the wire diameter increasing. As the wire diameter increased from 1.2mil to 1.5mil, the drop performance improved about two times.Figure 5. Comparison of the drop performance of I-shape and N-shape interconnects.Figure 6.Drop test failure modes for (a) Ø1.2mil I-shape interconnects, (b) Ø1.2mil N-shape interconnects, and (c) Ø1.5mil N-shape interconnects,B.Thermal cycling reliability performanceThe thermal cycling test results for conventional BGA, I-shape and N-shape interconnect are plotted in Fig. 7. The Weibull distribution is used to determine the characteristic lift (T63). Comparing I-shape interconnects and BGA, I-shape interconnects have similar TC performance with conventional BGA and the characteristic lifetime was less than 300 cycles. I-shape interconnects did not lead to better thermal cycling performance due to its rigid structure.Figure 7.Weibull plot of thermal cycling test for BGA, I-shape interconnects and N-shape interconnects.From Fig. 7, it is observed that N-shape interconnects have a far superior thermo-mechanical reliability with the characteristic lifetime achieved over 2000 cycles. The thermal cycling reliability of the N-shape interconnects exhibits about 8.5 times enhancement compared to that of conventional BGA. The compliant interconnects are able to absorb stress and improve overall reliability. Failure analysis was performed by cross sectioning the failed interconnects. Instead of solder joint crack in a conventional BGA packaging, fracture of Cu wire was observed in I-shape and N-shape interconnects [Fig. 8]. The locus of crack initiation and propagation occurred on the wire at wire-to-solder transition region.Figure 8. Thermal fatigue crack propagation in (a) BGA and (b) N-shape interconnects.The finite element modeling (FEM) results agreed well with the experimental observations that N-shaped interconnects could reduce accumulated stress significantly, as shown in Fig. 9. The position where the largest equivalent plastic strain (EPS) is the most susceptible region and the strain level represents the reliability of interconnects during thermal cycling. The result revealed that the EPS in N-shaped interconnects was reduced by 16 times compared with the I-shape interconnects and high strain concentrated at the Cu ball necking and wire-to-solder transition region.Figure 9. Thermal fatigue crack propagation in (a) BGA and (b) N-shape interconnects.From above result, the newly designed N-shape interconnects has better capability to absorb stresses. A stiff interconnect, such as BGA or I-shape interconnects, will induce high stress concentration and is not suitable for the large die application. In the following, key performance indicators affecting the TC performance of N-shape interconnects would be discussed.Effect of die thickness and pre-solder volumeIt is well known that thinner die has better solder joint performance [13-14]. Firstly, thinner die results in less global CTE mismatch stress with PCB. Secondly, thinner die is more compliant, and therefore the strains induced in solder jointsare reduced. The die thickness effect was also observed in our structure. Figure 10 shows the Weibull plot of thermal cycling for 31mil and 13mil die thickness with all the other parameters controlled. The characteristic lifetime of N-shape flexible interconnect could be increased by about 2.5 times as the die thickness decreased from 31mil to 13mil.Different pre-solder volume is also tested and shown in Fig 11. Two stencil opening, 240μm to 200μm, were tested and the stencil height was controlled to be 60μm. The test result showed that less solder volume (1 vs 1.45) had a negative effect on TC performance.Figure 10.Weibull plot of thermal cycling for different die thickness.Figure 11. Weibull plot of thermal cycling for different pre-solder volume.Effect of standoff height and horizontal lengthN-shape interconnects with different standoff height (300/400μm) and different horizontal length (150/200μm) are subjected to thermal cycling test, as showed in Fig. 12. It is obvious that increasing the wire height from 300 to 400μm has greater TC performance improvement (about 4 times). Then fatigue lifetime could be further improved by about 1.5 times by increasing the horizontal length from 150 to 200μm. This result showed that interconnects with longer horizontal length and stand-off height could increase the total wire length and become more flexible, leading to longer lifetime.Figure 12.(a) Diagrammatic drawing of N-shape interconnects. L is the horizontal length and H is the standoff height. (b) Weibull plot of thermal cycling test for different horizontal length and standoff height.Effect of wire diameter and wire materialThe influence of wire diameter is also investigated [Fig. 13]. Pd-coated wires with 1.2 and 1.5 mil diameter were tested. The characteristic lifetime of Ø1.2 mil wire is about 2.7 times longer than Ø1.5 mil wire.A thinner wire is better for thermal cycling performance but not for drop performance. Moreover, thinner wire is flexible but becoming difficult to handle in production. The structure design needs to be optimized for different applications. In this study, wire with 1.2 mil diameter is the optimized size to provide superior reliability and to provide sufficient mechanical support.Figure 13. Weibull plot of thermal cycling for different wire diameter.In term of Cu wire material, two types of Cu wire, Pd-coated Cu and Bare Cu, were tested, as shown in Fig. 14. Pd-coated Cu provided better TC performance than Bare Cu. Inaddition, the Weibull slope of the distribution of Pd-coated Cu is larger than Bare Cu.Based on stress-strain curve comparison between bare Cu wire & Pd-coated Cu wire, as shown in Fig. 15, Pd-coated wire with more superior uniform elastic deformation, uniform plastic deformation and higher resistance to rapture under stress condition as compare to bare Cu [15]. Thus Pd-coated Cu could withstand higher stress load before proceed to necking condition.Figure 14. Weibull plot of thermal cycling for bare Cu andPd-coated Cu.Figure 15. Stress-Strain Curve for various Cu wire [15]. ConclusionsA novel flexible interconnect technology has been demonstrated on 200 mm2 large die WLCSP successfully and eliminates the use of underfill. N-shaped interconnects with longer wire length could led to better reliability performance. All key parameters for optimization of N-shape interconnects are identified and confirmed with experiment. This technology will enable future large die fine pitch WLP and stacked packages, such as PoP. AcknowledgmentsThe authors would like to thank Kaijo Corporation for developing and providing wire bonds fabrication. References1. C. Regard, C. Gautier, H. Fremont, P. Poirier, “Influenceof Underfill Methods on the Solder Joint Fatigue of Wafer Level Packaging” Proc. Electronic Packaging Technology & High Density Packaging, Shanghai, July, 2008, pp. 1-6.2.Y.H. Lin, F. Kuo, Y.F. Chen, C.S. Ho, J.Y. Lai, S. Chen,F.L. Chien, R. Lee, and J. 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