CC1216中文资料

AC1210, AC1212AC1216用户手册1简体中文9 保修与服务 16订购部件或附件 1610 注意事项 16电磁场 (EMF) 16回收 16目录1 重要事项 22 您的空气净化器 4产品概述 4控件概览 53 使用入门 6安装滤网 64 使用空气净化器 7了解空气质量指示灯 7打开和关闭 7更改风扇速度 8光传感器 9智感睡眠模式 9设置童锁 105 清洁 10清洁空气净化器的机身 10清洁空气质量传感器 10清洁预过滤网 116 更换滤网 13滤网更换指示灯 13更换过滤网 137 存放 148 故障排除 15勿让儿童在无人监督的情况下清洁和保养产品。

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仕 様 書形 名ＲＣＨ１２１６Ｂ１．外形＊ 端子の寸法は、はんだつらら除く。

1-2．捺印表示例頭部直捺印捺印位置不定 ２．コイル仕様 2-1．端子接続図(裏面図)(10μH～47μH) (56μH～2.2mH)＊ 10μH～47μHは、端子番号①と④、②と③を接続して御使用ください。

＊ 10μH～47μHは、端子②－③間又は①－④間の半田ブリッジが可とする。

①②③④①②③ compliance Cd:Max.0.01wt%others:Max.0.1wt%RoHS1仕 様 書形 名ＲＣＨ１２１６Ｂ2-2．電気的特性直流重畳 許容電流 (Ａ) ※３No. 品 名表示 インダクタンス[以内]※１D.C.R. (Ω) [以下] (at 20℃)※２ at 20℃at 100℃ 温度上昇許容電流 （Ａ） ※４ スミダコード01 RCH1216BNP-1ØØM 100M 10μH ±20％24m(19m) 9.00 8.00 5.00 -000102 RCH1216BNP-12ØM 120M 12μH ±20％26m(21m) 7.80 7.00 4.60 -000203 RCH1216BNP-15ØM 150M 15μH ±20％29m(23m) 7.20 6.20 4.40 -000304 RCH1216BNP-18ØM 180M 18μH ±20％33m(26m) 6.75 5.80 4.20 -000405 RCH1216BNP-22ØM 220M 22μH ±20％37m(29m) 6.00 5.30 4.00 -000506 RCH1216BNP-27ØM 270M 27μH ±20％41m(32m) 5.50 4.80 3.80 -000607 RCH1216BNP-33ØM 330M 33μH ±20％46m(36m) 5.00 4.50 3.60 -000708 RCH1216BNP-39ØM 390M 39μH ±20％49m(39m) 4.70 4.10 3.30 -000809 RCH1216BNP-47ØM 470M 47μH ±20％56m(44m) 4.30 3.80 3.20 -000910 RCH1216BNP-56ØK 560K 56μH ±10％87m(69m) 4.10 3.70 2.70 -001011 RCH1216BNP-68ØK 680K 68μH ±10％98m(78m) 3.80 3.30 2.40 -001112 RCH1216BNP-82ØK 820K82μH ±10％107m(85m) 3.20 2.90 2.25 -001213 RCH1216BNP-1Ø1K 101K 100μH ±10％121m(96m) 3.00 2.70 2.15 -001314 RCH1216BNP-121K 121K 120μH ±10％134m(107m) 2.85 2.60 2.05 -001415 RCH1216BNP-151K 151K 150μH ±10％156m(124m) 2.55 2.35 1.90 -001516 RCH1216BNP-181K 181K 180μH ±10％206m(164m) 2.20 2.05 1.65 -001617 RCH1216BNP-221K 221K 220μH ±10％236m(188m) 2.00 1.85 1.55 -001718 RCH1216BNP-271K 271K 270μH ±10％0.32(0.25) 1.85 1.70 1.40 -001819 RCH1216BNP-331K 331K 330μH ±10％0.37(0.29) 1.65 1.53 1.30 -001920 RCH1216BNP-391K 391K 390μH ±10％0.48(0.38) 1.55 1.35 1.05 -002021 RCH1216BNP-471K 471K 470μH ±10％0.55(0.44) 1.45 1.25 1.00 -002122 RCH1216BNP-561K 561K 560μH ±10％0.62(0.49) 1.36 1.18 0.95 -002223 RCH1216BNP-681K 681K 680μH ±10％0.79(0.63) 1.20 1.06 0.82 -002324 RCH1216BNP-821K 821K 820μH ±10％0.88(0.70) 1.14 0.97 0.75 -002425 RCH1216BNP-1Ø2K 102K 1.0mH ±10％ 1.13(0.90) 1.00 0.80 0.65 -002526 RCH1216BNP-122K 122K 1.2mH ±10％ 1.25(1.00)0.89 0.76 0.61 -002627 RCH1216BNP-152K 152K 1.5mH ±10％ 1.52(1.26)0.85 0.70 0.54 -002728 RCH1216BNP-182K 182K 1.8mH ±10％ 1.93(1.60)0.76 0.63 0.46 -002829 RCH1216BNP-222K 222K2.2mH ±10％2.52(2.10)0.650.570.41-0029※1 測定周波数 インダクタンス at 1kHz ※2 ( )内は、標準値とする。

512M: 32M x16 Mobile DDR SDRAM Document Title512M: 32M x 16 Mobile DDR SDRAMRevision HistoryRevision No. Date History0.0Aug 21, 2007 Initial DraftEmerging Memory & Logic Solutions Inc.4F Korea Construction Financial Cooperation B/D, 301-1 Yeon-Dong, Jeju-Do, Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1750 / Homepage : The attached datasheets provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.512M: 32M x 16 Mobile DDR SDRAM512M : 32M x 16bit Mobile DDR SDRAMTable 1: ORDERING INFORMATIONNOTE :1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.Part No.Max Freq.InterfacePackage RemarkEMD12164P-60(DDR332)166(CL3), 111(CL2)LVCMOSWafer Biz.EMD12164P-75(DDR266)133(CL3), 83(CL2)FEATURES1.8V power supply, 1.8V I/O powerLVCMOS compatible with multiplexed address.Double-data-rate architecture; two data transfers per clock cycleBidirectional data strobe(DQS) Four banks operation.MRS cycle with address key programs. CAS latency (2, & 3). Burst length (2, 4, & 8).Burst type (Sequential & Interleave). Differential clock inputs(CK and CKB). EMRS cycle with address key programs. PASR(Partial Array Self Refresh). DS (Driver Strength) Internal auto TCSR(Temperature Compensated Self Refresh) Deep power-down(DPD) mode. DM for write masking only.Auto refresh and self refresh modes. 64 refresh period (8K cycle).Operating temperature range (-25 ~ 85).GENERAL DESCRIPTIONThis EMD12164P is 536,870,912 bits synchronous double data rate Dynamic RAM. Each 134,217,728 bits bank is organized as 8,192 rows by 1024columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology.This device uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls.Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.512M: 32M x 16 Mobile DDR SDRAM Table 2: Pad DescriptionSymbol Type DescriptionsCK, CKB Input Clock : CK and CKB are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived from CK/ CKB.CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CKB and CKE, are disabled during power-down and self refresh mode which are contrived for low standby power consumption.CSB Input Chip Select : CSB enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CSB is registered HIGH. CSB provides for external bank selection on systems with multiple banks. CSB is considered part of the command code.RASB, CASB,WEBInput Command Inputs: CASB, RASB, and WEB(along with CSB) define the command being entered.DQM0, DQM1 Input Input Data Mask : DQM is an input mask signal for write data. Input data is masked when DQM is sam-pled HIGH along with that input data during a WRITE access. DQM is sampled on both edges of DQS. Although DQM pins are input-only, the DQM loading matches the DQ and DQS loading. For x16 devices, DQM0 corresponds to the data on DQ0-DQ7, DQM1 corresponds to the data on DQ8-DQ15.BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied.A0 - A12 Input Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-mand.DQ0-DQ15 I/O Data Bus: Input / OutputDQS0, DQS1 I/O Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. For x16 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15.VDD Supply Power Supply VSS Supply GroundVDDQ Supply I/O Power Supply VSSQ Supply I/O Ground512M: 32M x 16 Mobile DDR SDRAMDevice OperationSimplified State DiagramPower OnDeep Power DownPrecharge All BanksIdle All banks prechargedSelf RefreshMRS EMRSAuto RefreshPrecharge Power DownActive Power DownRow ActiveBurst StopWRITE WRITE APrecharge PREALLREAD AREADPower appliedDPDSXMRSDPDSACTREFABSTREADREADAWRITEAPRE REFSXREFSCKEL CKEHCKELCKEH WRITEREADREADA READAPREPREPREWRITEAAutomatic Sequence Command SequenceACT = ActiveBST = Burst Terminate CKEL = Enter Power-Down CKEH =Exit Power-Down DPDS = Enter Deep Power-Down DPDSX = Exit Deep Power-DownEMRS = Ext. Mode Reg. Set MRS = Mode Register Set PRE = PrechargePREALL = Precharge All Banks REFA = Auto Refresh REFS = Enter Self RefreshREFSX = Exit Self Refresh READ = Read w/o Auto Precharge READA = Read with Auto Precharge WRITE = Write w/o Auto Precharge WRITEA = Write with Auto PrechargeREADWRITE512M: 32M x 16 Mobile DDR SDRAM FUNCTIONAL BLOCK DIAGRAM512M: 32M x 16 Mobile DDR SDRAMElectrical SpecificationsTable 3: ABSOLUTE MAXIMUM RATINGSNOTE :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Table 4: DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = -25o C~ 85o C for Extended)1. Under all conditions, VDDQ must be less than or equal to VDD.2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.Table 5: CAPACITANCE (V DD = 1.8V, V DDQ = 1.8V, T A = 25, f=1)ParameterSymbol Value Unit Voltage on any pin relative to V SSV IN ,V OUT -0.5 ~ 2.5V Voltage on V DD and V DDQ supply relative to V SS V DD , V DDQ-0.5 ~ 2.5VStorage temperature T STG -55 ~ +150Power dissipation P D 1.0WShort circuit current I OS50ParameterSymbol Min Typ Max Unit Note Supply voltage V DD 1.7 1.8 1.95V 1V DDQ 1.7 1.8 1.95V 1Input logic high voltage V IH 0.8 x V DDQ1.8V DDQ + 0.3V 2Input logic low voltage V IL -0.300.3V 2Output logic high voltage V OH 0.9 x V DDQ--V I OH = -0.1Output logic low voltage V OL --0.1 x V DDQVI OL = 0.1Input leakage current I LI -2-2Output leakage current I LO-5-5PinSymbol Min Max Unit NoteInput capacitance(ADD, BA0~1, RASB, CASB, WEB, CSB, CKE)C IN1 1.5 3.0Input capacitance(CK, CKB)C IN2 1.5 3.5Data & DQS input/output capacitance C out 2.0 4.5Input capacitance(DM)C IN32.04.5512M: 32M x 16 Mobile DDR SDRAM Table 6: DC CHARACTERISTICSRecommended operating conditions (Voltage referenced to VSS = 0V, T A = -25 to 85)Parameter Symbol Test ConditionVersionUnit -60-75Operating one bank active-precharge current I DD0t RC = t RCmin; t CK = t CKmin; CKE is HIGH; CSB is HIGHbetween valid commands; address inputs are SWITCH-ING; data bus inputs are STABLE10080mAPrecharge power-down standby current I DD2Pall banks idle, CKE is LOW; CSB is HIGH, t CK = t CKmin;address and control inputs are SWITCHING; data businputs are STABLE0.6mAPrecharge power-down standby current with clock stop I DD2PSall banks idle, CKE is LOW; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE0.6Precharge non power-down standby current I DD2Nall banks idle, CKE is HIGH; CSB is HIGH, t CK = t CKmin;address and control inputs are SWITCHING; data businputs are STABLE2520mAPrecharge non power-down standby current with clock stop I DD2NSall banks idle, CKE is HIGH; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE55Active power-down standby current I DD3Pone bank active, CKE is LOW; CSB is HIGH, t CK =t CKmin; address and control inputs are SWITCHING; databus inputs are STABLE8mAActive power-down standby current with clock stop I DD3PSone bank active, CKE is LOW; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE5Active non power-down standby current I DD3None bank active, CKE is HIGH; CSB is HIGH, t CK =t CKmin; address and control inputs are SWITCHING; databus inputs are STABLE2525mAActive non power-down standby current with clock stop I DD3NSone bank active, CKE is HIGH; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE1010mAOperating burst read current I DD4Rone bank active; BL=4; CL=3; t CK = t CKmin; continuousread bursts; Iout = 0 mA; address inputs are SWITCHING;50% data change each burst transfer130110mAOperating burst write current I DD4Wone bank active; t CK = t CKmin; continuous write bursts;address inputs are SWITCHING; 50% data change eachburst transfer11090mAAuto-Refresh current I DD5t RC = t RFCmin; burst refresh; CKE is HIGH;address and control inputs are SWITCHING; data businputs are STABLE120120mASelf Refresh Current I DD6CKE is LOW, CK = LOW, CKB= HIGH; Extended Mode Reg-ister set to all 0s; address andcontrol inputs are STABLE;data bus inputs are STABLETCSR Range45*185°CFull Array350600µA1/2 of Full Array2505001/4 of Full Array200450Deep Power-Down Current I DD8Address and Control inputs are STABLE;data bus inputs are STABLE1010µA512M: 32M x 16 Mobile DDR SDRAMNOTE :1. IDD specifications are tested after the device is properly initialized2. Input slew rate is 1V/ns.3. Definitions for IDD:LOW is defined as V IN 0.1 * VDDQ ; HIGH is defined as V IN 0.9 * VDDQ ;STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as :- address and command : inputs changing between HIGH and LOW once per two clock cycles ;- data bus inputs : DQ changing between HIGH and LOW once per clock cycle ; DM and DQS are STABLETable 7: AC OPERATING TEST CONDITIONS(V DD = 1.7V ~ 1.95V, T A = -25~85for Extended)NOTE :1. Under all conditions, VDDQ must be less than or equal to VDD.2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.3. CK and CKB crossing voltage.ParameterValueUnitNoteAC input levels(Vih/Vil)0.8V DDQ / 0.2 V DDQV Input timing measurement reference level 0.5V DDQ V Input rise and fall time1.0V /Output timing measurement reference level 0.5V DDQVVix0.4V DDQ (Min) / 0.6V DDQ (Max)V3Output load condition See Figure 21.8V 13.9V OH (DC) = 0.9V DDQ , I OH = -0.1V OL (DC) = 0.1V DDQ , I OL = 0.120Z0=50Vtt=0.5V DDQ5020Figure 1. DC Output Load CircuitFigure 2. AC Output Load CircuitOutputOutput10.6512M: 32M x 16 Mobile DDR SDRAMTable 8: OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)Parameter Sym-bol-60-75Unit Note Min Max Min MaxDQ output access time from CK/CKB t AC25 2.5 6.0ns3 DQS output access time from CK/CKB t DQSCK25 2.5 6.0ns Clock high-level width t CH0.450.550.450.55t CK Clock low-level width t CL0.450.550.450.55t CKClock half period t HPmin(t CL,t CH)min(t CL,t CH)nsClock cycle time CL = 3t CK61007.5100ns CL = 2910012100nsDQ and DM input setup time t DS 1.0 1.0ns4,5 DQ and DM input hold time t DH 1.0 1.0ns4,5 DQ and DM input pulse width t DIPW 1.8 2.0ns Address and control input setup time t IS 1.1 1.3ns1 Address and control input hold time t IH 1.1 1.3ns1 Address and control input pulse width t IPW 2.6 2.6nsDQ & DQS low-impedance time from CK/CKB t LZ 1.0 1.0nsDQ & DQS high-impedance time from CK/CKB t HZ5 6.0nsDQS - DQ skew t DQSQ0.60.6nsDQ / DQS output hold time from DQS t QH t HP-t QHS t HP-t QHS nsData hold skew factor t QHS0.650.75nsWrite command to 1st DQS latching transition t DQSS0.75 1.250.75 1.25t CKDQS input high-level width t DQSH0.40.60.40.6t CKDQS input low-level width t DQSL0.40.60.40.6t CKDQS falling edge to CK rising - setup time t DSS0.20.2t CKDQS falling edge from CK rising - hold time t DSH0.20.2t CK MODE REGISTER SET command period t MRD22t CKWrite preamble setup time t WPRES00nsWrite postamble t WPST0.40.60.40.6t CKWrite preamble t WPRE0.250.25t CK512M: 32M x 16 Mobile DDR SDRAMNote:Table 9: Input Setup/Hold Slew Rate1. This derating table is used to increase t IS /t IH in the case where the input slew rate is below 1.0V/ns.2. Minimum 5CK of t DAL (= t WR + t RP ) is required because it need minimum 2CK for t WR and minimum 3CK for t RP .3. t AC (min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C). t AC (max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).t AC is measured in the device with half driver strength and under the AC output load condition (Fig.2 in Page 8).ParameterSym-bol-60-75Unit NoteMin Max Min Max Read preamble CL = 2t RPRE 0.5 1.10.5 1.1t CK CL = 30.9 1.10.9 1.1t CK Read postamblet RPST 0.40.60.40.6t CK ACTIVE to PRECHARGE command period t RAS 42100,00045100,000ns ACTIVE to ACTIVE command period t RC 6060ns AUTO REFRESH toACTIVE / AUTO REFRESH command period t RFC 9090ns 6ACTIVE to READ or WRITE delay t RCD 1818ns PRECHARGE command period t RP 1822.5ns ACTIVE bank A to ACTIVE bank b delay t RRD 1821ns Column address to Column address delay t CCD 11t CK WRITE recovery timet WR 22t CKAuto precharge write recovery + precharge time t DAL t WR+t RPt WR+t RP2Internal write to Read command delay t WTR 11t CK Self refresh exit to next valid command delay t XSR 120120nsExit power down to next valid command delay t XP t CK +t ISt CK +t ISCKE min. pulse width(high and low pulse width)t CKE 12t CK Refresh Periodt REF6464ms Input Setup/Hold Slew Rate∆t IS ∆t IH (V/ns)(ps)(ps)1.0000.8+50+500.6+100+100512M: 32M x 16 Mobile DDR SDRAMTable 10: I/O Setup/Hold Slew Rate4. This derating table is used to increase t DS /t DH in the case where the I/O slew rate is below 1.0V/ns.Table 11: I/O Delta Rise/Fall Rate(1/slewrate)5. This derating table is used to increase t DS /t DH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 = 0.8V/ns, then the Delta Rise/Fall Rate = -0.25ns/V.6. Maximum burst refresh cycle : 8I/O Setup/Hold Slew Rate∆t DS ∆t DH (V/ns)(ps)(ps)1.0000.8+75+750.6+150+150Delta Rise/Fall Rate∆t DS ∆t DH (ns/V)(ps)(ps)0000.25+50+500.5+100+100512M: 32M x 16 Mobile DDR SDRAM Functional DescriptionThe 512Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM. Each of the 134,217,728-bit banks is organized as 8,192 rows by 1024 columns by 16 bits.The 512Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. single read or write access for the 512Mb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and con-tinue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the start-ing column location for the burst access.It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has been omitted to save power. Prior to normal operation, the Mobile DDR SDRAM must be initial-ized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.InitializationMobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. If there is an interruption to the device power, the initialization rou-tine should be followed to ensure proper functionality of the Mobile DDR SDRAM. The clock stop feature is not avail-able until the device has been properly initialized.To properly initialize the Mobile DDR SDRAM, this sequence must be followed:1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the samepower source and brought up simultaneously. If separate power sources are used, VDD must lead VDDQ.2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.3. Once the clock is stable, a 200µs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an exe cutable command. During this time, NOP or DESELECT commands must be issued on the command bus.4. Issue a PRECHARGE ALL command.5. Issue NOP or DESELECT commands for at least tRP time.6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a second AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. As part of the initialization sequence, two AUTO REFRESH commands must be issued. Typically, both of these commands are issued at this stage as described above. Alternately, the second AUTO-REFRESH command and NOP or DESELECT sequence can be issued between steps 10 and 11.7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.8. Issue NOP or DESELECT commands for at least tMRD time.9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical.10. Issue NOP or DESELECT commands for at least tMRD time.11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.512M: 32M x 16 Mobile DDR SDRAM Register DefinitionMode RegistersThe mode registers are used to define the specific mode of operation of the Mobile DDR SDRAM. There are two mode registers used to specify the operational characteristics of the device. The standard mode register, which exists for all SDRAM devices, and the extended mode register, which exists on all Mobile SDRAM devices.Standard Mode RegisterThe standard mode register definition includes the selection of a burst length, a burst type, a CAS latency and an oper-ating mode, as shown in page 15. The standard mode register is programmed via the LOAD MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again. Reprogram-ming the standard mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A12 specify the operating mode.Note: Standard refers to meeting JEDEC-standard mode register definitions.Burst LengthRead and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in page 15. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 are available for both the sequential and the interleaved burst types.Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Burst TypeAccesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected by A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. See Table 17~19 on page 17 for more information.CAS LatencyThe CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 3 clocks, as shown in page 15.For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at (n + 2 clocks + tAC). For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally be avail-able at (n + 1 clock + tAC).Reserved states should not be used as unknown operation or incompatibility with future versions may result.Operating ModeThe normal operating mode is selected by issuing a LOAD MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.512M: 32M x 16 Mobile DDR SDRAMExtended Mode RegisterThe extended mode register controls functions specific to low power operation. These additional functions include drive strength, temperature compensated self refresh, and partial array self refresh.This device has default values for the extended mode register (if not programmed, the device will operate with the default values . PASR = Full Array, DS = Full Drive).Temperature Compensated Self RefreshOn this version of the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. Programming of the temperature compensated self refresh (TCSR) bits will have no effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature.Partial Array Self RefreshFor further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. Low Power DDR SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.Output Driver StrengthBecause the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and A6 of the extended mode register can be used to select the driver strength of the DQ outputs.Stopping the External ClockOne method of controlling the power efficiency in applications is to throttle the clock which controls the Mobile DDR SDRAM. There are two basic ways to control the clock:1. Change the clock frequency, when the data transfers require a different rate of speed.2. Stopping the clock altogether.Both of these are specific to the application and its requirements and both allow power savings due to possible less transitions on the clock path.The Mobile DDR SDRAM allows the clock to change frequency during operation, only if all the timing parameters are met with respect to that change and all refresh requirements are satisfied.The clock can also be stopped all together, if there are no data accesses in progress, either WRITEs or READs that would be effected by this change; i.e., if a WRITE or a READ is in progress the entire data burst must be through the pipeline prior to stopping the clock. CKE must be held HIGH with CK = LOW and CKB = HIGH for the full duration of the clock stop mode. One clock cycle and at least one NOP is required after the clock is restarted before a valid com-mand can be issued.It is recommended that the Mobile DDR SDRAM should be in a precharged state if any changes to the clock frequency are expected. This will eliminate timing violations that may otherwise occur during normal operational accesses.BA1=0BA0=0BA0=1BA1=0BA1=0BA1=0BA0=0BA1=1BA1=1BA0=0BA0=1- Full Array- 1/2 Array- 1/4 ArrayBA1=1BA1=1BA1=0BA1=0BA0=0BA0=1BA1=1BA0=1BA0=0BA0=0BA0=1BA1=1BA0=1Partial Self Refresh Area512M: 32M x 16 Mobile DDR SDRAMTable 12: MODE REGISTER FIELD TABLE TO PROGRAM MODESRegister Programmed with Normal MRS NOTE :1. RFU(Reserved for future use) should stay “0” during MRS cycle.Table 13: Normal MRS Mode1. MRS can be issued only at all bank precharge state.2. Minimum tRP is required to issue MRS command.Address BA0 ~ BA1A12 ~ A10/APA9A8A7A6A5A4A3A2A1A0Function "0" Setting for Normal MRSRFU *1Operating ModeCAS LatencyBTBurst LengthOperating ModeCAS Latency Burst TypeBurst Length A8A7TypeA6A5A4Latency A3Type A2A1A0DDR 00Mode Register Set000Reserved 0Sequential 000Reserved01Reserved 001Reserved1Interleave 001210Reserved 0102Mode Select 010411Reserved0113BA1BA0Mode0118---100Reserved 0Setting for Nor-mal MRS100Reserved ---101Reserved 101Reserved ---110Reserved 110Reserved ---111Reserved111Reserved512M: 32M x 16 Mobile DDR SDRAMTable 14: Register Programmed with Extended MRSNOTE :1. RFU(Reserved for future use) should stay “0” during MRS and EMRS cycle.Table 15: EMRS for PASR(Partial Array Self Refresh) & DS(Driver Strength)Table 16: Internal Temperature Compensated Self Refresh (TCSR)NOTE :1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the two temperature range : Max 85, Max 452. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.3. It has +/- 5 tolerance.Address BA1BA0 A12 ~ A10/AP A9A8A7A6A5A4A3A2A1A0Function Mode SelectRFU *1DSRFU *1PASRMode SelectDriver Strength PASRBA1BA0MODE A6A5Driver Strength A2A1A0Size of Refreshed Array00Normal MRS 00Full 000Full Array 01Reserved011/20011/2 of Full Array 10EMRS for DDR SDRAM101/40101/4 of Full Array 11Reserved111/8011Reserved 100Reserved 101Reserved 110Reserved 111ReservedTemperature RangeSelf Refresh Current (I DD 6)UnitFull Array1/2 of Full Array1/4 of Full ArrayMax 85600500450Max 45350250200。

VCDCLVP1216 SCAS877C–MAY2009–REVISED AUGUST201116LVPECL Output,High-Performance Clock BufferCheck for Samples:CDCLVP1216FEATURES DESCRIPTIONThe CDCLVP1216is a highly versatile,low additive •2:16Differential Bufferjitter buffer that can generate16copies of LVPECL •Selectable Clock Inputs Through Control Pin clock outputs from one of two selectable LVPECL,•Universal Inputs Accept LVPECL,LVDS,and LVDS,or LVCMOS inputs for a variety of LVCMOS/LVTTL communication applications.It has a maximum clockfrequency up to2GHz.The CDCLVP1216features •16LVPECL Outputsan on-chip multiplexer(MUX)for selecting one of two •Maximum Clock Frequency:2GHz inputs that can be easily configured solely through a•Maximum Core Current Consumption:110mA control pin.The overall additive jitter performance isless than0.1ps,RMS from10kHz to20MHz,and •Very Low Additive Jitter:<100fs,rms in10-kHzoverall output skew is as low as30ps,making the to20-MHz Offset Rangedevice a perfect choice for use in demanding • 2.375V to3.6V Device Power Supply applications.•Maximum Propagation Delay:550psThe CDCLVP1216clock buffer distributes one of two •Maximum Output Skew:30ps selectable clock inputs(IN0,IN1)to16pairs of •LVPECL Reference Voltage,V AC_REF,Available differential LVPECL clock outputs(OUT0,OUT15)with minimum skew for clock distribution.The for Capacitive-Coupled InputsCDCLVP1216can accept two clock sources into an •Industrial Temperature Range:–40°C to+85°Cinput multiplexer.The inputs can be LVPECL,LVDS,•ESD Protection Exceeds2kV(HBM)or LVCMOS/LVTTL.•Available in7-mm×7-mm QFN-48(RGZ)The CDCLVP1216is specifically designed for driving Package50-Ωtransmission lines.When driving the inputs insingle-ended mode,the LVPECL bias voltage APPLICATIONS(VAC_REF)should be applied to the unused negativeinput pin.However,for high-speed performance up to •Wireless Communications2GHz,differential mode is strongly recommended.•Telecommunications/NetworkingThe CDCLVP1216is packaged in a small48-pin,•Medical Imaging7-mm x7-mm QFN package and is characterized for •Test and Measurement Equipment operation from–40°C to+85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2009–2011,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.CDCLVP1216SCAS877C–MAY2009–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.Table1.AVAILABLE OPTIONS(1)T A PACKAGED DEVICES FEATURESCDCLVP1216RGZT48-pin QFN(RGZ)package,small tape and reel –40°C to+85°CCDCLVP1216RGZR48-pin QFN(RGZ)package,tape and reel(1)For the most current specifications and package information,see the Package Option Addendum located at the end of this data sheet orrefer to our web site at .ABSOLUTE MAXIMUM RATINGSOver operating free-air temperature range(unless otherwise noted).(1)CDCLVP1216UNITV CC Supply voltage range(2)–0.5to4.6VV IN Input voltage range(3)–0.5to V CC+0.5VV OUT Output voltage range(3)–0.5to V CC+0.5VI IN Input current20mAI OUT Output current50mAT A Specified free-air temperature range(no airflow)–40to+85°CT STG Storage temperature range–65to+150°CT J Maximum junction temperature+125°CESD Electrostatic discharge(HBM)2kV (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated is not implied.Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.(2)All supply voltages must be supplied simultaneously.(3)The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. RECOMMENDED OPERATING CONDITIONSOver operating free-air temperature range(unless otherwise noted).CDCLVP1216PARAMETER MIN TYP MAX UNITV CC Supply voltage 2.375 2.50/3.30 3.60VT A Ambient temperature–40+85°C PACKAGE DISSIPATION RATINGS(1)(2)VALUETEST4×4VIASPARAMETER CONDITIONS ON PAD UNIT0LFM33.8°C/WθJA Thermal resistance,junction-to-ambient150LFM22.6°C/W400LFM19.2°C/WθJP(3)Thermal resistance,junction-to-pad 3.67°C/W(1)The package thermal resistance is calculated in accordance with JESD51and JEDEC2S2P(high-K board).(2)Connected to GND with16thermal vias(0.3-mm diameter).(3)θJP(junction-to-pad)is used for the QFN package,because the primary heat flow is from the junction to the GND pad of the QFNpackage.2Submit Documentation Feedback Copyright©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1216CDCLVP1216 SCAS877C–MAY2009–REVISED AUGUST2011ELECTRICAL CHARACTERISTICS:LVCMOS Input(1)At V CC=2.375V to3.6V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1216PARAMETER TEST CONDITIONS MIN TYP MAX UNITf IN Input frequency200MHzExternal threshold voltage applied toV th Input threshold voltage 1.1 1.8Vcomplementary inputV IH Input high voltage V th+0.1V CC VV IL Input low voltage0V th–0.1VI IH Input high current V CC=3.6V,V IH=3.6V40μAI IL Input low current V CC=3.6V,V IL=0V–40μAΔV/ΔT Input edge rate20%to80% 1.5V/nsI CAP Input capacitance5pF(1)Figure3and Figure4show dc test setup.ELECTRICAL CHARACTERISTICS:Differential Input(1)At V CC=2.375V to3.6V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1216PARAMETER TEST CONDITIONS MIN TYP MAX UNITf IN Input frequency Clock input2000MHzf IN≤1.5GHz0.1 1.5VV IN,DIFF,PP Differential input peak-peak voltage1.5GHz≤f IN≤2GHz0.2 1.5VV ICM Input common-mode level 1.0V CC–0.3VI IH Input high current V CC=3.6V,V IH=3.6V40μAI IL Input low current V CC=3.6V,V IL=0V–40μAΔV/ΔT Input edge rate20%to80% 1.5V/nsI CAP Input capacitance5pF(1)Figure5and Figure6show dc test setup.Figure7shows ac test setup.ELECTRICAL CHARACTERISTICS:LVPECL Output(1)At V CC=2.375V to2.625V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1216PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH Output high voltage V CC–1.26V CC–0.9VV OL Output low voltage V CC–1.7V CC–1.3VV OUT,DIFF,PP Differential output peak-peak voltage f IN≤2GHz0.5 1.35VV AC_REF Input bias voltage(2)I AC_REF=2mA V CC–1.6V CC–1.1VV IN,DIFF,PP=0.1V550pst PD Propagation delayV IN,DIFF,PP=0.3V550pst SK,PP Part-to-part skew150pst SK,O Output skew30psCrossing-point-to-crossing-point distortion,t SK,P Pulse skew(with50%duty cycle input)–5050psf OUT=100MHzf OUT=100MHz,V IN,SE=V CC,V th=1.25V,0.11ps,RMS10kHz to20MHzf OUT=100MHz,V IN,SE=0.9V,0.128ps,RMSV th=1.1V,10kHz to20MHzRandom additive jitter(with50%duty f OUT=2GHz,V IN,DIFF,PP=0.2V,t RJIT0.053ps,RMS cycle input)V ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=0.15V,0.093ps,RMSV ICM=1V,10kHz to20MHz(1)Figure8and Figure9show dc and ac test setup.(2)Internally generated bias voltage(V AC_REF)is for3.3-V operation only.It is recommended to apply externally generated bias voltage forV SS<3.0V.Copyright©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):CDCLVP1216CDCLVP1216SCAS877C–MAY2009–REVISED ELECTRICAL CHARACTERISTICS:LVPECL Output(1)(continued)At V CC=2.375V to2.625V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1216PARAMETER TEST CONDITIONS MIN TYP MAX UNITf OUT=100MHz,V IN,DIFF,PP=1V,0.092ps,RMSV ICM=1V,10kHz to20MHzt R/t F Output rise/fall time20%to80%200psI EE Supply internal current Outputs unterminated110mAI CC Output and internal supply current All outputs terminated,50Ωto V CC–2618mA ELECTRICAL CHARACTERISTICS:LVPECL Output(1)At V CC=3.0V to3.6V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1216PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH Output high voltage V CC–1.26V CC–0.9VV OL Output low voltage V CC–1.7V CC–1.3VV OUT,DIFF,PP Differential output peak-peak voltage f IN≤2GHz0.65 1.35VV AC_REF Input bias voltage I AC_REF=2mA V CC–1.6V CC–1.1VV IN,DIFF,PP=0.1V550pst PD Propagation delayV IN,DIFF,PP=0.3V550pst SK,PP Part-to-part skew150pst SK,O Output skew30psCrossing-point-to-crossing-point distortion,t SK,P Pulse skew(with50%duty cycle input)–5050psf OUT=100MHzf OUT=100MHz,V IN,SE=V CC,V th=1.65V,0.101ps,RMS10kHz to20MHzf OUT=100MHz,V IN,SE=0.9V,0.130ps,RMSV th=1.1V,10kHz to20MHzRandom additive jitter(with50%duty f OUT=2GHz,V IN,DIFF,PP=0.2V,t RJIT0.069ps,RMS cycle input)V ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=0.15V,0.094ps,RMSV ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=1V,0.094ps,RMSV ICM=1V,10kHz to20MHzt R/t F Output rise/fall time20%to80%200psI EE Supply internal current Outputs unterminated110mAI CC Output and internal supply current All outputs terminated,50Ωto V CC–2618mA(1)Figure8and Figure9show dc and ac test setup.4Submit Documentation Feedback Copyright©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1216CDCLVP1216V CC OUTP11O U T N 10O U T N 8O U T N 6O U T N 9O U T N 7O U T N 5OUTN11O U T P 10O U T P 8O U T P 6O U T P 9O U T P 7O U T P 5OUTP12OUTN12OUTP13OUTN13OUTP14OUTN14OUTP15OUTN15V CCV CC OUTN4OUTP4OUTN3OUTP3OUTN2OUTP2OUTN1OUTP1OUTN0OUTP0V CC123456789101112363534333231302928272625242322212019181716151413373839404142434445464748Thermal Pad(1)G N DI N _S E LI N P 1I N N 1N CV C CV C CV A C _R E FI N N 0I N P 0N CG N DCDCLVP1216SCAS877C –MAY 2009–REVISED AUGUST 2011RGZ PACKAGEQFN-48(TOP VIEW)(1)Thermal pad must be soldered to ground.Copyright ©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):CDCLVP1216CDCLVP1216SCAS877C–MAY2009–REVISED PIN DESCRIPTIONSCDCLVP1216Pin DescriptionsTERMINAL TERMINAL PULL-UP/NAME NO.TYPE PULLDOWN DESCRIPTION6,7,13,24,37,V CC Power— 2.5-/3.3-V supplies for the device48GND1,12Ground—Device groundsINP0,INN010,9Input—Differential input pair or single-ended input.Unused input pair can be left floating.INP1,INN13,4Input—Redundant differential input pair or single-ended input.Unused input pair can be left floating.OUTP15,46,47Output—Differential LVPECL output pair no.15.Unused output pair can be left floating.OUTN15OUTP14,44,45Output—Differential LVPECL output pair no.14.Unused output pair can be left floating.OUTN14OUTP13,42,43Output—Differential LVPECL output pair no.13.Unused output pair can be left floating.OUTN13OUTP12,40,41Output—Differential LVPECL output pair no.12.Unused output pair can be left floating.OUTN12OUTP11,38,39Output—Differential LVPECL output pair no.11.Unused output pair can be left floating.OUTN11OUTP10,35,36Output—Differential LVPECL output pair no.10.Unused output pair can be left floating.OUTN10OUTP9,33,34Output—Differential LVPECL output pair no.9.Unused output pair can be left floating.OUTN9OUTP8,31,32Output—Differential LVPECL output pair no.8.Unused output pair can be left floating.OUTN8OUTP7,29,30Output—Differential LVPECL output pair no.7.Unused output pair can be left floating.OUTN7OUTP6,27,28Output—Differential LVPECL output pair no.6.Unused output pair can be left floating.OUTN6OUTP5,25,26Output—Differential LVPECL output pair no.5.Unused output pair can be left floating.OUTN5OUTP4,22,23Output—Differential LVPECL output pair no.4.Unused output pair can be left floating.OUTN4OUTP3,20,21Output—Differential LVPECL output pair no.3.Unused output pair can be left floating.OUTN3OUTP2,18,19Output—Differential LVPECL output pair no.2.Unused output pair can be left floating.OUTN2OUTP1,16,17Output—Differential LVPECL output pair no.1.Unused output pair can be left floating.OUTN1OUTP0OUTN014,15Output—Differential LVPECL output pair no.0.Unused output pair can be left floating.PulldownIN_SEL2Input MUX select input for input choice(see Table3)(see Table2)Bias voltage output for capacitive coupled inputs.Do not use V AC_REF at V CC<3.0V.If V AC_REF8Output—used,it is recommended to use a0.1-μF capacitor to GND on this pin.The output current islimited to2mA.NC5,11——Do not connectTable2.Pin CharacteristicsPARAMETER MIN TYP MAX UNITSR PULLDOWN Input pulldown resistor150kΩTable3.Input Selection TableIN_SEL ACTIVE CLOCK INPUT0INP0,INN01INP1,INN16Submit Documentation Feedback Copyright©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP12160.20.40.60.81.01.21.41.62.01.8Frequency (GHz)1.00.90.80.70.60.50.4D i f f e r e n t i a l O u t p u t P e a k -t o -P e a k V o l t a g e (V)0.20.40.60.81.01.21.41.62.01.8Frequency (GHz)1.11.21.31.00.90.80.70.60.50.4D i f f e r e n t i a l O u t p u t P e a k -t o -P e a k V o l t a g e (V )CDCLVP1216SCAS877C –MAY 2009–REVISED AUGUST 2011TYPICAL CHARACTERISTICSAt T A =–40°C to +85°C (unless otherwise noted).DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGEvs FREQUENCYFigure 1.DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGEvs FREQUENCYFigure 2.Copyright ©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):CDCLVP1216VV V thV IHmaxV ILmaxV IHminV ILminV IHV ILV th V V V GNDV CCV V CDCLVP1216SCAS877C –MAY 2009–REVISED AUGUST 2011TEST CONFIGURATIONSThis section describes the function of each block for the CDCLVP1216.Figure 3through Figure 9illustrate how the device should be setup for a variety of test configurations.Figure 3.DC-Coupled LVCMOS Input During Device TestFigure 4.V th Variation over LVCMOS LevelsFigure 5.DC-Coupled LVPECL Input During Device Test8Submit Documentation FeedbackCopyright ©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1216V VCDCLVP1216 SCAS877C–MAY2009–REVISED AUGUST2011 Figure6.DC-Coupled LVDS Input During Device TestFigure7.AC-Coupled Differential Input to DeviceFigure8.LVPECL Output DC Configuration During Device TestFigure9.LVPECL Output AC Configuration During Device TestCopyright©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):CDCLVP1216OUTPxOUTNxV OHV OL VOD)´INPx INNx OUTP0OUTN0OUTP1OUTN1OUTP2OUTN2OUTP15OUTN15CDCLVP1216SCAS877C –MAY 2009–REVISED AUGUST 2011Figure 10shows the output voltage and rise/fall time.Output and part-to-part skew are shown in Figure 11.Figure 10.Output Voltage and Rise/Fall Time(1)Output skew is calculated as the greater of the following:As the difference between the fastest and the slowest t PLHn (n =0,1,2....15),or as the difference between the fastest and the slowest t PHLn (n =0,1,2....15).(2)Part-to-part skew is calculated as the greater of the following:As the difference between the fastest and the slowest t PLHn (n =0,1,2....15)across multiple devices,or the difference between the fastest and the slowest t PHLn (n =0,1,2....15)across multiple devices.Figure 11.Output and Part-to-Part Skew10Submit Documentation FeedbackCopyright ©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1216分销商库存信息:TICDCLVP1216RGZT CDCLVP1216RGZR CDCLVP1216EVM。