通用接口光电编码器电路

The Design and Implementation of Universal Interface Circuit for Photoelectric EncoderDa Li, Hui Zhao, Honglin Xue, An ZouSchool of AstronauticsHarbin Institute of TechnologyHarbin, Heilongjiang Province, 150001, Chinazhaohui@Abstract - The majority of encoder signal process circuits only support one type of the specific photoelectric encoder, either absolute encoder or incremental encoder. In order to realize the compatibility for both two types of encoders simultaneously, a novel encoder signal process circuit based on FPGA is presented in this paper. Firstly, a series of universal functions are analyzed and demonstrated. On this basis, the approaches on multiplexing interfaces is designed and verified by simulation. Importantly, the compatibility is solved by multiplexing pins of the IC chip in terms of the hardware interface. As for the software interface, FPGA internal signal acquisition and processing programs deal with the different encoder protocols. Finally, two different types of encoders are concurrently connected to the circuit for system testing. The result indicates that the real-time angular position curve is smooth and the measured angle value is accurately displayed on the host computer. Consequently, the stability and compatibility are successfully proven. Besides, those expensive dedicated interface circuits could be replaced by the proposed circuit, as well as the costs can be significantly reduced. The circuit is ideal for applications requiring high resolution and fast data acquisition in industrial control fields.Index Terms - Photoelectric encoder, signal process circuit, EnDat or SSI interface, FPGAI.I NTRODUCTIONDigital drive systems and feedback loops always require fast data transfer with high system reliability from the position sensors [1].Due to high resolution and precision, excellent quality, simple connection and cost optimization, photoelectric encoders are widely applied in radar, turntable, robotics, CNC machine tool and other high precision servo control systems.Depending on differences of the working principle and output signals, generally, photoelectric encoders are mainly divided into two types: Absolute encoders and incremental encoders. As with the output encoder signals, absolute encoders always output serial Gray codes or BCD output as certain communication protocol. And incremental encoders output two-phase square wave pulses, which the number of pulses means the displacement and the phase difference indicates the direction of rotation. Fig.1 shows the coded disk patterns of the incremental encoder and absolute encoder. Therefore, the photoelectric encoder interfaces require the corresponding subsequent electronic equipment to receive and process the output encoder signals, for the host computer or the servo motor in close-loop systems. Generally, most encoder signal process circuits could only handle with one type of the specific encoder interface, i.e., either the absolute encoder or the incremental encoder.In recent years, encoder manufacturers have developed their dedicated encoder signal process circuits, which could convert the serial output data of the encoder into parallel data for motor drive or controller. For instance, the famous German Corporation HEIDENHAIN has a world-wide high reputation for producing encoders with high precision in the field of position measurement. The interpolation and counter card IK220 is designed by HEIDENHAIN. It could support two protocols including EnDat and SSI and its current version only supports up to two channels of encoders. However, it lacks functions of the conversion from the Gray code to BCD. Tosome degree, such circuits are too expensive [2].Fig. 1 Coded disk patterns of the incremental encoder and absolute encoder Therefore, if one single hardware interface for both absolute and incremental encoders can be accomplished, by multiplexing pins for the differential signals, the versatility will be much enhanced. What’s more, some early-designed circuits are quite large and complicated, meanwhile, along with the defects of more power consumption and poor reliability [3].Thus, utilizing FPGA instead of discrete electric components will be more preferable and efficient.The encoder interface protocols mainly comprise EnDat or SSI protocol for absolute encoders, as well as quadrature signals for incremental encoders. For instance, SSI is one digital bidirectional protocol, which supplies the absolute position value in synchrony with one clock pulse from the subsequent circuit. When the resolution of the encoder is determined, the number of transmitting pulses per clock cycle is also fixed. Furthermore, EnDat interface is greatly improved based on SSI. Fig.2 is the data transmission timing diagram of EnDat 2.1. It is capable of transmitting position values from absolute encoders, updating information stored in the encoder,Proceeding of the 11th World Congress on Intelligent Control and Automation Shenyang, China, June 29 - July 4 2014Fig. 2 Data transmission timing diagram of Protocol EnDat 2.1and saving new information. Because of serial transmission method, only four signal lines are required [4]. It is apparent that the EnDat interface has the higher system reliability and more simple connection. As to incremental encoder interface, its output differential signals consist of signal A, B and index signal Z, as presented in Fig.3. Signal A and B are quadrature square waves, whose phase difference is 90 degrees, are for counting and signing the direction of rotation. The absolute zero position is marked by index signal Z per revolution. Moreover, t he function ofclearing and resetting the counter for calibration could beaccomplished by signal Z.Fig. 3 Output waveforms of signals A, B and Z of the incremental encoderIn a word, to overcome these restrictions, it is essential to develop a universal signal process circuit compatible with both absolute encoder and incremental encoder.II. D ESIGN OF T HE M ULTIPLEXING I NTERFACESA. Demonstration of the Universal FunctionsThe versatility, compatibility and stability of the encoder signal process circuit in the engineering applications should be considering about. After demonstration, this paper identifies following functions that the circuit should implement:Firstly, multi-channel signal acquisition and processing should be applied in multi-DOF position measurement and speed measurement, such as multi-axis servo turntable, dexterous robot hand joints and other servo systems, so it is necessary to be compatible with both absolute encoder and incremental encoder simultaneously.Then, the word length of encoding value should be adjustable, according to the accuracy requirement and the type of the encoder. For incremental encoders, the word length is set as 24 bits so as to be read as three bytes. As for the absolute encoder, due to the specific product model, the word length should be ranged from 11 to 26 bits. Therefore, this function could satisfy the majority of the encoder applications.When the encoder is used as angle sensor for the motor, the circuit needs to be able to give real-time parallel angular position value for the drive to read. Since 12-bit angular position value has a resolution reached 5.27' to meet most requirements. Thereby, each channel should output high 12-bit parallel angular position value for motor drive.In addition, most absolute encoders directly adopt the BCD output after internal conversion, but some old-fashioned absolute encoders still directly output Gray code. It is essential to support the conversion from Gray code into BCD output. B. Approaches on Multiplexing Interfaces The problem of the compatibility is solved by sharing the common pins of the IC chip MAX485, for differential signals from encoder and single-ended signals from FPGA. Thus, approaches on multiplexing the interfaces are described as follows.As shown in Fig.4, data signals DATA_ENCODER_i (i=1,2,3) of the absolute encoder are multiplexed with the corresponding quadrature signal A of the incremental encoder, respectively. When the absolute encoder is connected to the circuit, the direction of data signal is determined by the enable signal OUTPUT_EN_i (i=1, 2, 3). If it is high, the mode command is transmitted from the subsequent circuit to the encoder. Otherwise, if it is low, the data transmission is conducted from the encoder to the subsequent circuit. On the other hand, while the incremental encoder is connected to circuit, the phase A or index Z signal are only received from the encoder instead of sending. Therefore, the enable signal is always low.Similarly, clock signals CLOCK_ENCODER_i (i = 1,2,3) of absolute encoder are multiplexed with the corresponding quadrature signal B of incremental encoder, respectively, as shown Fig.5. However, it is worth pointing out that signalline is always unidirectional with absolute encoder. Since the clock signal is only transmitted from the subsequent circuit to the encoder, hence, the enable signal is alwayshigh. While the incremental encoder is accessed, the phase B or index Z signal are only received from the encoder instead of delivering, so the enable signal is always low.It is clear that the approach mentioned above could resolve the compatibility for both two different interfaces. Fig. 4 Data signal DATA_ENCODER_1 of absolute encoder multiplexeswith signal A of incremental encoderFig. 5 Clock signal CLOCK_ENCODER_1 of absolute encoder multiplexeswith signal B of incremental encoderIII.E NCODER S IGNAL A CQUISITION A ND P ROCESSIn this paper, the encoder signal acquisition and process plays a significant role throughout the FPGA internal logic design. It could be divided into two sections including absolute encoder section and incremental encoder section. And each section could be classified into several modules with the corresponding functions.The former section is composed of clock and reset signal generator module, start/alarm/warning bit check module, receiving/sending module, serial to parallel codes converter module, Gray code to binary code converter module, etc. On the other hand, the latter section consists of digital filter module, frequency multiplier and phase detector module, 24-bit counter and 24-bit latch module, etc. Furthermore, the enable signals are generated and transmitted from the FPGA internal logic control module to other modules else. The schematic diagram of the signal acquisition and process is shown in Fig.6.A. Absolute Encoder SectionThe main modules of absolute encoder section among the FPGA internal logic schematic diagram are illustrated below: FPGA internal logic control module: It is the core control module both in the absolute encoder module and incremental encoder module. The main function is to set and reset enable signals that control other modules, via the value of synchronous clock counter, at different time nodes within one data transmission cycle. What’s more, each module is separately triggered according to the corresponding logical sequence, respectively, along with the requirement of the interface protocol. Accordingly, the accuracy of timing sequence within the data transmission is ensured.Clock and reset signal generator module: The frequencyof system clock requires to be divided. The clock pulse is transmitted to the encoder and the FPGA on circuit, respectively, to synchronize the data transmission. On the other hand, the counters, registers and enable signals of other modules need to be reset at the beginning of each transmission cycle.Receiving/Sending module: The identification of encoder interface is mainly completed by receiving module. The sending module is divided into two parts: one is to achieve parallel communication with the host computer via the ISA bus, the other one is to output high 12-bit parallel angular position for each channel to the motor drive.Start/warning/error bit parity module: This module is only employed for protocol EnDat 2.1/2.2, to validate whether the error bit is normal after the encoder delivers the start bit[5]. If the test is correct, then the serial-to-parallel converter is prepared to start; otherwise, the recovery time is immediately activated until the next transmission cycle.Serial-to-parallel/parallel-to-serialconvertermodule:The serial-to-parallel module is to convert the serial data into parallel data. Meanwhile, the parallel-to-serial module is only used for 8-bit parallel mode commands from host computer tobe converted into serial data, then to be sent to the encoder.B. Incremental Encoder SectionTo extract the effective signals from the input and realize the output accurately and stably, three feasible solutions are presented for this purpose: a reasonable digital filter, an effective frequency multiplier and phase detector and an accurate counting.Digital filter module: As to the orthogonal signal, the rising and falling edges of phase A and B are the key moment, which are highly sensitive to noise and disturbance[6]. The ability of eliminating jitter and noise in conventional circuits is quite poor. Therefore, it is in urgent need to be solved. Due to the causes mentioned above, such digital filter module requires to be added to filter out glitches. The insensitivity to noise can be strengthened. In our implementation, its basic thought is that if the input signals sampled by three successive sampling times are identical, so then the output would be regarded as stable and effective. It is worth pointing out that the filter clock cycle could be set by host computer, which greatly increases the flexibility and scalability.Frequency multiplier and phase detector module: There are four changes of the phase A and B signal within one signal period. Namely, it turns out to be four bounces of rising and falling edges. Thus, the input signals are disposed of four-fold frequency, so that the encoder can be increased quadruple revolution [7]. Although the signal period is uncertain, the phase difference between phase A and B signal is always 90 degrees. So the direction of rotation can be discriminated and signed by this characteristic. It is the most direct and effective way to increase the resolution of the encoder.Fig. 6 FPGA internal logic schematic diagramCounter and latch module: The output counting pulses are transmitted to the next 24-bit reversible counter. The reason why the counter digit is determined as 24 bits is that it can be exactly divided into three 8-bit latches for high, medium and low bytes, respectively. What’s more, 24 bits could meet the general encoding requirements of most encoders with the corresponding revolution. Whether the positive counting or negative counting depend on the direction signal from the phase detector module.In summary, the detailed FPGA internal logic modules are described above in detail. It is worth mentioning that several modules are common and reused for both absolute encoders and incremental encoders.IV. S IMULATION W AVEFORMSVerilog HDL is chosen as the programming language and functional and timing simulation is conducted on Quartus II platform. After that the accuracy of functions for each sub module has been verified, the synthetic simulation and timing analysis are preceded, along with the comprehensive inspection of versatility. According to the corresponding settings, main enable signals, clock signals and other data signals can be apparently observed from the simulation waveforms. The simulation waveforms are shown in Fig.7 and Fig.8, respectively, for encoders with different interfaces connected to each channel.Fig. 7 Simulation waveform of incremental interfaceFig. 8 Simulation waveform of EnDat2.2 interfaceFinally, the correctness of FPGA internal hardware logic design is validated, by the comprehensive simulation results under a variety of circumstances, to guarantee the next stage of debugging.V. S YSTEM T EST A ND R ESULT A NALYSISFirst, the parameter settings demand to be initialized on the host computer, including the base address of the ISA card, encoder number, encoder type, lines of incremental encoder, resolution of position value bits, etc. Other than those, the PC control program is supposed to be designed to realize the communication between the host computer and the circuit. After the program runs, the curve of angular position value will be presented in real time.The 17-bit absolute encoder ROC417 with EnDat 2.1 interface is adopted for the test. The output waveforms of the clock signal (A wave) and the data signal (B wave) via the ScopeMeter, as is shown in Fig.9. What’s more, Fig.10 shows the angular position curve when ROC417 is connected to the circuit. Obviously, angular position curve can be observed smoothly, as well as the output real-time angular positionvalue can be read out from the corresponding frame.Fig.9 Output waveforms of clock signal and data signalof ROC417 on ScopeMeterThe data transmission cycle is described as below. It is indicated the data transmission begins when the clock signal becomes low, as well as the enable signal OUTPUT_EN is pulled high. From the waveform, it can be observed that after two waiting clock periods, the 6-bit mode command “000111” is sent from FPGA to the encoder. Subsequently, after another three waiting clock periods, the OUTPUT_EN is reset andremains low during the rest of the cycle. Then, the data frame "11-11011100101111010-01100-1" will be transmitted from the encoder to the circuit. It should be noted that the first two bits "11", respectively, are performed as the start and warning bit, which satisfy the start/warning/error bit parity of EnDat 2.2 interface. Then, the following "11011100101111010" is the 17-bit angular position code and the subsequent 5 bits "01100" is its CRC code; finally data signal is pulled high to indicate the end of the transmission.Incremental encoders are mostly applied for calculating the number of pulses per signal period to gain speed; therefore, the accumulative counting should be actualized. Moreover, whether to access the index signal Z depends on the specific applications. Fig.11 shows the output curve of angular position without Z signal for multi-turn rotation. If without signal Z, the angular position value will be still accumulated and counted while exceeding 360 degrees. However, it will be cleared or reset until the counter exceeds 0xFFFFFF to be overflowed.Fig.10 Curve of measured angle with ROC417Otherwise, if the index Z signal is accessed, the angular position value will be reset as 0 degree, whenever the encoder runs forward to 360 degree. Similarly, it will be also settled as 360 degrees whenever the encoder rotates backward to 0 degree. Fig.12 shows the curve of the measured angle value with the index Z signal, when the encoder is in unidirectional rotating. As is shown, the function of clearing and resetting themeasured angle value within 360 degrees by the index Z signal has been validated. In a word, the compatibility for supporting both absolute encoder and incremental encoder concurrently isimplemented successfully.Fig.11 Curve of measured angle with multi-turn rotation(Without Index Z signal)Fig.12 Curve of measured angle with unidirectional rotating(With Index Z signal)VI. C ONCLUSIONIn this paper, one universal signal process circuit based on FPGA for photoelectric encoder has been designed and implemented. Especially, the proposed circuit is able to support both absolute encoder and incremental encoder concurrently. On one hand, the compatibility is solved by multiplexing pins of the IC chip MAX485. The expansion of the system could be enhanced by those FPGA pins saved by multiplexing. On the other hand, the circuit can be upgraded by modifying the FPGA internal program, instead of changing the hardware circuit structure. What’s more, the disturbance and noise can be effectively eliminated to minimize the measuring errors. Therefore, the limitation that most circuits could only support one dedicated type of encoders has been broken through.Finally, the performance of the circuit is evaluated and validated via the system test. The result obtained from the experiment is almost consistent with the simulation above. Furthermore, this design has merits of more compact structure, lower power consumption, faster speed of signal processing and more stable operation. Consequently, those expensive dedicated interface circuits could be replaced by the proposed circuit in the future, as well as the costs can be significantly reduced. The circuit is ideal for applications requiring high resolution and fast data acquisition in multi-DOF position measurement such as multi-axis servo turntable, dexterous robot hand joints and other servo control systems.R EFERENCE[1] Huang Liangdong, Chen Guilin,Wang Ganquan, “Acquisition methodsfrom precision optical encoder under protocol EnDat,” Optical Technology , Vol. 31, 2005, pp. 192-194.[2] HEIDENHAIN Corporation, “IK 220 PC Counter Card User's Manual,”/fileadmin/pdb/media/img/339_904-26.pdf, 2012.[3] Du Libin, Sun Jichang, Liu Yan, Cheng yan, “Design of Multi-channelEncoder Interface Card Based on FPGA,” Proceedings of the First International Symposium on Test Automation & Instrumentation , vol. 1, 2006, pp. 515-517.[4] Dr. Johannes Heidenhain, “EnDat 2.2 Bidirectional Interface for PositionEncoders Technical Information,” 2008,/fileadmin/pdb/media/img/383-942-24.pdf. [5] Wang, Ming-Shyan; Kung, Ying-Shieh; Lin, Tsung-Ting; Tu, Yi-Ming,“FPGA-Based Interpolation for Motor Encoders,” Sensor Letters , vol. 10, May 2012, pp. 1142-1148.[6] Ching-Hwa Ho, Ji-Hsien Ho, “Practical and User-Friendly Circuits andSystem Design for Signals’ Sensing and Generation,” Circuits and Systems , vol. 4, 2013, pp. 387-392.[7] Xia Jiakuan, Li Xiaofan, “FPGA-based communication interface designof absolute encoder RCN223,” Micromotors , vol. 43, 2010, pp. 54-56.。