AD9826中文资料

COP8SG Family8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory,Two Comparators and USARTGeneral DescriptionThe COP8SG Family ROM and OTP based microcontrollers are highly integrated COP8™Feature core devices with 8k to 32k memory and advanced features including Analog comparators,and zero external components.These single-chip CMOS devices are suited for more complex applica-tions requiring a full featured controller with larger memory,low EMI,two comparators,and a full-duplex USART.COP8SGx7devices are 100%form-fit-function compatible OTP (One Time Programmable)versions for use in produc-tion or development of the COP8SGx5ROM.Erasable windowed versions (Q3)are available for use with a range of COP8software and hardware development tools.Family features include an 8-bit memory mapped architec-ture,15MHz CKI with 0.67µs instruction cycle,14inter-rupts,three multi-function 16-bit timer/counters with PWM,full duplex USART,MICROWIRE/PLUS ™,two analog com-parators,two power saving HALT/IDLE modes,MIWU,idle timer,on-chip R/C oscillator,high current outputs,user se-lectable options (WATCHDOG ™,4clock/oscillator modes,power-on-reset),2.7V to 5.5V operation,program code se-curity,and 28/40/44pin packages.Devices included in this datasheet are:Device Memory (bytes)RAM (bytes)I/O Pins Packages Temperature COP8SGE58k ROM 25624/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGG516k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGH520k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGK524k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGR532k ROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGE78k OTP EPROM 25624/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGR732k OTP EPROM 51224/36/4028DIP/SOIC,40DIP ,44PLCC/QFP/CSP -40to +85˚C,-40to +125˚C COP8SGR7-Q332k EPROM51224/36/4028DIP ,40DIP ,44PLCCRoom Temp.Key Featuresn Low cost 8-bit microcontrollern Quiet Design (low radiated emissions)n Multi-Input Wakeup pins with optional interrupts (8pins)nMask selectable clock options —Crystal oscillator—Crystal oscillator option with on-chip bias resistor —External oscillator —Internal R/C oscillatorn Internal Power-On-Reset —user selectablen WATCHDOG and Clock Monitor Logic —user selectable n Eight high current outputsn 256or 512bytes on-board RAMn8k to 32k ROM or OTP EPROM with security featureCPU Featuresn Versatile easy to use instruction set n 0.67µs instruction cycle timen Fourteen multi-source vectored interrupts servicing —External interrupt /Timers T0—T3—MICROWIRE/PLUS Serial Interface —Multi-Input Wake Up —Software Trap—USART (2;1receive and 1transmit)—Default VIS (default interrupt)n 8-bit Stack Pointer SP (stack in RAM)n Two 8-bit Register Indirect Data Memory Pointers n True bit manipulationn BCD arithmetic instructionsPeripheral Featuresn Multi-Input Wakeup Logicn Three 16-bit timers (T1—T3),each with two 16-bit registers supporting:—Processor Independent PWM mode —External Event Counter mode —Input Capture modeCOP8™is a trademark of National Semiconductor Corporation.October 2001COP8SG Family,8-Bit CMOS ROM Based and OTP Microcontrollers with 8k to 32k Memory,Two Comparators and USART©2001National Semiconductor Corporation Peripheral Features(Continued)n Idle Timer (T0)n MICROWIRE/PLUS Serial Interface (SPI Compatible)n Full Duplex USARTnTwo Analog ComparatorsI/O Featuresn Software selectable I/O options (TRI-STATE ®Output,Push-Pull Output,Weak Pull-Up Input,and High Impedance Input)n Schmitt trigger inputs on ports G and L n Eight high current outputsn Packages:28SO with 24I/O pins,40DIP with 36I/O pins,44PLCC,PQFP and CSP with 40I/O pinsFully Static CMOS Designn Low current drain (typically <4µA)n Two power saving modes:HALT and IDLETemperature Rangen −40˚C to +85˚C,−40˚C to +125˚CDevelopment Supportn Windowed packages for DIP and PLCCn Real time emulation and debug tools availableBlock Diagram10131744FIGURE 1.COP8SGx Block DiagramC O P 8S G F a m i l y 21.0Device Description1.1ARCHITECTUREThe COP8family is based on a modified Harvard architec-ture,which allows data tables to be accessed directly from program memory.This is very important with modern microcontroller-based applications,since program memory is usually ROM or EPROM,while data memory is usually RAM.Consequently data tables need to be contained in non-volatile memory,so they are not lost when the micro-controller is powered down.In a modified Harvard architec-ture,instruction fetch and memory data transfers can be overlapped with a two stage pipeline,which allows the next instruction to be fetched from program memory while the current instruction is being executed using data memory. This is not possible with a Von Neumann single-address bus architecture.The COP8family supports a software stack scheme that allows the user to incorporate many subroutine calls.This capability is important when using High Level Languages. With a hardware stack,the user is limited to a small fixed number of stack levels.1.2INSTRUCTION SETIn today’s8-bit microcontroller application arena cost/ performance,flexibility and time to market are several of the key issues that system designers face in attempting to build well-engineered products that compete in the marketplace. Many of these issues can be addressed through the manner in which a microcontroller’s instruction set handles process-ing tasks.And that’s why COP8family offers a unique and code-efficient instruction set—one that provides the flexibil-ity,functionality,reduced costs and faster time to market that today’s microcontroller based products require.Code efficiency is important because it enables designers to pack more on-chip functionality into less program memory space.Selecting a microcontroller with less program memory size translates into lower system costs,and the added security of knowing that more code can be packed into the available program memory space.1.2.1Key Instruction Set FeaturesThe COP8family incorporates a unique combination of in-struction set features,which provide designers with optimum code efficiency and program memory utilization.Single Byte/Single Cycle Code ExecutionThe efficiency is due to the fact that the majority of instruc-tions are of the single byte variety,resulting in minimum program space.Because compact code does not occupy a substantial amount of program memory space,designers can integrate additional features and functionality into the microcontroller program memory space.Also,the majority instructions executed by the device are single cycle,result-ing in minimum program execution time.In fact,77%of the instructions are single byte single cycle,providing greater code and I/O efficiency,and faster code execution.1.2.2Many Single-Byte,Multifunction InstructionsThe COP8instruction set utilizes many single-byte,multi-function instructions.This enables a single instruction to accomplish multiple functions,such as DRSZ,DCOR,JID, LD(Load)and X(Exchange)instructions with post-incrementing and post-decrementing,to name just a fewexamples.In many cases,the instruction set can simulta-neously execute as many as three functions with the samesingle-byte instruction.JID:(Jump Indirect);Single byte instruction;decodes exter-nal events and jumps to corresponding service routines(analogous to“DO CASE”statements in higher level lan-guages).LAID:(Load Accumulator-Indirect);Single byte look up tableinstruction provides efficient data path from the programmemory to the CPU.This instruction can be used for tablelookup and to read the entire program memory for checksumcalculations.RETSK:(Return Skip);Single byte instruction allows returnfrom subroutine and skips next instruction.Decision tobranch can be made in the subroutine itself,saving code.AUTOINC/DEC:(Auto-Increment/Auto-Decrement);Theseinstructions use the two memory pointers B and X to effi-ciently process a block of data(analogous to“FOR NEXT”inhigher level languages).1.2.3Bit-Level ControlBit-level control over many of the microcontroller’s I/O portsprovides a flexible means to ease layout concerns and saveboard space.All members of the COP8family provide theability to set,reset and test any individual bit in the datamemory address space,including memory-mapped I/O portsand associated registers.1.2.4Register SetThree memory-mapped pointers handle register indirect ad-dressing and software stack pointer functions.The memorydata pointers allow the option of post-incrementing or post-decrementing with the data movement instructions(LOAD/EXCHANGE).And15memory-maped registers allow de-signers to optimize the precise implementation of certainspecific instructions.1.3EMI REDUCTIONThe COP8SGx5family of devices incorporates circuitry thatguards against electromagnetic interference—an increasingproblem in today’s microcontroller board designs.National’spatented EMI reduction technology offers low EMI clockcircuitry,gradual turn-on output drivers(GTOs)and internalICCsmoothing filters,to help circumvent many of the EMI issues influencing embedded control designs.National hasachieved15dB–20dB reduction in EMI transmissions whendesigns have incorporated its patented EMI reducing cir-cuitry.1.4PACKAGING/PIN EFFICIENCYReal estate and board configuration considerations demandmaximum space and pin efficiency,particularly given today’shigh integration and small product form factors.Microcon-troller users try to avoid using large packages to get the I/Orge packages take valuable board space andincreases device cost,two trade-offs that microcontrollerdesigns can ill afford.The COP8family offers a wide range of packages and do notwaste pins:up to90.9%(or40pins in the44-pin package)are devoted to useful I/O.COP8SGFamily3Connection Diagrams10131704Top ViewOrder Number COP8SGXY28M8See NS Package Number M28B Order Number COP8SGXY28N8See NS Package Number N28B Order Number COP8SGR728Q3See NS Package Number D28JQ10131753Top ViewOrder Number COP8SGR7HLQ8See NS Package Number LQA44A10131705Top ViewOrder Number COP8SGXY40N8See NS Package Number N40A Order Number COP8SGR5740Q3See NS Package Number D40KQ10131706Top ViewOrder Number COP8SGXY44V8See NS Package Number V44A Order Number COP8SGR744J3See NS Package Number EL44C10131743Top ViewOrder Number COP8SGXYVEJ8See NS Package Number VEJ44ANote 1:X =E for 8k,G for 16k,H for 20k,K for 24k,R for 32k Y =5for ROM,7for OTPC O P 8S G F a m i l y 4Pinouts for28-,40-and44-Pin PackagesPort Type Alt.Fun 28-PinSO40-Pin DIP44-PinPLCC44-Pin PQFP44-Pin CSPL0I/O MIWU1117171112 L1I/O MIWU or CKX1218181213 L2I/O MIWU or TDX1319191314 L3I/O MIWU or RDX1420201415 L4I/O MIWU or T2A1521251920 L5I/O MIWU or T2B1622262021 L6I/O MIWU or T3A1723272122 L7I/O MIWU or T3B1824282223 G0I/O INT2535393334 G1I/O WDOUT*2636403435 G2I/O T1B2737413536 G3I/O T1A2838423637 G4I/O SO1334142 G5I/O SK2444243 G6I SI3554344 G7I CKO466441 D0O1925292324 D1O2026302425 D2O2127312526 D3O2228322627 D4O29332728 D5O30342829 D6O31352930 D7O32363031 F0I/O79934 F1I/O COMP1IN−8101045 F2I/O COMP1IN+9111156 F3I/O COMP1OUT10121267 F4I/O COMP2IN−131378 F5I/O COMP2IN+141489 F6I/O COMP2OUT1515910 F7I/O16161011 C0I/O39433738 C1I/O40443839 C2I/O113940 C3I/O224041 C4I/O211516 C5I/O221617 C6I/O231718 C7I/O241819 VCC68823 GND2333373132 CKI I57712 RESET I2434383233 *G1operation as WDOUT is controlled by ECON bit2.COP8SG Family 52.1Ordering Information10131708FIGURE 2.Part Numbering SchemeC O P 8S G F a m i l y 63.0Electrical CharacteristicsAbsolute Maximum Ratings(Note2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage(V CC)7VVoltage at Any Pin−0.3V to V CC+0.3VTotal Current into V CCPin(Source)100mATotal Current out ofGND Pin(Sink)110mAStorage TemperatureRange−65˚C to+140˚CESD Protection Level2kV(Human BodyModel) Note2:Absolute maximum ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.DC Electrical Characteristics−40˚C≤T A≤+85˚C unless otherwise specified.Parameter Conditions Min Typ Max Units Operating Voltage 2.7 5.5V Power Supply Rise Time1050x106ns V CC Start Voltage to Guarantee POR00.25V Power Supply Ripple(Note4)Peak-to-Peak0.1V cc V Supply Current(Note5)CKI=15MHz V CC=5.5V,t C=0.67µs9.0mA CKI=10MHz V CC=5.5V,t C=1µs 6.0mA CKI=4MHz V CC=4.5V,t C=2.5µs 2.1mA HALT Current(Note6)V CC=5.5V,CKI=0MHz<410µA IDLE Current(Note5)CKI=15MHz V CC=5.5V,t C=0.67µs 2.25mA CKI=10MHz V CC=5.5V,t C=1µs 1.5mA CKI=4MHz V CC=4.5V,t C=2.5µs0.8mA Input Levels(V IH,V IL)RESETLogic High0.8V cc V Logic Low0.2V cc V CKI,All Other InputsLogic High0.7V cc V Logic Low0.2V cc V Internal Bias Resistor for theCrystal/Resonator Oscillator0.512MΩCKI Resistance to V CC or GND when R/COscillator is selectedV CC=5.5V5811kΩHi-Z Input Leakage V CC=5.5V−2+2µA Input Pullup Current V CC=5.5V,V IN=0V−40−250µA G and L Port Input Hysteresis V CC=5.5V0.25V cc V COP8SG Family 7DC Electrical Characteristics(Continued)−40˚C ≤T A ≤+85˚C unless otherwise specified.ParameterConditionsMinTypMaxUnitsOutput Current Levels D Outputs Source V CC =4.5V,V OH =3.3V −0.4mA V CC =2.7V,V OH =1.8V -0.2mA Sink V CC =4.5V,V OL =1.0V 10mA V CC =2.7V,V OL =0.4V 2mA All OthersSource (Weak Pull-Up Mode)V CC =4.5V,V OH =2.7V −10.0−110µA V CC =2.7V,V OH =1.8V -2.5-33µA Source (Push-Pull Mode)V CC =4.5V,V OH =3.3V −0.4mA V CC =2.7V,V OH =1.8V -0.2mA Sink (Push-Pull Mode)V CC =4.5V,V OL =0.4V V CC =2.7V,V OL =0.4V 1.60.7mA mA TRI-STATE LeakageV CC =5.5V−2+2µA Allowable Sink Current per Pin (Note 9)D Outputs and L0to L315mA All Others3mA Maximum Input Current without Latchup (Note 7)Room Temp.±200mA RAM Retention Voltage,Vr 2.0V V CC Rise Time from a V CC ≥2.0V (Note 10)12µsEPROM Data Retenton (Note 8),(Note 9)T A =55˚C >29years Input Capacitance (Note 9)7pF Load Capacitance on D2(Note 9)1000pFAC Electrical Characteristics−40˚C ≤T A ≤+85˚C unless otherwise specified.ParameterConditionsMin Typ Max Units Instruction Cycle Time (t C )Crystal/Resonator,External 4.5V ≤V CC ≤5.5V 0.67µs 2.7V ≤V CC ≤4.5V 2µsR/C Oscillator (Internal) 4.5V ≤V CC ≤5.5V 2µs Frequency Variation (Note 9) 4.5V ≤V CC ≤5.5V ±35%External CKI Clock Duty Cycle (Note 9)fr =Max4555%Rise Time (Note 9)fr =10MHz Ext Clock 8ns Fall Time (Note 9)fr =10MHz Ext Clock5ns MICROWIRE Setup Time (t UWS )(Note 11)20ns MICROWIRE Hold Time (t UWH )(Note 11)56nsMICROWIRE Output Propagation Delay (t UPD )(Note 11)220nsInput Pulse Width (Note 9)Interrupt Input High Time 1t C Interrupt Input Low Time 1t C Timer 1,2,3,Input High Time 1t C Timer 12,3,Input Low Time 1t C Reset Pulse Width1µsNote 3:t C =Instruction cycle time.C O P 8S G F a m i l y 8AC Electrical Characteristics(Continued)Note4:Maximum rate of voltage change must be<0.5V/ms.Note5:Supply and IDLE currents are measured with CKI driven with a square wave Oscillator,External Oscillator,inputs connected to V CC and outputs driven low but not connected to a load.Note6:The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations.In the R/C configuration,CKI is forced high internally.In the crystal or external configuration,CKI is TRI-STATE.Measurement of I DD HALT is done with device neither sourcing nor sinking current;with L.F,C,G0,and G2–G5 programmed as low outputs and not driving a load;all outputs programmed low and not driving a load;all inputs tied to V CC;clock monitor disabled.Parameter refers to HALT mode entered via setting bit7of the G Port data register.Note7:Pins G6and RESET are designed with a high voltage input network.These pins allow input voltages>V CC and the pins will have sink current to V CC when biased at voltages>V CC(the pins do not have source current when biased at a voltage below V CC).The effective resistance to V CC is750Ω(typical).These two pins will not latch up.The voltage at the pins must be limited to<14V.WARNING:Voltages in excess of14V will cause damage to the pins.This warning excludes ESD transients.Note8:National Semiconductor uses the High Temperature Storage Life(HTSL)test to evaluate the data retention capabilities of the EPROM memory cells used in our OTP microcontrollers.Qualification devices have been stressed at150˚C for1000hours.Under these conditions,our EPROM cells exhibit data retention capabilities in excess of29years.This is based on an activation energy of0.7eV derated to55˚C.Note9:Parameter characterized but not tested.Note10:Rise times faster than the minimum specification may trigger an internal power-on-reset.Note11:MICROWIRE Setup and Hold Times and Propagation Delays are referenced to the appropriate edge of the MICROWIRE clock.See and the MICROWIRE operation description.Comparators AC and DC CharacteristicsV CC=5V,−40˚C≤T A≤+85˚C.Parameter Conditions Min Typ Max Units Input Offset Voltage(Note12)0.4V≤V IN≤V CC−1.5V±5±15mV Input Common Mode Voltage Range0.4V CC−1.5V Voltage Gain100dB Low Level Output Current V OL=0.4V−1.6mA High Level Output Current V OH=V CC−0.4V 1.6mA DC Supply Current per Comparator(When Enabled)150µAResponse Time(Note13)200mV step input100mV Overdrive,100pF Load600nsComparator Enable Time(Note14)600ns Note12:The comparator inputs are high impedance port inputs and,as such,input current is limited to port input leakage current.Note13:Response time is measured from a step input to a valid logic level at the comparator output.software response time is dependent of instruction execution. Note14:Comparator enable time is that delay time required between the end of the instruction cycle that enables the comparator and using the output of the comparator,either by hardware or by software.10131709FIGURE3.MICROWIRE/PLUS Timing COP8SG Family 9Absolute Maximum Ratings(Note 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V CC )7VVoltage at Any Pin −0.3V to V CC +0.3VTotal Current into V CC Pin (Source)100mA Total Current out of GND Pin (Sink)110mAStorage Temperature Range−65˚C to +140˚C ESD Protection Level2kV (Human BodyModel)Note 15:Absolute maximum ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.DC Electrical Characteristics−40˚C ≤T A ≤+125˚C unless otherwise specified.ParameterConditionsMin TypMax Units Operating Voltage 4.5 5.5V Power Supply Rise Time1050x 106ns V CC Start Voltage to Guarantee POR 00.25V Power Supply Ripple (Note 4)Peak-to-Peak0.1V ccVSupply Current (Note 5)CKI =10MHz V CC =5.5V,t C =1µs 6.0mA CKI =4MHz V CC =4.5V,t C =2.5µs 2.1mA HALT Current (Note 6)V CC =5.5V,CKI =0MHz<410µAIDLE Current (Note 5)CKI =10MHz V CC =5.5V,t C =1µs 1.5mA CKI =4MHz V CC =4.5V,t C =2.5µs0.8mAInput Levels (V IH ,V IL )RESET Logic High 0.8V ccV Logic Low 0.2V ccVCKI,All Other Inputs Logic High 0.7V ccV Logic Low0.2V ccV Internal Bias Resistor for the Crystal/Resonator Oscillator0.512M ΩCKI Resistance to V CC or GND when R/C Oscillator is selected V CC =5.5V 5811k ΩHi-Z Input Leakage V CC =5.5V−5+5µA Input Pullup CurrentV CC =5.5V,V IN =0V −35−400µA G and L Port Input Hysteresis V CC =5.5V0.25V ccVOutput Current Levels D Outputs Source V CC =4.5V,V OH =3.3V −0.4mA Sink V CC =4.5V,V OL =1.0V9mAAll OthersSource (Weak Pull-Up Mode)V CC =4.5V,V OH =2.7V −9−140µA Source (Push-Pull Mode)V CC =4.5V,V OH =3.3V −0.4mA Sink (Push-Pull Mode)V CC =4.5V,V OL =0.4V 1.4mA TRI-STATE LeakageV CC =5.5V−5+5µAAllowable Sink Current per Pin (Note 9)D Outputs and L0to L31515mA All Others33mAC O P 8S G F a m i l y 10DC Electrical Characteristics(Continued)−40˚C≤T A≤+125˚C unless otherwise specified.Parameter Conditions Min Typ Max UnitsMaximum Input Current without Latchup (Note7)Room Temp.±200mARAM Retention Voltage,Vr 2.0V V CC Rise Time from a V CC≥2.0V(Note10)12µs EPROM Data Retenton(Note8),(Note9)T A=55˚C>29years Input Capacitance(Note9)7pF Load Capacitance on D2(Note9)1000pF COP8SG FamilyAC Electrical Characteristics−40˚C ≤T A ≤+125˚C unless otherwise specified.ParameterConditionsMinTypMaxUnitsInstruction Cycle Time (t C )Crystal/Resonator,External 4.5V ≤V CC ≤5.5V 1µs R/C Oscillator (Internal) 4.5V ≤V CC ≤5.5V 2µs Frequency Variation (Note 9) 4.5V ≤V CC ≤5.5V ±35%External CKI Clock Duty Cycle (Note 9)fr =Max4555%Rise Time (Note 9)fr =10MHz Ext Clock 12ns Fall Time (Note 9)fr =10MHz Ext Clock8ns MICROWIRE Setup Time (t UWS )(Note 11)20ns MICROWIRE Hold Time (t UWH )(Note 11)56ns MICROWIRE Output Propagation Delay (t UPD )(Note 11)220nsInput Pulse Width (Note 9)Interrupt Input High Time 1t C Interrupt Input Low Time 1t C Timer 1,2,3,Input High Time 1t C Timer 12,3,Input Low Time 1t C Reset Pulse Width1µsComparators AC and DC CharacteristicsV CC =5V,−40˚C ≤T A ≤+125˚C.ParameterConditionsMinTypMaxUnits Input Offset Voltage (Note 12)0.4V ≤V IN ≤V CC −1.5V±5±25mV Input Common Mode Voltage Range 0.4V CC −1.5V Voltage Gain100dB Low Level Output Current V OL =0.4V −1.6mA High Level Output CurrentV OH =V CC −0.4V1.6mA DC Supply Current per Comparator (When Enabled)150µAResponse Time (Note 13)200mV step input 100mV Overdrive,600ns Comparator Enable Time600nsC O P 8S G F a m i l yTypical Performance Characteristics TA=25˚C(unless otherwise specified)10131749101317501013175110131752COP8SG Family4.0Pin DescriptionsThe COP8SGx I/O structure enables designers to reconfig-ure the microcontroller’s I/O functions with a single instruc-tion.Each individual I/O pin can be independently configured as output pin low,output high,input with high impedance or input with weak pull-up device.A typical example is the use of I/O pins as the keyboard matrix input lines.The input lines can be programmed with internal weak pull-ups so that the input lines read logic high when the keys are all open.With a key closure,the corresponding input line will read a logic zero since the weak pull-up can easily be overdriven.When the key is released,the internal weak pull-up will pull the input line back to logic high.This eliminates the need for external pull-up resistors.The high current options are avail-able for driving LEDs,motors and speakers.This flexibility helps to ensure a cleaner design,with less external compo-nents and lower costs.Below is the general description of all available pins.V CC and GND are the power supply pins.All V CC and GND pins must be connected.CKI is the clock input.This can come from the Internal R/C oscillator,external,or a crystal oscillator (in conjunction with CKO).See Oscillator Description section.RESET is the master reset input.See Reset description section.Each device contains four bidirectional 8-bit I/O ports (C,G,L and F),where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G),output or TRI-STATE under program control.Three data memory address locations are allocated for each of these I/O ports.Each I/O port has two associated 8-bit memory mapped registers,the CONFIGURATION register and the output DATA register.A memory mapped address is also reserved for the input pins of each I/O port.(See the memory map for the various addresses associated with the I/O ports.)Figure 4shows the I/O port configurations.The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown be-low:CONFIGURATIONRegisterDATA RegisterPort Set-Up00Hi-Z Input(TRI-STATE Output)01Input with Weak Pull-Up 10Push-Pull Zero Output 11Push-Pull One OutputPort L is an 8-bit I/O port.All L-pins have Schmitt triggers on the inputs.Port L supports the Multi-Input Wake Up feature on all eight pins.Port L has the following alternate pin functions:L7Multi-input Wakeup or T3B (Timer T3B Input)L6Multi-input Wakeup or T3A (Timer T3A Input)L5Multi-input Wakeup or T2B (Timer T2B Input)L4Multi-input Wakeup or T2A (Timer T2A Input)L3Multi-input Wakeup and/or RDX (USART Receive)L2Multi-input Wakeup or TDX (USART Transmit)L1Multi-input Wakeup and/or CKX (USART Clock)L0Multi-input WakeupPort G is an 8-bit port.Pin G0,G2–G5are bi-directional I/O ports.Pin G6is always a general purpose Hi-Z input.All pins have Schmitt Triggers on their inputs.Pin G1serves as thededicated WATCHDOG output with weak pullup if WATCHDOG feature is selected by the Mask Option reg-ister.The pin is a general purpose I/O if WATCHDOG feature is not selected.If WATCHDOG feature is selected,bit 1of the Port G configuration and data register does not have any effect on Pin G1setup.Pin G7is either input or output depending on the oscillator option selected.With the crystal oscillator option selected,G7serves as the dedicated output pin for the CKO clock output.With the internal R/C or the external oscillator option selected,G7serves as a gen-eral purpose Hi-Z input pin and is also used to bring the device out of HALT mode with a low to high transition on G7.Since G6is an input only pin and G7is the dedicated CKO clock output pin (crystal clock option)or general purpose input (R/C or external clock option),the associated bits in the data and configuration registers for G6and G7are used for special purpose functions as outlined below.Reading the G6and G7data bits will return zeroes.Each device will be placed in the HALT mode by writing a “1”to bit 7of the Port G Data Register.Similarly the device will be placed in the IDLE mode by writing a “1”to bit 6of the Port G Data Register.Writing a “1”to bit 6of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with the alter-nate phase of the SK clock.The G7configuration bit,if set high,enables the clock start up delay after HALT when the R/C clock configuration is used.Config.Reg.Data Reg.G7CLKDLY HALT G6Alternate SKIDLEPort G has the following alternate features:G7CKO Oscillator dedicated output or general purposeinputG6SI (MICROWIRE Serial Data Input)G5SK (MICROWIRE Serial Clock)G4SO (MICROWIRE Serial Data Output)G3T1A (Timer T1I/O)G2T1B (Timer T1Capture Input)G1WDOUT WATCHDOG and/or CLock Monitor if WATCH-DOG enabled,otherwise it is a general purpose I/O G0INTR (External Interrupt Input)Port C is an 8-bit I/O port.The 40-pin device does not have a full complement of Port C pins.The unavailable pins are not terminated.A read operation on these unterminated pins will return unpredictable values.The 28pin device do not offer Port C.On this device,the associated Port C Data and Configuration registers should not be used.Port F is an 8-bit I/O port.The 28--pin device does not have a full complement of Port F pins.The unavailable pins are not terminated.A read operation on these unterminated pins will return unpredictable values.Port F1–F3are used for Comparator 1.Port F4–F6are used for Comparator 2.The Port F has the following alternate features:F6COMP2OUT (Comparator 2Output)F5COMP2+IN (Comparator 2Positive Input)F4COMP2-IN (Comparator 2Negative Input)F3COMP1OUT (Comparator 1Output)F2COMP1+IN (Comparator 1Positive Input)F1COMP1-IN (Comparator 1Negative Input)C O P 8S G F a m i l y。

Triple Differential Driverfor Wideband VideoAD8146/AD8147/AD8148 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.FEATURESTriple high speed fully differential driver700 MHz, −3 dB, 2 V p-p bandwidth (AD8146/AD8148) 600 MHz, −3 dB, 2 V p-p bandwidth (AD8147)200 MHz, 0.1 dB, 2 V p-p bandwidth3000 V/μs slew rateFixed gain (AD8146/AD8147: G = 2, AD8148: G = 4) Differential or single-ended input to differential output Can be used as differential-to-differential receiver Drives one or two 100 Ω UTP cablesAdjustable output common-mode voltage (AD8146) Internal common-mode feedback networkOutput balance error −50 dB @ 50 MHzOn-chip, sync-on common-mode encoding (AD8147/AD8148) Output pull-down feature for line isolationLow power: 57 mA @ 5 V for 3 drivers (AD8146)Wide supply voltage range: +5 V to ±5 VAvailable in a small 4 mm × 4 mm LFCSPAPPLICATIONSQXGA or 1080p video transmissionKVM networkingVideo over unshielded twisted pair (UTP)Differential signal multiplexingFUNCTIONAL BLOCK DIAGRAMSVVV OCM CV S+–IN C+IN CV S––OUT CVS+–INB+INBVS–VOCMAVOCMB+OUT VS+OUT–OUT VS+OUT6655-1Figure 1.OPDV S––IN R+IN RV S–SYNC LEVELV S+ (SYNC)–IN B+IN BV S––OUT R–OUT BVS+–ING+INGVS–(SYNC)VSYNCHSYNC+OUTRVS++OUTG–OUTGVS++OUTB6655-2Figure 2.GENERAL DESCRIPTIONThe AD8146/AD8147/AD8148 are high speed triple, differential or single-ended input to differential output drivers. The AD8146 and AD8147 have a fixed gain of 2, and the AD8148 has a fixed gain of 4. They are all specifically designed for the highest resolution component video signals but can be used for any type of analog signals or high speed data transmission over either Category 5 UTP cable or differential printed circuit board (PCB) transmission lines.These drivers can be used with the AD8145 triple differential-to-singled-ended receiver, and the AD8117 crosspoint switch to produce a video distribution system capable of supporting UXGA or 1080p signals.Manufactured on the Analog Devices, Inc. second generation XFCB bipolar process, the drivers have large signal bandwidths of 700 MHz and fast slew rates. They have an internal common-mode feedback feature that provides output amplitude and phase matching that is balanced to −60 dB at 50 MHz, suppressing even-order harmonics and minimizing radiated electromagnetic interference (EMI).The common-mode voltage of each AD8146 output can be set to any level, allowing transmission of signals over the common-mode voltages. The AD8147 and AD8148 encode the vertical and horizontal sync signals on the common-mode voltages of the outputs. All outputs can be independently set to low voltage states to be used with series diodes for line isolation, allowing easy differential multiplexing over the same twisted pair cable. The AD8146/AD8147/AD8148 are available in a 24-lead LFCSP and operate over a temperature range of −40°C to +85°C.AD8146/AD8147/AD8148Rev. 0 | Page 2 of 24TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagrams.............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Absolute Maximum Ratings............................................................7 Thermal Resistance......................................................................7 ESD Caution..................................................................................7 Pin Configuration and Function Descriptions.............................8 Typical Performance Characteristics...........................................10 Theory of Operation......................................................................14 Definition of Terms....................................................................14 Analyzing an Application Circuit.............................................14 Closed-Loop Gain......................................................................14 Calculating the Input Impedance.............................................15 Input Common-Mode Voltage Range in Single-SupplyApplications................................................................................15 Output Common-Mode Control.............................................15 Sync-On Common-Mode.........................................................15 Applications.....................................................................................16 Driving RGB Video Signals Over Category-5 UTP Cable....16 Video Sync-On Common-Mode..............................................16 Driving Two UTP Cables With One Driver...........................18 Using the AD8146 as a Receiver...............................................18 Output Pull-Down (OPD)........................................................19 Layout and Power Supply Decoupling Considerations.........19 Driving a Capacitive Load.........................................................19 Adding Pre-Emphasis to the AD8148.....................................20 Exposed Paddle (EP)..................................................................21 Outline Dimensions.......................................................................22 Ordering Guide.. (22)REVISION HISTORY5/07—Revision 0: Initial VersionAD8146/AD8147/AD8148Rev. 0 | Page 3 of 24SPECIFICATIONSV S = ±5V , V OCM = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R L , dm = 200 Ω, unless otherwise noted. T MIN to T MAX = −40°C to +85°C. Table 1.Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT AC Dynamic Performance−3 dB Small Signal Bandwidth V O = 0.2 V p-p,AD8146 and AD8148/AD8147900/780 MHz −3 dB Large Signal Bandwidth V O = 2 V p-p,AD8146 and AD8148/AD8147700/600 MHz Bandwidth for 0.1 dB Flatness V O = 2 V p-p,AD8146 and AD8147/AD8148200/235 MHz Slew Rate V O = 2 V p-p, 25% to 75% 3000 V/μs Isolation Between Amplifiers f = 10 MHz, between amplifiers,AD8146 and AD8147/AD8148−86/−80 dB DIFFERENTIAL INPUT DC Input Common-Mode Voltage Range −5 to +5 V Input Resistance Differential 1.0 kΩ Single-ended input 1.13 kΩ Input Capacitance Differential 2 pF DC CMRR ΔV OUT, dm /ΔV IN, cm , ΔV IN, cm = ±1 V,AD8146/AD8147/AD8148−53/−49/−55 dB DIFFERENTIAL OUTPUT Differential Signal Gain ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V,AD8146 and AD81471.952.00 V/V ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V, AD8148 −3.42 +3.5 V/V Output Voltage Swing Each single-ended output,AD8146/AD8147/AD8148−3/−2.25/−3.42 +3.4/+3.4/+3.5 V Output Offset Voltage −19 +19 mV Output Offset Drift T MIN to T MAX ±8 μV/°COutput Balance Error ΔV OUT, cm /ΔV IN, dm , ΔV OUT, dm = 2 V p-p,f = 50 MHz,AD8146 and AD8147/AD8148−52/−49 dB DC, AD8146 and AD8148/AD8147 −41/−44 dB Output Voltage Noise (RTO) f = 1 MHz, AD8146 and AD8147/AD8148 25/42 nV/√Hz Output Short-Circuit Current Short to GND, source/sink +87/−67 mAV OCM DYNAMIC PERFORMANCE(AD8146 ONLY) −3 dB Bandwidth ΔV OCM = 100 mV p-p 340 MHz Slew Rate V OCM = −1 V to +1 V, 25% to 75% 800 V/μs DC Gain ΔV OCM = ±1 V 0.986 1.000 V/VV OCM INPUT CHARACTERISTICS(AD8146 ONLY)Input Voltage Range ±3 V Input Resistance 12.5 kΩ Input Offset Voltage −20 +20 mV DC CMRR ΔV OUT, dm /ΔV OCM , ΔV OCM = ±1 V −48 dBSYNC DYNAMIC PERFORMANCE(AD8147/AD8148 ONLY) Slew Rate V OUT, cm = −1 V to +1 V; 25% to 75% 1000 V/μsAD8146/AD8147/AD8148Rev. 0 | Page 4 of 24Parameter Conditions Min Typ Max UnitH SYNC AND V SYNC INPUTS(AD8147/AD8148 ONLY) Input Low Voltage 1.5 to 1.7 V Input High Voltage 1.5 to 1.7 VSYNC LEVEL INPUT(AD8147/AD8148 ONLY) Setting to 0.5 V Pulse Levels 0.5 V Gain to Red Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL (AD8147/AD8148) 0.93/0.965 1.08/1.04 V/V Gain to Green Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL (AD8147/AD8148) 1.91/1.935 2.11/2.05 V/V Gain to Blue Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL (AD8147/AD8148) −1.08/−1.035 −0.93/−0.965 V/V POWER SUPPLY Operating Range +4.5 ±5.5 V Quiescent Current, Positive Supply AD8146 57 mA AD8147/AD8148 61.5/62.5 mA Disabled, AD8146/AD8147 and AD8148 6/21.5 mA Quiescent Current, Negative Supply AD8146 −57 mA AD8147/AD8148 −60.5/−62 mA Disabled −37 mA PSRR ΔV OUT, dm /ΔV S ; ΔV S = ±1 V(AD8146/AD8147/AD8148)−66/−52/−55 dB OUTPUT PULL-DOWN OPD Input Low Voltage 1.1 V OPD Input High Voltage 2.1 V OPD Input Bias Current 520 μA OPD Assert Time 1 μs OPD Deassert Time 10 nsOutput Voltage When OPD Asserted Each output, OPD input @ V S + −4.2 −3.8 VAD8146/AD8147/AD8148Rev. 0 | Page 5 of 24V S = +5 V or ±2.5 V; V OCM = midsupply (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R L, dm = 200 Ω, unless otherwise noted. T MIN to T MAX = −40°C to +85°C. Table 2.Parameter Conditions Min Typ Max Unit DIFFERENTIAL INPUT AC Dynamic Performance −3 dB Small Signal Bandwidth V O = 0.2 V p-p,AD8146/AD8147 and AD8148870/680 MHz −3 dB Large Signal Bandwidth V O = 2 V p-p,AD8147/AD8146 and AD8148590/620 MHz Bandwidth for 0.1 dB Flatness V O = 2 V p-p,AD8146 and AD8147/AD8148165/200 MHz DIFFERENTIAL INPUT DC Input Common-Mode Voltage Range 0 to 5 V Input Resistance Differential 1.0 kΩ Single-ended input 1.13 kΩ Input Capacitance Differential 2 pF DC CMRR ΔV OUT, dm /ΔV IN, cm ; ΔV IN, cm = ±1 V,AD8146/AD8147/AD8148−53/−49/−55 dB DIFFERENTIAL OUTPUT Differential Signal Gain ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V,AD8146 and AD81471.952.013 V/V ΔV OUT, dm /ΔV IN, dm ; ΔV IN, dm = ±1 V, AD81483.874.00 V/V Output Voltage Swing Each single-ended outputAD8146 and AD8147/AD8148−1.17/−1.23 +1.24/+1.26 V Output Offset Voltage −17 +17 mV Output Offset Drift T MIN to T MAX ±8 μV/°COutput Balance Error ΔV OUT, cm /ΔV IN, dm , ΔV OUT, dm = 2 V p-p,f = 50 MHz,AD8146 and AD8147/AD8148−53/−49 dB DC, AD8146 and AD8148/AD8147 −41/−44 dB Output Voltage Noise (RTO) f = 1 MHz, AD8146, AD8147/AD8148 25/42 nV/√Hz Output Short-Circuit Current Short to GND, source/sink +63/−48 mAV OCM DYNAMIC PERFORMANCE(AD8146 ONLY) −3 dB Bandwidth ΔV OCM = 100 mV p-p 310 MHz Slew Rate V OCM = −1 V to +1 V, 25% to 75% 800 V/μs DC Gain ΔV OCM = ±1 V, T MIN to T MAX 0.99 1.00 V/VV OCM INPUT CHARACTERISTICS(AD8146 ONLY) Input Voltage Range ±1.2 V Input Resistance 12.5 kΩ Input Offset Voltage −20 +20 mV DC CMRR ΔV O, dm /ΔV OCM ; ΔV OCM = ±1 V −42 dBSYNC DYNAMIC PERFORMANCE(AD8147/AD8148 ONLY) Slew Rate V OUT, cm = −1 V to +1 V; 25% to 75% 800 V/μsH SYNC AND V SYNC INPUTS(AD8147/AD8148 ONLY) Input Low Voltage 1.3 to 1.5 V Input High Voltage 1.3 to 1.5 VAD8146/AD8147/AD8148Rev. 0 | Page 6 of 24Parameter Conditions Min Typ Max UnitSYNC LEVEL INPUT(AD8147/AD8148 ONLY) Setting to 0.5 V Pulse Levels 0.5 V Gain to Red Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL , AD8147/AD8148 0.88/0.925 1.07/1.00 V/V Gain to Green Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL , AD8147/AD8148 1.83/1.85 2.05/2.00 V/V Gain to Blue Common-Mode Output ΔV O, cm /ΔV SYNC LEVEL , AD8147/AD8148 −1.07/−1 −0.88/−0.925 V/V POWER SUPPLY Operating Range +4.5 ±5.5 V Quiescent Current Positive Supply AD8146 50 mA AD8147/AD8148 55.5/52 mA Disabled, AD8146/AD8147 and AD8148 4/12 mA Quiescent Current Negative Supply AD8146 −50 mA AD8147/AD8148 −55/−51 mA Disabled, AD8146/AD8147/AD8148 −14/−18.2/−15 mA PSRR ΔV OUT, dm /ΔV S ; ΔV S = ±1 V,AD8146/AD8147/AD8148−70/−54/−60 dB OUTPUT PULL-DOWN OPD Input Low Voltage 1.0 V OPD Input High Voltage 2.0 V OPD Input Bias Current 160 μA OPD Assert Time 600 ns OPD Deassert Time 10 ns Output Voltage When OPD Asserted Each output, OPD input @ V S + −1.71 −1.6 VAD8146/AD8147/AD8148Rev. 0 | Page 7 of 24ABSOLUTE MAXIMUM RATINGSTable 3.Parameter Rating Supply Voltage 11 V All V OCM ±V S Power Dissipation See Figure 3Input Common-Mode Voltage ±V S Storage Temperature Range −65°C to +125°C Operating Temperature Range−40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C Junction Temperature150°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.THERMAL RESISTANCEθJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in a circuit board in still air. Table 4. Thermal Resistance with the Underside Pad Connected to the PlanePackage Type/PCB Type θJA Unit 24-Lead LFCSP/4-Layer57°C/WMaximum Power DissipationThe maximum safe power dissipation in the AD8146/AD8147/AD8148 package is limited by the associated rise in junction temperature (T J ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of theAD8146/AD8147/AD8148. Exceeding a junction temperature of 175°C for an extended time can result in changes in the silicon devices, potentially causing failure.The power dissipated in the package (P D ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V S ) times the quiescent current (I S ). The load current consists of differentialand common-mode currents flowing to the loads, as well as currents flowing through the internal differential and common-mode feedback loops. The internal resistor tap used in the common-mode feedback loop places a 4 kΩ differential load on the output. Differential feedback, network resistor values are given in the Theory of Operation section and Applications section. RMS output voltages should be considered when dealing with ac signals. Airflow reduces θJA . In addition, more metal directly in contact with the package leads from metal traces, through holes,ground, and power planes reduces the θJA . The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a ground plane to achieve the specified θJA .Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 24-lead LFCSP (57°C/W) package on a JEDEC standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a ground plane. θJA values are approximations.3.50–40–20020406080AMBIENT TEMPERATURE (°C)M A X I M U M P O W E R D I S S I P A T I O N (W )3.02.52.01.51.00.506655-021Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer BoardESD CAUTIONAD8146/AD8147/AD8148Rev. 0 | Page 8 of 24PIN CONFIGURATION AND FUNCTION DESCRIPTIONS1OPD 2V S–3–IN A 4+IN A 5V S–6–OUT A 15+IN C 16–IN C 17V S+18V OCM C 14V S–13–OUT C7+O U T A 8V S +9+O U T B 11V S +12+O U T C 10–O U T B 1V S –2+I N B 3–I N B 4V S +0V O C M A 9V O C M B 06655-004Figure 4. AD8146 Pin ConfigurationTable 5. AD8146 Pin Function DescriptionsPin No. Mnemonic Description 1 OPD Output Pull-Down. 2, 5, 14, 21 V S−Negative Power Supply Voltage. 3 −IN A Inverting Input, Amplifier A. 4 +IN A Noninverting Input, Amplifier A. 6 −OUT A Negative Output, Amplifier A. 7 +OUT A Positive Output, Amplifier A. 8, 11, 17, 24 V S+Positive Power Supply Voltage. 9 +OUT B Positive Output, Amplifier B. 10 −OUT B Negative Output, Amplifier B. 12 +OUT C Positive Output, Amplifier C. 13 −OUT C Negative Output, Amplifier C. 15 +IN C Noninverting Input, Amplifier C. 16 −IN C Inverting Input, Amplifier C. 18 V OCM C The voltage applied to this pin controls output common-mode voltage, Amplifier C. 19 V OCM B The voltage applied to this pin controls output common-mode voltage, Amplifier B. 20 V OCM A The voltage applied to this pin controls output common-mode voltage, Amplifier A. 22 +IN B Noninverting Input, Amplifier B. 23 −IN B Inverting Input, Amplifier B.AD8146/AD8147/AD8148Rev. 0 | Page 9 of 241OPD 2V S–3–IN R 4+IN R 5V S–6–OUT R+IN B –IN B V S+ (SYNC)SYNC LEVEL V S––OUT B7+O U T R 8V S +9+O U T G 11V S +12+O U T B 10–O U T G 1V S – (S Y N C )2+I N G 3–I N G 4V S +0V S Y N C 9H S Y N C06655-005Figure 5. AD8147/AD8148 Pin ConfigurationTable 6. AD8147/AD8148 Pin Function DescriptionsPin No. Mnemonic Description 1 OPD Output Pull-Down. 2, 5, 14 V S−Negative Power Supply Voltage. 3 −IN R Inverting Input, Red Amplifier. 4 +IN R Noninverting Input, Red Amplifier. 6 −OUT R Negative Output, Red Amplifier. 7 +OUT R Positive Output, Red Amplifier. 8, 11, 24 V S+Positive Power Supply Voltage. 9 +OUT G Positive Output, Green Amplifier. 10 −OUT G Negative Output, Green Amplifier. 12 +OUT B Positive Output, Blue Amplifier. 13 −OUT B Negative Output, Blue Amplifier. 15 +IN B Noninverting Input, Blue Amplifier. 16 −IN B Inverting Input, Blue Amplifier. 17 V S+ (SYNC) Positive Power Supply Voltage for Sync. 18 SYNC LEVEL The voltage applied to this pin controls the amplitude of the sync pulses that are applied tothe common-mode voltages.19 H SYNC Horizontal Sync Pulse Input. 20 V SYNC Vertical Sync Pulse Input. 21 V S− (SYNC) Negative Power Supply Voltage for Sync. 22 +IN G Noninverting Input, Green Amplifier. 23 −IN G Inverting Input, Green Amplifier. Exposed Paddle GND Signal Ground Reference.AD8146/AD8147/AD8148Rev. 0 | Page 10 of 24TYPICAL PERFORMANCE CHARACTERISTICSV S = ±5V; V OCM = 0 V (AD8146); SYNC LEVEL = 0 V (AD8147/AD8148); T = 25°C; R L , dm = 200 Ω; C L, dm = 0 pF, unless otherwise noted. T MIN to T MAX = −40°C to +85°C.9–1101000FREQUENCY (MHz)G A I N (d B )10087654321006655-010Figure 6. AD8146/AD8147 Large Signal Frequency Response for Various Supplies101000FREQUENCY (MHz)G A I N (d B )10006655-011Figure 7. AD8146/AD8147 Small Signal Frequency Response for Various Supplies6.55.511000FREQUENCY (MHz)G A I N (d B )101006.46.36.26.16.05.95.85.75.606655-012Figure 8. AD8146/AD8147 Large Signal 0.1 dB Flatness for Various Supplies155101000FREQUENCY (MHz)G A I N (d B )1001413121110987606655-013Figure 9. AD8148 Large Signal Frequency Response for Various Supplies155101000FREQUENCY (MHz)G A I N (d B )1001413121110987606655-014Figure 10. AD8148 Small Signal Frequency Response for Various Supplies12.511.511000FREQUENCY (MHz)G A I N (d B )1010012.412.312.212.112.011.911.811.711.606655-015Figure 11. AD8148 Large Signal 0.1 dB Flatness for Various SuppliesAD8146/AD8147/AD8148TIME (ns)V O L T A G E (V )–1.5020–0.5–1.02468101214161806655-016TIME (ns)V O L T A G E (m V )Figure 12. AD8146/AD8147 Large Signal Transient Response for Various Supplies150–15002010050–50–1002468101214161806655-017Figure 13. AD8146/AD8147 Small Signal Transient Response for Various Supplies–20–701106655-0241.5–1.5020TIME (ns)V O L T A G E (V )000FREQUENCY (MHz)O U T P U T B A L A N C E E R R O R (d B )10100–25–30–35–40–45–50–55–60–65Figure 14. Output Balance vs. Frequency1.00.5–0.5–1.02468101214161806655-019150–150020TIME (ns)V O L T A G E (m V )Figure 15. AD8148 Large Signal Transient Response for Various Supplies10050–50–10006655-02024681012141618Figure 16. AD8148 Small Signal Transient Response for Various Supplies–20–8011000FREQUENCY (MHz)C O M M O N -M ODE R E J E C T I O N (d B)10100–30–40–50–60–70Figure 17. CMRR vs. FrequencyAD8146/AD8147/AD8148–20–1000.11000FREQUENCY (MHz)P O W E R S U P P L Y R E J E C T I O N (d B )110100–30–40–50–60–70–80–9006655-028Figure 18. Positive Power Supply Rejection vs. Frequency1000100.01100000FREQUENCY (kHz)N O I S E (n H z )0.1110100100010000100Figure 19. Output-Referred Voltage Noise vs. Frequency1000TIME (ns)V O L T A G E (V )100200300400500600700800900Figure 20. AD8146/AD8147 Output Overdrive Recovery–20–1100.11000FREQUENCY (MHz)P O W E R S U PP L Y R E J E C T I O N (d B )110100–30–40–50–60–70–80–90–100Figure 21. Negative Power Supply Rejection vs. Frequency–20–1200.11000FREQUENCY (MHz)I S O L A T I O N (d B )110100–30–40–50–60–70–80–90–100–110Figure 22. Amplifier-to-Amplifier Isolation vs. Frequency1000TIME (ns)V O L T A G E (V )100200300400500600700800900Figure 23. AD8148 Output Overdrive RecoveryAD8146/AD8147/AD81485945–60120TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )575553514947–40–2002040608010006655-0546248–60120TEMPERATURE (°C)S U P P L Y C U R R E N T (m A )605856545250–40–20020406080100Figure 24. AD8146 Supply Current vs. TemperatureFigure 26. AD8147/AD8148 Supply Current vs. Temperature–35–6511000FREQUENCY (MHz)V O C M C M R R (d B )10100–40–45–50–55–601.5–1.504TIME (ns)V O L T A G E (V )1.00.5–0.5–1.05101520253035Figure 27. AD8146 Large Signal V OCM Transient Response for Various SuppliesFigure 25. V OCM Common-Mode Rejection RatioAD8146/AD8147/AD8148 THEORY OF OPERATIONEach differential driver differs from a conventional op amp in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The drivers make it easy to perform single-ended-to-differential conversion, common-mode level shifting, and amplification of differential signals.Previous differential drivers, both discrete and integrated designs, were based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks.DC common-mode level shifting has also been difficult with previous differential drivers. Level shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes, the third amplifier was also used to attempt to correct an inherently unbalanced circuit. Excellent performance over a wide frequency range has proven difficult with this approach.Each of the drivers uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set by the internal resistors, controls only the differential output voltage. The internal common-mode feedback loop controls only the common-mode output voltage. This architecture makes it easy to transmit signals over the common-mode voltage channels by simply applying the signal voltages to the V OCM inputs. The output common-mode voltage is forced, by internal common-mode feedback, to equal the voltage applied to the V OCM input, without affecting the differential output voltage.The driver architecture results in outputs that are highly balanced over a wide frequency range without requiring external components or adjustments. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude that are exactly 180° apart in phase. DEFINITION OF TERMSDifferential VoltageDifferential voltage refers to the difference between two node voltages that are balanced with respect to each other. For example, in Figure 28 the output differential voltage (or equivalently output differential mode voltage) is defined as V OUT, dm = (V OP − V ON) Common-Mode VoltageCommon-mode voltage refers to the average of two node voltages with respect to a common reference. The output common-mode voltage is defined asV OUT, cm = (V OP + V ON)/2Output BalanceOutput balance is a measure of how well the differential output signals are matched in amplitude and how close they are to exactly 180° apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential output voltage nodes and comparing the magnitude of the signal at the divider’s midpoint with the magnitude of the differential signal. By this definition, output balance error is the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differential mode voltage in response to a differential input signal.dmOUTcmOUTVVErrorBalanceOutput,,ΔΔ=ANALYZING AN APPLICATION CIRCUITThe drivers use high open-loop gain and negative feedback to force their differential and common-mode output voltages to minimize the differential and common-mode input error voltages. The differential input error voltage is defined as the voltage between the differential inputs labeled V AP and V AN in Figure 28. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to V OCM can also be assumed to be zero. Starting from these two assumptions,any application circuit can be analyzed.CLOSED-LOOP GAINThe differential mode gain of the circuit in Figure 28 can be described byGFdmIN,dmOUT,RRVV=where:R F is 1.0 kΩ and R G is 500 Ω nominally for the AD8146 and AD8147.R F is 2.0 kΩ and R G is 500 Ω nominally for the AD8148.VV+V IN, dm–VONOPOUT, dm6655-6 Figure 28. Internal Architecture and Signal Name Definitions。

REV.0aInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/ Fax: 781/326-8703© Analog Devices, Inc., 2002AD9860/AD9862*Mixed-Signal Front-End (MxFE ™) Processorfor Broadband Communications*Protected by U.S.Patent No. 5,969,657; other patents pending.MxFE is a trademark of Analog Devices, Inc.GENERAL DESCRIPTIONThe AD9860 and AD9862 (AD9860/AD9862) are versatile integrated mixed-signal front-ends (MxFE) that are optimized for broadband communication markets. The AD9860/AD9862are cost effective, mixed signal solutions for wireless or wireline standards based or proprietary broadband modem systems where dynamic performance, power dissipation, cost, and size are all critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;the AD9862 has 12-bit ADCs and 14-bit DACs.The AD9860/AD9862 receive path (Rx) consists of two channels that each include a high performance, 10-/12-bit, 64 MSPS analog-to-digital converter (ADC), input buffer, Programmable Gain Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The Rx can be used to receive real, diversity, or I/Q data at baseband or low IF. The input buffers provide a constant input impedance for both channels to ease impedance matching with external com-ponents (e.g., SAW filter). The RxPGA provides a 20dB gainrange for both channels. The output data bus can be multi-plexed to accommodate a variety of interface types.The AD9860/AD9862 transmit path (Tx) consists of two chan-nels that contain high performance, 12-/14-bit, 128 MSPS digital-to-analog converters (DAC), programmable gain amplifiers (TxPGA), interpolation filters, a Hilbert filter, and digital mixers for complex or real signal frequency modulation. The Tx latch and demultiplexer circuitry can process real or I/Q data. Interpo-lation rates of 2ϫ and 4ϫ are available to ease requirements on an external reconstruction filter. For single channel systems, the digital Hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. The two 12-/14-bit, high performance DACs produce an output signal that can be scaled over a 20 dB range by the TxPGA.A programmable delay-locked loop (DLL) clock multiplier and integrated timing circuits enable the use of a single external reference clock or an external crystal to generate clocking for all internal blocks and also provides two external clock outputs.Additional features include a programmable sigma-delta output,four auxiliary ADC inputs and three auxiliary DAC outputs.Device programmability is facilitated by a serial port interface (SPI) combined with a register bank. The AD9860/AD9862 is available in a space saving 128-lead LQFP.FUNCTIONAL BLOCK DIAGRAMTx DA T A [0:13]SIGDEL T A T A FEATURESMixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path Includes:Two 10-/12-Bit, 64 MSPS Sampling A/D Converters with Internal or External Independent References,Input Buffers, Programmable Gain Amplifiers,Low-Pass Decimation Filters, and a Digital Hilbert Filter Transmit Signal Path Includes:Two 12-/14-Bit, 128 MSPS D/A Converters with Programmable Full-Scale Output Current, Channel Independent Fine Gain and Offset Control, Digital Hilbert and Interpolation Filters, and Digitally Tunable Real or Complex Up-ConvertersDelay-Locked Loop Clock Multiplier and Integrated Timing Generation Circuitry Allow for Single Crystal or Clock OperationProgrammable Output Clocks, Serial Programmable Interface, Programmable Sigma-Delta, Three Auxiliary DAC Outputs and Two Auxiliary ADCs with Dual Multiplexed InputsAPPLICATIONSBroadband Wireless SystemsFixed Wireless, WLAN, MMDS, LMDS Broadband Wireline SystemsCable Modems, VDSL, PowerPlug Digital CommunicationsSet-Top Boxes, Data ModemsAD9860/AD9862–SPECIFICATIONS(V A = 3.3 V ؎ 5%, V D = 3.3 V ؎ 10%, f DAC = 128 MHz, f ADC = 64 MHzNormal Timing Mode, 2؋ DLL Setting, R SET = 4 k⍀, 50 ⍀ DAC Load,–2–REV. 0AD9860/AD9862–3–Test AD9860/AD9862Rx PARAMETERS (continued)Temp Level Min Typ Max Unit DC ACCURACYDifferential Nonlinearity25ºC III±0.3/±0.4LSB Integral Nonlinearity25ºC III±1.2/±5LSB Offset Error25ºC III±0.1%FSR Gain Error25ºC III±0.2%FSR Aperture Delay25ºC III 2.0ns Aperture Uncertainty (Jitter)25ºC III 1.2ps rms Input Referred Noise25ºC III 250µV Reference Voltage ErrorREFT-REFB Error (1 V)25ºC I±1±4mV AD9860 DYNAMIC PERFORMANCE (A IN = –0.5 dBFS, f = 5 MHz)Signal-to-Noise Ratio25∞C I59.0 60.66dBc Signal-to-Noise and Distortion Ratio25∞C I56.0 58.0dBc Total Harmonic Distortion25∞C I–76.5–70.5dBc Spurious Free Dynamic Range25∞C I70.3 81.0dBc AD9862 DYNAMIC PERFORMANCE (A IN = –0.5 dBFS, f = 5 MHz)Signal-to-Noise Ratio25∞C I62.6 64.2dBc Signal-to-Noise and Distortion Ratio25∞C I62.5 64.14dBc Total Harmonic Distortion25∞C I–79.22–73.2dBc Spurious Free Dynamic Range25∞C I77.09 85.13dBc CHANNEL-TO-CHANNEL ISOLATIONTx-to-Rx (A OUT = 0 dBFS, f OUT = 7 MHz)25ºC III >90dB Rx Channel Crosstalk (f1 = 6 MHz, f2 = 9 MHz)25ºC III >80dB PARAMETERSCMOS LOGIC INPUTSLogic “1” Voltage, V IH25ºC II DRVDD – 0.7V Logic “0” Voltage, V IL25ºC II0.4V Logic “1” Current25ºC II12µA Logic “0” Current25ºC II12µA Input Capacitance25ºC III 3pF CMOS LOGIC OUTPUTS (1 mA Load)Logic “1” Voltage, V OH25ºC II DRVDD – 0.6V Logic “0” Voltage, V OL25ºC II0.4V POWER SUPPLYAnalog Supply CurrentsTx (Both Channels, 20 mA FS Output)25ºC I 7076mA Tx Powered Down25ºC I 2.5 5.0mA Rx (Both Channels, Input Buffer Enabled)25ºC I 275307mA Rx (Both Channels, Input Buffer Disabled)25ºC III 245mA Rx (32 MSPS, Low Power Mode, Buffer Disabled)25ºC III 155mA Rx (16 MSPS, Low Power Mode, Buffer Disabled)25ºC III 80mA Rx Path Powered Down25ºC I 5.0 6.0mA DLL25ºC III 12mA Digital Supply CurrentAD9860 Both Rx and Tx Path (All Channels Enabled)2ϫ Interpolation, f DAC = f ADC = 64 MSPS25ºC I 92112mA AD9862 Both Rx and Tx Path (All Channels Enabled)2ϫ Interpolation, f DAC = f ADC = 64 MSPS25ºC I 104124mA Tx Path (f DAC = 128 MSPS)Processing Blocks Disabled25ºC III 45mA 4ϫ Interpolation25ºC III 90mA 4ϫ Interpolation, Coarse Modulation25ºC III 110mA 4ϫ Interpolation, Fine Modulation25ºC III 110mA 4ϫ Interpolation, Coarse and Fine Modulation25ºC III 130mAREV. 0REV. 0–4–AD9860/AD9862Test AD9860/AD9862(20 pF Load)Temp Level Min Typ MaxUnit Minimum Reset Pulsewidth Low (t RL )NA NA 5Clock Cycles Digital Output Rise/Fall Time 25ºC III 2.84ns DLL Output Clock25ºC III 32128MHz DLL Output Duty Cycle25ºC III 50%Tx –/Rx –Interface (See Figures 11 and 12)TxSYNC/TxIQ Setup Time (t Tx1, t Tx3)25ºC III 3ns TxSYNC/TxIQ Hold Time (t Tx2, t Tx4)25ºC III 3ns RxSYNC/RxIQ/IF to Valid Time(t Rx1, t Rx3)25ºC III 5.2ns RxSYNC/RxIQ/IF Hold Time (t Rx2, t Rx4)25ºC III 0.2ns Serial Control Bus (See Figures 1 and 2)Maximum SCLK Frequency (f SCLK )Full III 16MHz Minimum Clock Pulsewidth High (t HI )Full III 30ns Minimum Clock Pulsewidth Low (t LOW )Full III 30ns Maximum Clock Rise/Fall TimeFull III 1ms Minimum Data/SEN Setup Time (t S )Full III 25ns Minimum SEN/Data Hold Time (t H )Full III 0ns Minimum Data/SCLK Setup Time (t DS )Full III 25ns Minimum Data Hold Time (t DH )Full III 0ns Output Data Valid/SCLK Time (t DV )Full III 30ns AUXILARY ADC Conversion Rate 25ºC III 1.25MHz Input Range 25ºC III 3V Resolution 25ºC III 10Bits AUXILARY DAC Settling Time 25ºC III 8m s Output Range 25ºC III 3V Resolution25ºC III 8Bits ADC TIMINGLatency (All Digital Processing Blocks Disabled)25ºC III 7Cycles DAC TimingLatency (All Digital Processing Blocks Disabled)25ºC III 3Cycles Latency (2ϫ Interpolation Enabled)25ºC III 30Cycles Latency (4ϫ Interpolation Enabled)25ºC III 72Cycles Additional Latency (Hilbert Filter Enabled)25ºC III 36Cycles Additional Latency (Coarse Modulation Enabled)25ºC III 5Cycles Additional Latency (Fine Modulation Enabled)25ºC III 8Cycles Output Settling Time (TST) (to 0.1%)25ºCIII35nsSpecifications subject to change without notice.TIMING CHARACTERISTICSTest AD9860/AD9862PARAMETERS (continued)TempLevelMinTyp MaxUnitPOWER SUPPLY (continued)Rx Path (f ADC = 64 MSPS)Processing Blocks Disabled 25ºCIII 9mA Decimation Filter Enabled 25ºC III 15mA Hilbert Filter Enabled25ºC III 16mA Hilbert and Decimation Filter Enabled25ºC III 18.5mANOTES 1% f DATA refers to the input data rate of the digital block.2Interpolation filter stop band is defined by image suppression of 50 dB or greater.Specifications subject to change without notice.REV. 0AD9860/AD9862–5–CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.ABSOLUTE MAXIMUM RATINGS 1Power Supply (V AS , V DS ) . . . . . . . . . . . . . . . . . . . . . . . . .3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . .5 mA Digital Inputs . . . . . . . . . . . . . . . .–0.3 V to DRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . .–0.3 V to AVDD (IQ) + 0.3 V Operating Temperature 2 . . . . . . . . . . . . . . . . .–40؇C to +70؇C Maximum Junction Temperature . . . . . . . . . . . . . . . . .150؇C Storage Temperature . . . . . . . . . . . . . . . . . . .–65؇C to +150؇C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . .300؇CNOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.2The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40؇C to +85؇C) when operated in Half Duplex Mode.EXPLANATION OF TEST LEVELSI.Devices are 100% production tested at 25ºC and guaranteed by design and characterization testing for the extended industrial temperature range (–40ºC to +70ºC).II.Parameter is guaranteed by design and/or characterization testing.III.Parameter is a typical value only.NA.Test level definition is not applicable.THERMAL CHARACTERISTICS Thermal Resistance128-Lead LQFP ␪JA = 29ºC/WORDERING GUIDEModel Temperature Range Package DescriptionPackage Option AD9860BST –40∞C to +70∞C *128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128B AD9862BST –40∞C to +70∞C *128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128BAD9860PCB Evaluation Board with AD9860AD9862PCBEvaluation Board with AD9862*The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40؇C to +85؇C) when operated in Half Duplex Mode.REV. 0–6–AD9860/AD9862PIN CONFIGURATIONAGND AVDD DVDD DGND DGND DVDD Tx11/13 (MSB)Tx10/12T x 9/1T x 8/1T x 7/T x 6/T x 5/T x 4/T x 3/T x 2/T x 1/T x 0/N C /T x N C /T x AUX_ADC_A1AGND AVDD AVDD SIGDEL T AUX_DAC_A AUX_DAC_B AUX_DAC_CAGNDDLL_Lock AGND NC AVDD OSC1OSC2AGND CLKSEL AVDD AGND AVDD REFIO FSADJ AVDD AGND IOUT–A IOUT+A AGND AGND IOUT+B IOUT–B T x S Y N D G N D V D S C L S D S D I S E D G N D V D D G N D V D M O D E /T x B L A N R E S E T C L K O U T A G N DA V D DA V D DA G N DV I N +BV I N –BA G N DA G N DV R E FA G N DA G N DV I N –AV I N +AA G N DA V D DA V D DA G N DR E F B _AR E F T _AA G N DA V D DA V D DA U X _A D C _B 2A U X _A D C _B 1A U X _A D C _R E FA U X _A D C _A 2NC = NO CONNECTAD9860/AD9862–7–Pin No.Mnemonic FunctionClock Pins10DLL_Lock DLL Lock Indicator Pin11, 16AGND DLL Analog Ground Pins12NC No Connect13AVDD DLL Analog Supply Pin14OSC1Single Ended Input Clock(or Crystal Oscillator Input)15OSC2Crystal Oscillator Input17CLKSEL Controls CLKOUT1 Rate64CLKOUT2Clock Output Generated from InputClock (DLL Multiplier Settingand CLKOUT2 Divide Factor)65CLKOUT1Clock Output Generated fromInput Clock (1ϫ if CLKSEL = 1or /2 if CLKSEL = 0)Various Pins1AUX_ADC_A1Auxiliary ADC A Input 13, 4, 13AVDD Analog Power Pins2, 9AGND Analog Ground Pins5SIGDELT Digital Output fromProgrammable Sigma-Delta6AUX_DAC_A Auxiliary DAC A Output7AUX_DAC_B Auxiliary DAC B Output8AUX_DAC_C Auxiliary DAC C Output33, 36, 53,DVDD Digital Power Supply Pin59, 61, 66,9334, 35, 52,DGND Digital Ground Pin58, 60, 67,9454SCLK Serial Bus Clock Input55SDO Serial Bus Data Bit56SDIO Serial Bus Data Bit57SEN Serial Bus Enable63RESETB Reset (SPI Registers and Logic) 95AUX_SPI_do Optional Auxiliary ADC Serial BusData Out Bit96AUX_SPI_clk Optional Auxiliary ADC Serial BusData Out Latch Clock97AUX_SPI_csb Optional Auxiliary ADC Serial BusChip Select Bit128AUX_ADC_A2Auxiliary ADC A Input 2126AUX_ADC_B1Auxiliary ADC B Input 1125AUX_ADC_B2Auxiliary ADC B Input 2127AUX_ADC_REF Auxiliary ADC ReferencePin No.Mnemonic FunctionReceive Pins68/70–79D0A to10-/12-Bit ADC Output ofD9A/D11A Receive Channel A80/82–91D0B to10-/12-Bit ADC Output ofD9B/D11B Receive Channel B92RxSYNC Synchronization Clock forChannel A and Channel B Rx Paths98, 99,AVDD Analog Supply Pins104, 105,117, 118,123, 124,100, 103,AGND Analog Ground Pins106, 109,110, 112,113, 116,119, 122,101REFT_B Top Reference Decoupling forChannel B ADC102REFB_B Bottom Reference Decouplingfor Channel B ADC107VIN+B Receive Channel B Differential (+) Input108VIN–B Receive Channel B Differential (؊) Input111VREF Internal ADC Voltage Reference114VIN–A Receive Channel A Differential (؊) Input115VIN+A Receive Channel A Differential (+) Input120REFB_A Bottom Reference Decoupling forChannel A ADC121REFT_A Top Reference Decoupling forChannel A ADCTransmit Pins18, 20AVDD Analog Supply Pins23, 3219, 24,AGND Analog Ground Pins27, 28, 3121REFIO Reference Output, 1.2 V Nominal22FSADJ Full-Scale Current Adjust25IOUT–A Transmit Channel A DACDifferential (؊) Output26IOUT+A Transmit Channel A DACDifferential (+) Output29IOUT+B Transmit Channel B DACDifferential (+) Output30IOUT–B Transmit Channel B DACDifferential (؊) Output37–48/50Tx11/Tx1312-/14-Bit Transmit DAC Datato Tx0(Interleaved Data when Required)51TxSYNC Synchronization Input for Transmitter62MODE/Configures Default Timing Mode,TxBLANK*Controls Tx Digital Power Down*The logic level of the Mode/TxBLANK pin at power up defines the default timingmode; a logic low configures Normal Operation, logic high configures AlternateOperation Mode.PIN FUNCTION DESCRIPTIONSREV. 0AD9860/AD9862DEFINITIONS OF SPECIFICATIONSDifferential Nonlinearity Error (DNL, No Missing Codes)An ideal converter exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicate that all 1024 codes respectively, must be present over all operating ranges.Integral Nonlinearity Error (INL)Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.Phase NoiseSingle-sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in Single Tone Trans-mit Mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. Output Compliance RangeThe range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.Spurious-Free Dynamic Range (SFDR)The difference, in dB, between the rms amplitude of the DAC’s output signal (or ADC’s input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth unless otherwise noted).Pipeline Delay (Latency)The number of clock cycles between conversion initiation and the associated output data being made available.Offset ErrorFirst transition should occur for an analog value 1/2 LSB above –full scale. Offset error is defined as the deviation of the actual transition from that point.Gain ErrorThe first code transition should occur at an analog value 1/2LSB above –full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.Aperture DelayThe aperture delay is a measure of the Sample-and-Hold Ampli-fier (SHA) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion.Aperture Uncertainty (Jitter)Aperture jitter is the variation in aperture delay for successivesamples and is manifested as noise on the input to the ADC.Input Referred NoiseThe rms output noise is measured using histogram techniques.The ADC output code’s standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noisefigure that can be referred directly to the input of the AD9860/ AD9862.Signal-to-Noise and Distortion (S/N+D, SINAD) RatioS/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.Effective Number of Bits (ENOB)For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula:N=()SINAD dB–..176602it is possible to get a measure of performance expressed as N,the effective number of bits. Thus, effective number of bits fora device for sine wave inputs at a given input frequency can becalculated directly from its measured SINAD.Signal-to-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR isexpressed in decibels.Total Harmonic Distortion (THD)THD is the ratio of the rms sum of the first six harmoniccomponents to the rms value of the measured input signal and is expressed as a percentage or in decibels.Power Supply RejectionPower supply rejection specifies the converter’s maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages.Channel-to-Channel Isolation (Crosstalk)In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channel-to-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel.REV. 0–8––9–FREQUENCY – MHzTPC 1.AD9862 Tx Output 6 MHzSingle Tone; CLKIN = 32 MHz;DLL 4ϫ SettingFREQUENCY – MHzMAGNITUDE–dBm–20–4020406080100110120–60–80140TPC 4.TxDAC Generating anOFDM Signal; CLKIN = 64 MHz,DLL 2ϫ Settingf OUT – MHz5203510152530THD–dBcTPC 7.TxDAC HarmonicDistortion vs. f OUTFREQUENCY – MHzTPC 2.AD9862 Tx Output 6 MHzSingle Tone; CLKIN = 64 MHz;DLL 2ϫ SettingFREQUENCY – MHzMAGNITUDE–dBm20406080100110120140TPC 5.TxDAC Generating anOFDM Signal; CLKIN = 64 MHz,DLL 2ϫ SettingFREQUENCY– MHzSNR–dB74737271706968TPC 8.Signal-to-Noise Ratio (SNR)vs. f OUTFREQUENCY – MHzTPC 3.AD9862 Tx Output 6 MHzSingle Tone; CLKIN = 128 MHz;DLL 1ϫ SettingFREQUENCY – MHzMAGNITUDE–dBm–20–40–60–80–100–120TPC 6.Zoomed in Plot of FourNotched Carriers of OFDM Signal;CLKIN = 64 MHz, DLL 2ϫ SettingCARRIER FREQUENCY – MHz5IMD–dBc20–60–65–70–75–80–85–9010152530–50–55–95TPC 9.Two Tone Intermodulationvs. f OUT1 (f OUT2 = f OUT1 + 1 MHz)REV. 0AD9860/AD9862FFT OUTPUT – MHz5FFTMAGNITUDE–dBFS20–20–40–60–8010152530–100–120TPC 10.ADC Dual Tone FFT withBuffer Tones at 4.5 MHz and 5.5 MHzf IN – MHz52TPC 13.AD9862 Rx SINADvs. fINat 64 MSPSf IN – MHzTPC 16.AD9860 Rx SINADvs. f IN at 64 MSPSFFT OUTPUT – MHz5FFTMAGNITUDE–dBFS20–20–40–60–8010152530–100–120TPC 11.ADC Dual Tone FFT withoutBuffer Tones at 4.5 MHz and 5.5 MHzf IN – MHzSINAD–dBcTPC 14.AD9862 Rx SINADvs. f IN at 32 MSPSf IN – MHzSINAD–dBc62TPC 17.AD9860 Rx SINADvs. f IN at 32 MSPSFFT OUTPUT – MHz5FFTMAGNITUDE–dBFS20–20–40–60–8010152530–100–120TPC 12.ADC Dual Tone FFT(undersampling) without BufferTones at 69.5 MHz and 70.5 MHzf IN – MHz020050SINAD–dBc150250100300TPC 15.AD9862 Rx SINADvs. f IN at 16 MSPSf IN – MHzSINAD–dBc62TPC 18.AD9860 Rx SINADvs. f IN at 16 MSPSREV. 0–10–AD9860/AD9862INPUT FREQUENCY – MHzT H D – d B c–60–65–70–75–80–85–90–50–55–95–100TPC 19.Rx THD vs. f IN ,F ADC = 64 MSPSINPUT FREQUENCY – MHzS F D R – d B c–60–65–70–75–80–85–90–50–55–95–100TPC 22.Rx SFDR @ 64 MSPSINPUT FREQUENCY – MHzR E L A T I V E A T T E N U A T I O N – d B10–1–2–3–4–5–6TPC 25.Rx Input Attenuationf IN – MHzT H D – d B c–75–80–85–90–70–65–60–55–50TPC 20.Rx THD vs. f IN ,F ADC = 32 MSPS f IN – MHzS F D R – d B c–75–80–85–90–70–65–60–55–50–95TPC 23.Rx SFDR @ 32 MSPS f IN – MHzI N P U T I M P E D A N C E – ⍀60250240230220210200190204080100270260180280TPC 26.Rx Input Buffer Impedance vs. f INf IN – MHzT H D – d B c–75–80–85–90–70–65–60–55–50TPC 21.Rx THD vs. f IN ,F ADC = 16 MSPSf IN – MHz020050S F D R – d B c–75–80–85–90–70150250100–65–60–55–50300–95TPC 24.Rx SFDR @ 16 MSPSf ADC – MSPS04010R x A N A L O G P O W E R – m W30020010004003050205006007008007060TPC 27.Rx Analog Power ConsumptionAD9860/AD9862REGISTER MAP (0x00–0x3F)1NOTES1When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers are set low, except for the bits in the shaded boxes, which are set high.2DecimalAD9860/AD9862REGISTER BIT DEFINITIONSREGISTER 0: GENERALBIT 7: SDIO BiDir (Bidirectional)Default setting is low, which indicates SPI serial port uses dedi-cated input and output lines (i.e., 4-wire interface), SDIO and SDO Pins, respectively. Setting this bit high configures the serial port to use the SDIO Pin as a bidirectional data pin.BIT 6: LSB FirstDefault setting is low, which indicates MSB first SPI Port Access Mode. Setting this bit high configures the SPI port access to LSB first mode.BIT 5: Soft ResetWriting a high to this register resets all the registers to their default values and forces the DLL to relock to the input clock. The Soft Reset Bit is a one shot register and is cleared immediately after the register write is completed.REGISTER 1: Rx PWRDWNBIT 7: V REF, diff (Power-Down)Setting this bit high will power down the ADC’s differential references (i.e., REFT and REFB).BIT 6: V REF (Power-Down)Setting this register bit high will power down the ADC reference circuit (i.e., V REF).BIT 5: Rx Digital (Power-Down)Setting this bit high will power down the digital section of the receive path of the chip. Typically, any unused digital blocks are automatically powered down.BIT 4/3: Rx Channel B/Rx Channel A (Power-Down)Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The entire Rx channel is powered down, including the differential references, input buffer, and the internal digital block. The bandgap reference remains active for quick recovery.BIT 2/1: Buffer B/Buffer A (Power-Down)Setting either of these bits high will power down the input buffer circuits for the respective channel. The input buffer should be powered down when bypassed. By default, these bits are low and the input buffers are enabled.BIT 0: All Rx (Power-Down)Setting this bit high powers down all circuits related to the receive path.REGISTER 2/3: Rx A/Rx BBIT 7: Bypass Buffer A/Bypass Buffer BSetting either of these bits high will bypass the respective input buf-fer circuit. When the buffer is bypassed, the input signal is routed directly to the switched capacitor SHA input of the RxPGA. When operating with buffer bypassed, it should be powered down.BIT 0–4: RxPGA A/RxPGA BThese 5-bit straight binary registers (Bit 0 is the LSB, Bit 4 is the MSB) provide control for the programmable gain amplifiers in the dual receive paths. A 0 dB to 20 dB gain range is accom-plished through a switched capacitor network with fast settling of a few clock cycles. The step size is approximately 1 dB. The register default setting is minimum gain or hex00. The maximum setting for these registers is hex14.REGISTER 4: Rx MISCBIT 2: HS (High Speed) Duty CycleSetting this bit high optimizes duty cycle of the internal ADC sampling clock. It is recommended that this bit be set high in high speed applications when clock duty cycle affects noise and distortion performance the most. This bit should be set high in conjunction with Clk Dut Enable register bit.BIT 1: Shared RefSetting this bit high forces the dual receive ADCs into a mode to share their differential references to provide superior gain matching. When this option is enabled, the REFT of Channel A and Channel B should be connected together off-chip and the REFB of both channels should be connected.BIT 0: Clk DutySetting this bit high enables an on-chip duty cycle stabilizer (DCS) circuit to generate the internal clock for the Rx block. This option is useful for adjusting for high speed input clocks with skewed duty cycle. The DCS Mode can be used with ADC sampling frequencies over 40 MHz.REGISTER 5: Rx I/F (INTERFACE)BIT 4: Three-stateSetting this bit high will force both Rx data output buses, including the RxSYNC Pin, into a three-state mode.BIT 3: Rx RetimeThe Rx path can use either of the clock outputs, CLKOUT1 or CLKOUT2, to latch the Rx output data. Since CLKOUT1 and CLKOUT2 have slight phase offsets, this provides some timing flexibility with the interface. By default, this bit is low and the Rx output latches use CLKOUT1. Setting this bit will force the Rx output latches to use CLKOUT2.BIT 2: Twos ComplementDefault data format for the Rx data is straight binary. Setting this bit high will generate two’s complement data.BIT 1: Inv RxSyncWhen the receive data is multiplexed onto one data port (i.e., Mux Mode Enabled), the RxSYNC Pin can be used to decode which channel generated the current output data at the active port. Default condition is that RxSYNC is high when Channel A is at the output and is low when Channel B is at the output. Setting this bit high reverses this synchronization.BIT 0: Mux OutSetting this bit high enables the Rx Mux Mode. Default setting is low, which is Dual Port Mode, (i.e., non Rx Mux Mode). When in Rx Mux Mode, both Rx channels share the same output data bus, pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862). The other Rx output bus (pins D0B to D9B or D0B to D11B) outputs a low logic.REGISTER 6: Rx DigitalBIT 3: 2 ChannelSetting this bit low disables the Rx B output data port (pins D0B to D9B or D11B), forcing the output pins to zero. By default, the bit is high and both data paths are active.BIT 2: Keep –veThis bit selects whether the receive Hilbert filter will filter positive or negative frequencies, assuming the filter is enabled. By default this bit is low, which passes positive frequencies. Setting this bit high will configure the filter to pass negative frequencies.BIT 1: HilbertThis bit enables or disables the Hilbert filter in the receive path. By default, this bit is low, which disables the receive Hilbert filter. Setting this bit high enables the receive Hilbert filter.BIT 0: DecimateThis register enables or disables the decimation filters. By default, the register setting is low and the decimation filter is disabled.。