eMMC for China_CSV September_2011

eMMC的发展历史及未来市场前景导读: eMMC是针对智能型手机（Smartphone）所设计的内嵌式存储器规格，是外接式记忆卡MMC的延伸，eMMC之后也扩散至平板计算机（Tablet PC）应用领域。

•关键字•eMMC发展智能手机存储器记忆卡eMMC是针对智能型手机（Smartphone）所设计的内嵌式存储器规格，是外接式记忆卡MMC的延伸，eMMC之后也扩散至平板计算机（Tablet PC）应用领域。

eMMC设计概念是把NAND Flash芯片和控制芯片封装成BGA 封装芯片，可节省电路板的面积，客户设计新产品时，也不需考虑内建NAND Flash芯片的三星电子（Samsung Electron ic s）、美光（Micron）、东芝（Toshiba），或是35纳米、24纳米或19纳米制程，便利了手机客户设计的程序和新产品问世时间点。

快闪记忆卡协会SD协会也同样推出eSD规格，但目前eMMC在智能型手机内嵌式存储器领域的领导位置无可动摇，几乎是所有手机大厂储存接口的标准，除了苹果（Apple）必采用自家的设计规范外。

eMMC规格的标准这几年也快速演进，从eMMC4.3、eMMC4.4、eMMC4.5陆续问世，而预计接棒eMMC规格的会是三星电子（Samsung Electronics）主导的UFS（Universal Flash Storage），会把Mobile RAM等芯片功能都涵盖。

在智能型手机领域中，eMMC规格是主流，但在平板计算机或是轻薄型笔记本电脑（NB）上，仍要和SATA接口的固态硬盘（SSD）做竞争，毕竟SATA SSD有读写速度上的优势，不论是随机效能（Random Pe rf ormance）或是连续效能（Sequential Performance）等，内嵌式iSSD也都明显优于eMMC，较适合PC类的产品应用，例如新帝的iSSD产品就是SATA接口SSD的代表。

讨论到eMMC的发展历程，必须要从介绍Flash的历史开始Flash分为两种规格：NOR Flash和NAND Flash，两者均为非易失性闪存模块。

Embedded Multi-Media Card(e•MMC™ 5.1)EMMC04G-M627-X03UProduct Features•Packaged managed NAND flash memory with e•MMC™ 5.1 interface•Backward compatible with all prior e•MMC™ specification revisions•153-ball JEDEC FBGA RoHS Compliant package•Operating voltage range:o VCCQ = 1.8 V/3.3 Vo VCC = 3.3 V•Operating Temperature - 25C to +85C•Storage Temperature -40C to +85C•Compliant with e•MMC™ 5.1 JEDEC Standard Number JESD84-B51•Transitions to low power state after 50ms from idle state entry.e•MMC™ Specific Feature Support•High-speed e•MMC™ protocol•Variable clock frequencies of 0-200MHz•Ten-wire bus interface (clock, 1 bit command, 8 bit data bus) with an optional hardware reset •Supports three different data bus widths: 1 bit(default), 4 bits, 8 bits•Bus Modes:o Single data transfer rate: up to 52MB/s (using 8 parallel data lines at 52MHz)o Dual data rate mode (DDR-104) : up to 104MB/s @ 52MHzo High speed, single data rate mode (HS-200) : up to 200MB/s @ 200MHzo High speed, dual data rate mode (HS-400) : up to 400MB/s @ 200MHz •Supports alternate boot operation mode to provide a simple boot sequence method o Supports SLEEP/AWAKE (CMD5)o Host initiated explicit sleep mode for power saving•Enhanced write protection with permanent and partial protection options•Multiple user data partition with enhanced attribute for increased reliability•Error free memory accesso Cyclic Redundancy Code (CRC) for reliable command and data communicationo Internal error correction code (ECC) for improved data storage integrityo Internal enhanced data management algorithmo Data protection for sudden power failure during program operations•Securityo Secure bad block erase commandso Enhanced write protection with permanent and partial protection options•Power off notification for sleep•Field firmware update (FFU)•Production state awareness•Device health report•Command queuing•Enhanced strobe•Cache flushing report•Cache barrier•Background operation control & High Priority Interrupt (HPI)•RPMB throughput improvement•Secure write protection•Pre EOL information•Optimal sizeProduct DescriptionKingston’s e•MMC™ products conform to the JEDEC e•MMC™ 5.1standard. These devices are an ideal universal storage solution for many commercial and industrial applications. In a single integrated packaged device, e•MMC™ combines multi-level cell (MLC) NAND flash memory with an onboard e•MMC™ controller, providing an industry standard interface to the host system. The integrated e•MMC™ controller directly manages NAND flash media which relieves the host processor of these tasks, including flash media error control, wear-leveling, NAND flash management and performance optimization. Future revision to the JEDEC e•MMC™ standard will always maintain backward compatibility. The industry standard interface to the host processor ensures compatibility across future NAND flash generations as well, easing product sustainment throughout the product life cycle. ConfigurationsKingston’s e•MMC™ products support a variety of configurations that allow the e•MMC™ device to be tailored to your specific application needs. The most popular configurations described below are each offered under standard part numbers.Standard MLC – By default the e•MMC™ device is configured with the NAND flash in a standard MLC mode. This configuration provides reasonable performance and reliability for many applications. Pseudo Single Level Cell (pSLC) – The MLC NAND flash in the Kingston e•MMC™ device can be configured to further improve device endurance, data retention, reliability and performance over the standard MLC configuration. This is done by converting the NAND MLC cells to a pseudo single level cell (SLC) configuration. In this configuration, along with the performance and reliability gains, the device capacity is reduced by 50%. This one-time configuration is achieved by setting the e•MMC™ enhanced attribute for the hardware partition.Enhanced Reliable Write – When not configured as pSLC, MLC NAND flash stores 2 bits of information in 4 energy levels per NAND flash cell. Since these paired bits are organized in different NAND pages, there is a possibility that a power failure while programming a page could corrupt a paired page that was already programmed. For the Kingston e•MMC™, this condition is rare and the possibility is further reduced due to the device’s built-in data protection with on-board error correction code (ECC) bits. With reliable write set, the onboard e•MMC™ controller will back-up any paired pages to ensure that there is no data loss during sudden power failure. This configuration can result in a write performance penalty of up to 20% over the standard MLC configuration.Kingston e•MMC™ can be ordered preconfigured with the option of reliable write or pSLC at no additional cost. Standard MLC devices can also be one-time configured in-field by following the procedures outlined in the JEDEC e•MMC™ specification. The JEDEC e•MMC™ specification allows for many additional configurations such as up to 4 additional general purpose (GPn) hardware partitions each with the option to support pSLC and reliable write. Additionally, Kingston provides a content loading service that can streamline your product assembly while reducing production costs. For more information, contact your Kingston representative.Kingston e•MMC™ devices are fully compliant with the JEDEC Standard Specification No. JESD84-B51. This datasheet provides technical specifications for Kingston’s family of e•MMC™ devices. Refer to the JEDEC e•MMC™ standard for specific information related to e•MMC™ device function and operation. See: /sites/default/files/docs/JESD84-B51.pdfPart NumberingFigure 1 – Part Number FormatEMMC 64G - xxxx - nnnnA B C DPart Number FieldsA: Product Family : EMMCB: Device Capacity : Available capacities of 4GBC: Hardware Revision and ConfigurationD: Device Firmware Revision and ConfigurationTable 1 - Device SummaryDevice PerformanceTable 2 below provides sequential read and write speeds for all capacities. Performance numbers can vary under different operating conditions. Values are given at HS400 bus mode. Contact your Kingston Representative for performance numbers using other bus modes.Power ConsumptionDevice current consumption for various device configurations is defined in the power class fields of the EXT_CSD register. Power consumption values are summarized in Table 3 below.Device and Partition CapacityThe device NAND flash capacity is divided across two boot partitions (2048 KB each), a Replay Protected Memory Block (RPMB) partition (512 KB), and the main user storage area. Four additional general purpose storage partitions can be created from the user partition. These partitions can be factory preconfigured or configured in-field by following the procedure outlined in section 6.2 of the JEDEC e•MMC™ specification JESD84-B51. A small portion of the NAND storage capacity is used for the storage of the onboard controller firmware and mapping tables. Additionally, several NAND blocks are held in reserve to boost performance and extend the life of the e•MMC™ device. Table 4 identifies the specific capacity of each partition. This information is reported in the device EXT_CSD register. The contents of this register are also listed in the Appendix.e•MMC™ Bus ModesKingston e•MMC™ devices support all bus modes defined in the JEDEC e•MMC™ 5.1 specification. These modes are summarized in Table 6 below.Signal DescriptionTable 7 - e•MMC™ Signals Name Type DescriptionCLK I Clock: Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock frequency.DAT[7:0] I/O/PP Data: These are bidirectional data channels. The DAT signals operate in push-pull mode. These bidirectional signals are driven by either the e•MMC™ device or the host controller. By default, after power up or reset, only DAT0 is used for data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-DAT7, by the e•MMC™ host controller. The e•MMC™ device includes internal pull-ups for data lines DAT1-DAT7. Immediately after entering the 4-bit mode, the device disconnects the internal pull ups of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode, the device disconnects the internal pull-ups of lines DAT1–DAT7.CMD I/O/PP/OD Command: This signal is a bidirectional command channel used for device initialization and transfer of commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-pull for fast command transfer. Commands are sent from the e•MMC™ host controller to the e•MMC™ device and responses are sent from the device to the host.DS O This signal is generated by the device and used for output in HS400 mode. The frequency of this signal follows the frequency of CLK. For data output each cycle of this signal directs two bits transfer(2x) on the data - one bit for positive edge and the other bit for negative edge. For CRC status response output and CMD response output (enabled only HS400 enhanced strobe mode), the CRC status and CMD Response are latched on the positive edge only, and don't care on the negative edge.RST_n I Hardware Reset: By default, hardware reset is disabled and must be enabled in the EXT_CSD register if used. Otherwise, it can be left un-connected.RFU - Reserved for future use: These pins are not internally connected. Leave floatingNC - Not Connected: These pins are not internally connected. Signals can be routed through these balls to ease printed circuit board design. See Kingston’s Design Guidelines for further details.VSF - Vendor Specific Function: These pins are not internally connectedVddi - Internal Voltage Node: Note that this is not a power supply input. This pin provides access to the output of an internal voltage regulator to allow for the connection of an external Creg capacitor. See Kingston’s Design Guidelines for further details.Vcc S Supply voltage for core Vccq S Supply voltage for I/ODesign GuidelinesDesign guidelines are outlined in a separate document. Contact your Kingston Representative for more information.Package DimensionsFigure 2 – Package DimensionsFigure 3 – Ball Pattern DimensionsBall Assignment (153 ball)Table 8 – Ball Assignment, Top View (HS400)1 2 3 4 5 6 7 8 9 10 11 12 13 14A NC NC DAT0 DAT1 DAT2 Vss RFU NC NC NC NC NC NC NC AB NC DAT3 DAT4 DAT5 DAT6 DAT7 NC NC NC NC NC NC NC NC BC NC Vddi NC Vssq NC Vccq NC NC NC NC NC NC NC NC CD NC NC NC NC NC NC NC DE NC NC NC RFU Vcc Vss VSF VSF VSF NC NC NC EF NC NC NC Vcc VSF NC NC NC FG NC NC RFU Vss VSF NC NC NC GH NC NC NC DS Vss NC NC NC H J NC NC NC Vss Vcc NC NC NC J K NC NC NC RST_n RFU RFU Vss Vcc VSF NC NC NC K L NC NC NC NC NC NC L M NC NC NC Vccq CMD CLK NC NC NC NC NC NC NC NC M N NC Vssq NC Vccq Vssq NC NC NC NC NC NC NC NC NC N P NC NC Vccq Vssq Vccq Vssq RFU NC NC RFU NC NC NC NC P1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note: VSF, RFU and NC balls are not electrically connected. RFU balls may be defined with functionality by the Joint Electron Device Engineering Council (JEDEC) in future revisions of the e•MMC™ standard. Please refer to Kingston’s design guidelines for more info.Device MarkingFigure 4 - EMMC Package Marking240xxxx-xxx.xxxxYYWW PPPPPPPPxxxxxxx-xxxx2xxxxxxTAIWANKingston Logo240xxxx-xxx.xxxx：Internal control numberYYWW：Date code (YY– Last 2 digits ofyear, WW- Work week)PPPPPPPP： Internal control numberxxxxxxx-xxxx Sales P/N2xxxxxx : Internal control numberCountry：TAIWANCard Identification Register (CID)The Card Identification (CID) register is a 128-bit register that contains device identification information used during the e•MMC™ protocol device identification phase. Refer to JEDEC Standard Specification No.JESD84-B51 for details.Field Byte ValueMID [127:120] 0x70reserved [119:114] 0x00CBX [113:112] 0x01OID [111:104] 0x00PNM [103:56 ] M62704PRV [ 55:48 ] 0x03PSN [ 47:16 ] RandomMDT [ 15:8 ] month, yearCRC [ 7:1 ] Follows JEDEC Standardreserved [ 0:0 ] 0x01Card Specific Data Register [CSD]The Card-Specific Data (CSD) register provides information on how to access the contents stored in e•MMC™. The CSD registers are used to define the error correction type, maximum data access time, data transfer speed, data format…etc. For details, refer to section 7.3 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueCSD_Structure [127:126] 0x03 (V2.0)SPEC_VER [125:122] 0x04 (V4.0~4.2)reserved [121:120] 0x00TAAC [119:112] 0x4F (40ms)NSAC [111:104] 0x01TRAN_SPEED [103:96 ] 0x32 (26Mbit/s)CCC [ 95:84 ] 0x0F5READ_BL_LEN [ 83:80 ] 0x09 (512 Bytes)READ_BL_PARTIAL [ 79:79 ] 0x00WRITE_BLK_MISALIGN [ 78:78 ] 0x00READ_BLK_MISALIGN [ 77:77 ] 0x00DSR_IMP [ 76:76 ] 0x00reserved [ 75:74 ] 0x00C_SIZE [ 73:62 ] 0xFFFVDD_R_CURR_MIN [ 61:59 ] 0x07 (100mA)VDD_R_CURR_MAX [ 58:56 ] 0x07 (200mA)VDD_W_CURR_MIN [ 55:53 ] 0x07 (100mA)VDD_W_CURR_MAX [ 52:50 ] 0x07 (200mA)C_SIZE_MULT [ 49:47 ] 0x07 (512 Bytes)ERASE_GRP_SIZE [ 46:42 ] 0x1FERASE_GRP_MULT [ 41:37 ] 0x1FWP_GRP_SIZE [ 36:32 ] 0x07WP_GRP_ENABLE [ 31:31 ] 0x01DEFAULT_ECC [ 30:29 ] 0x00R2W_FACTOR [ 28:26 ] 0x02WRITE_BL_LEN [ 25:22 ] 0x09 (512 Bytes)WRITE_BL_PARTIAL [ 21:21 ] 0x00reserved [ 20:17 ] 0x00CONTENT_PROT_APP [ 16:16 ] 0x00FILE_FORMAT_GRP [ 15:15 ] 0x00COPY [ 14:14 ] 0x00PERM_WRITE_PROTECT [ 13:13 ] 0x00TMP_WRITE_PROTECT [ 12:12 ] 0x00FILE_FORMAT [ 11:10 ] 0x00Field Byte ValueECC [ 9:8 ] 0x00CRC [ 7:1 ] Follow JEDEC Standard reserved [ 0:0 ] 0x01Extended Card Specific Data Register [EXT_CSD]The Extended CSD register defines the Device properties and selected modes. It is 512 bytes long. The most significant 320 bytes are the Properties segment, which defines the Device capabilities and cannot be modified by the host. The lower 192 bytes are the Modes segment, which defines the configuration the Device is working in. These modes can be changed by the host by means of the SWITCH command. For details, refer to section 7.4 of the JEDEC Standard Specification No.JESD84-B51.Field Byte ValueReserved [511:506] 0EXT_SECURITY_ERR [505:505] 0x00S_CMD_SET [504:504] 0x01HPI_FEATURES [503:503] 0x01BKOPS_SUPPORT [502:502] 0x01MAX_PACKED_READS [501:501] 0x3CMAX_PACKED_WRITES [500:500] 0x3CDATA_TAG_SUPPORT [499:499] 0x01TAG_UNIT_SIZE [498:498] 0x03TAG_RES_SIZE [497:497] 0x00CONTEXT_CAPABILITIES [496:496] 0x05LARGE_UNIT_SIZE_M1 [495:495] 0x03EXT_SUPPORT [494:494] 0x03SUPPORTED_MODES [493:493] 0x01FFU_FEATURES [492:492] 0x00OPERATION_CODE_TIMEOUT [491:491] 0x00FFU_ARG [490:487] 65535BARRIER_SUPPORT [486:486] 0x01Reserved [485:309] 0CMDQ_SUPPORT [308:308] 0x01CMDQ_DEPTH [307:307] 0x1FReserved [306:306] 0x00 NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED [305:302] 0 VENDOR_PROPRIETARY_HEALTH_REPORT [301:270] 0DEVICE_LIFE_TIME_EST_TYP_B [269:269] 0x01DEVICE_LIFE_TIME_EST_TYP_A [268:268] 0x01PRE_EOL_INFO [267:267] 0x01OPTIMAL_READ_SIZE [266:266] 0x01OPTIMAL_WRITE_SIZE [265:265] 0x04OPTIMAL_TRIM_UNIT_SIZE [264:264] 0x01DEVICE_VERSION [263:262] 0FIRMWARE_VERSION [261:254] 0x03PWR_CL_DDR_200_360 [253:253] 0x00Field Byte Value CACHE_SIZE [252:249] 512 GENERIC_CMD6_TIME [248:248] 0x19POWER_OFF_LONG_TIME [247:247] 0xFF BKOPS_STATUS [246:246] 0x00 CORRECTLY_PRG_SECTORS_NUM [245:242] 0 INI_TIMEOUT_AP [241:241] 0x64 CACHE_FLUSH_POLICY [240:240] 0x01PWR_CL_DDR_52_360 [239:239] 0x00PWR_CL_DDR_52_195 [238:238] 0x00PWR_CL_200_195 [237:237] 0x00PWR_CL_200_130 [236:236] 0x00 MIN_PERF_DDR_W_8_52 [235:235] 0x00MIN_PERF_DDR_R_8_52 [234:234] 0x00Reserved [233:233] 0x00TRIM_MULT [232:232] 0x11 SEC_FEATURE_SUPPORT [231:231] 0x55 SEC_ERASE_MULT [230:230] 0x01SEC_TRIM_MULT [229:229] 0x01 BOOT_INFO [228:228] 0x07Reserved [227:227] 0x00 BOOT_SIZE_MULT [226:226] 0x10ACC_SIZE [225:225] 0x06 HC_ERASE_GRP_SIZE [224:224] 0x01ERASE_TIMEOUT_MULT [223:223] 0x11 REL_WR_SEC_C [222:222] 0x01HC_WP_GRP_SIZE [221:221] 0x08S_C_VCC [220:220] 0x08S_C_VCCQ [219:219] 0x08 PRODUCTION_STATE_AWARENESS_TIMEOUT [218:218] 0x14 S_A_TIMEOUT [217:217] 0x12 SLEEP_NOTIFICATION_TIME [216:216] 0x0F SEC_COUNT [215:212] 7405568Reserved [211:211] 0x01 MIN_PERF_W_8_52 [210:210] 0x08MIN_PERF_R_8_52 [209:209] 0x08 MIN_PERF_W_8_26_4_52 [208:208] 0x08MIN_PERF_R_8_26_4_52 [207:207] 0x08 MIN_PERF_W_4_26 [206:206] 0x08MIN_PERF_R_4_26 [205:205] 0x08Reserved [204:204] 0x00 PWR_CL_26_360 [203:203] 0x00Field Byte Value PWR_CL_52_360 [202:202] 0x00 PWR_CL_26_195 [201:201] 0x00 PWR_CL_52_195 [200:200] 0x00 PARTITION_SWITCH_TIME [199:199] 0x03 OUT_OF_INTERRUPT_TIME [198:198] 0x04 DRIVER_STRENGTH [197:197] 0x1F DEVICE_TYPE [196:196] 0x57 Reserved [195:195] 0x00 CSD_STRUCTURE [194:194] 0x02 Reserved [193:193] 0x00 EXT_CSD_REV [192:192] 0x08 CMD_SET [191:191] 0x00Reserved [190:190] 0x00 CMD_SET_REV [189:189] 0x00 Reserved [188:188] 0x00 POWER_CLASS [187:187] 0x00 Reserved [186:186] 0x00HS_TIMING [185:185] 0x01 STROBE_SUPPORT [184:184] 0x01 BUS_WIDTH [183:183] 0x02Reserved [182:182] 0x00 ERASED_MEM_CONT [181:181] 0x00 Reserved [180:180] 0x00 PARTITION_CONFIG [179:179] 0x00 BOOT_CONFIG_PROT [178:178] 0x00 BOOT_BUS_CONDITIONS [177:177] 0x00 Reserved [176:176] 0x00 ERASE_GROUP_DEF [175:175] 0x00 BOOT_WP_STATUS [174:174] 0x00 BOOT_WP [173:173] 0x00Reserved [172:172] 0x00USER_WP [171:171] 0x00Reserved [170:170] 0x00FW_CONFIG [169:169] 0x00 RPMB_SIZE_MULT [168:168] 0x04 WR_REL_SET [167:167] 0x00 WR_REL_PARAM [166:166] 0x15 SANITIZE_START [165:165] 0x00BKOPS_START [164:164] 0x00BKOPS_EN [163:163] 0x00 RST_n_FUNCTION [162:162] 0x00Field Byte Value HPI_MGMT [161:161] 0x00 PARTITIONING_SUPPORT [160:160] 0x07MAX_ENH_SIZE_MULT [159:157] 452PARTITIONS_ATTRIBUTE [156:156] 0x00 PARTITION_SETTING_COMPLETED [155:155] 0x00 GP_SIZE_MULT_4 [154:152] 0GP_SIZE_MULT_3 [151:149] 0GP_SIZE_MULT_2 [148:146] 0GP_SIZE_MULT_1 [145:143] 0ENH_SIZE_MULT [142:140] 0ENH_START_ADDR [139:136] 0Reserved [135:135] 0x00 SEC_BAD_BLK_MGMNT [134:134] 0x00 PRODUCTION_STATE_AWARENESS [133:133] 0x00 TCASE_SUPPORT [132:132] 0x00PERIODIC_WAKEUP [131:131] 0x00 PROGRAM _CID_CSD_DDR_SUPPORT [130:130] 0x01 Reserved [129:128] 0 VENDOR_SPECIFIC_FIELD [127:67 ] 68157696 ERROR_CODE [ 66:65 ] 0ERROR_TYPE [ 64:64 ] 0x00 NATIVE_SECTOR_SIZE [ 63:63 ] 0x00USE_NATIVE_SECTOR [ 62:62 ] 0x00DATA_SECTOR_SIZE [ 61:61 ] 0x00INI_TIMEOUT_EMU [ 60:60 ] 0x00CLASS_6_CTRL [ 59:59 ] 0x00DYNCAP_NEEDED [ 58:58 ] 0x00 EXCEPTION_EVENTS_CTRL [ 57:56 ] 0EXCEPTION_EVENTS_STATUS [ 55:54 ] 0 EXT_PARTITIONS_ATTRIBUTE [ 53:52 ] 0 CONTEXT_CONF [ 51:37 ] 0 PACKED_COMMAND_STATUS [ 36:36 ] 0x00PACKED_FAILURE_INDEX [ 35:35 ] 0x00 POWER_OFF_NOTIFICATION [ 34:34 ] 0x00 CACHE_CTRL [ 33:33 ] 0x00FLUSH_CACHE [ 32:32 ] 0x00 Reserved [ 31:31 ] 0x00 MODE_CONFIG [ 30:30 ] 0x00 MODE_OPERATION_CODES [ 29:29 ] 0x00 Reserved [ 28:27 ] 0 FFU_STATUS [ 26:26 ] 0x00C - 4Field Byte Value PRE_LOADING_DATA_SIZE [ 25:22 ] 0 MAX_PRE_LOADING_DATA_SIZE [ 21:18 ] 3670016 PRODUCT_STATE_AWARENESS_ENABLEMENT [ 17:17 ] 0x01 SECURE_REMOVAL_TYPE [ 16:16 ] 0x01 CMDQ_MODE_EN [ 15:15 ] 0x00Reserved [ 14:0 ] 0C - 5。

e·MMC ™ MemoryMTFC2GMVEA-0M WT, MTFC4GLVEA-0M WT, MTFC4GMVEA-1M WT,MTFC8GLVEA-1M WT, MTFC16GJVEC-2M WT, MTFC32GJVED-3M WT,MTFC64GJVDN-3M WT Features•MultiMediaCard (MMC) controller and NAND Flash •153- or 169-ball WFBGA/VFBGA/LFBGA (RoHS 6/6-compliant)•V CC : 2.7–3.6V•V CCQ (dual voltage): 1.65–1.95V; 2.7–3.6V •Temperature ranges–Operating temperature: –25˚C to +85˚C –Storage temperature: –40˚C to +85˚C •Typical current consumption–Standby current: 110µA for 2GB, 120µA for 4GB,8GB, 16GB; 140µA for 32G; 160µA for 64GB –Active current (RMS): 70mA (2GB); 80mA (4GB,8GB, 16GB, 32GB, 64GB)MMC-Specific Features•JEDEC/MMC standard version 4.41-compliant (JEDEC Standard No. 84-A441) – SPI mode not supported (see /sites/default/files/docs/JESD84-A441.pdf )–Advanced 11-signal interface–x1, x4, and x8 I/Os, selectable by host –MMC mode operation–Command classes: class 0 (basic); class 2 (block read); class 4 (block write); class 5 (erase);class 6 (write protection); class 7 (lock card)–MMC plus ™ and MMC mobile ™ protocols –Temporary write protection –52 MHz clock speed (MAX)–Boot operation (high-speed boot)–Sleep mode–Replay-protected memory block (RPMB)–Secure erase and trim –Hardware reset signal–Multiple partitions with enhanced attribute –Permanent and power-on write protection –Double data rate (DDR) function –High-priority interrupt (HPI)Figure 1: Micron e ·MMC DeviceMMC-Specific Features (Continued)–Enhanced reliable write–Configurable reliability settings –Background operation–Fully enhanced configurable–Backward-compatible with previous MMC modes•ECC and block management implementede·MMC PerformanceTable 1: MLC Partition PerformanceNote: 1.Random access of 4KB chunk; sequential read access of 1MB chunk. Additional performance data, such as power consumption or timing for different device modes, will be provided in a separate document uponcustomer request.Ordering InformationTable 2: Ordering InformationPart Numbering InformationMicron®e·MMC memory devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at . To compare features and specifications by device type, visit /products. Contact the factory for devices not found.Figure 2: Marketing Part Number ChartMT FC 2G M V x EA - 0 M WTMicron TechnologyProduct FamilyFC = NAND Flash + controllerNAND Flash Density2G = 2GB4G = 4GB8G = 8GB16G = 16GB32G = 32GB64G = 64GBNAND Flash Component Controller Revision Production StatusBlank = ProductionES = Engineering samplesMS = Mechanical samplesOperating Temperature Range Blank = 0°C to 70°CWT = Standard (–25°C to +85°C)IT = Extended (–40°C to +85)°CSLC Enhanced AreaF = 40%M = 100%Maximum Boot Size0 = 1MB1 = 2MB2 = 4MB3 = 8MB4 = 16MBPackage Codes (Pb-free)DN = 169 LFBGA 14mm x 18mm x 1.4mm DQ = 100 LFBGA 14mm x 18mm x 1.4mm EA = 153 WFBGA 11.5mm x 13mm x 0.8mm EC = 169 WFBGA 14mm x 18mm x 0.8mm ED = 169 VFBGA 14mm x 18mm x 1.0mmReserved for Future UseMark DeviceJ MLC 64Gb, x8, 3.3V (25nm)L MLC 32Gb, x8, 3.3V (25nm)M MLC 16Gb, x8, 3.3V (25nm)Mark (Rev.) Controller IDT EnhancedV ComboNote: 1.Not all combinations are necessarily available. For a list of available devices or for further information on any aspect of these products, please contact your nearest Micron sales office.General DescriptionMicron e·MMC is a communication and mass data storage device that includes a Multi-MediaCard (MMC) interface, a NAND Flash component, and a controller on an ad-vanced 11-signal bus, which is compliant with the MMC system specification. Its lowcost, small size, Flash technology independence, and high data throughput makee·MMC ideal for embedded applications like set-top boxes, digital cameras/camcor-ders, digital TVs, and a variety other consumer products.The nonvolatile e·MMC draws no power to maintain stored data, delivers high perform-ance across a wide range of operating temperatures, and resists shock and vibration dis-ruption.Signal DescriptionsTable 3: Signal DescriptionsNote: 1.V SS and V SSQ are connected internally.153-Ball Signal AssignmentsFigure 3: 153-Ball FBGA (top view, ball down)1 2 3 4 5 6 7 8 9 10 11 12 13 14BCDEFGHJKLMNPNotes: 1.Some test pads on the device are not shown. They are not solder balls and are for Mi-cron internal use only.2.Some previous versions of the JEDEC product or mechanical specification had definedreserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-vious specifications could have been connected to ground on the system board. To ena-ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-chanical specification. Any new PCB footprint implementations should use the new ballassignments and leave the RFU balls floating on the system board.169-Ball Signal AssignmentsFigure 4: 169-Ball FBGA (top view, ball down)1 2 3 4 5 6 7 8 9 10 11 12 13 14BCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHNotes: 1.Empty balls do not denote actual solder balls; they are position indicators only.2.Some test pads on the device are not shown. They are not solder balls and are for Mi-cron internal use only.3.Some previous versions of the JEDEC product or mechanical specification had definedreserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the pre-vious specifications could have been connected to ground on the system board. To ena-ble new feature introduction, some of these balls are assigned as RFU in the v4.4 me-chanical specification. Any new PCB footprint implementations should use the new ball assignments and leave the RFU balls floating on the system board.Package DimensionsFigure 5: 153-Ball WFBGA – 11.5mm x 13.0mm x 0.8mm (Package Code: EA)Note: 1.Dimensions are in millimeters.Figure 6: 169-Ball WFBGA – 14.0mm x 18.00mm x 0.8mm (Package Code: EC)Note: 1.Dimensions are in millimeters.Figure 7: 169-Ball VFBGA – 14.0mm x 18.00mm x 1.0mm (Package Code: ED)Note: 1.Dimensions are in millimeters.Figure 8: 169-Ball LFBGA – 14.0mm x 18.00mm x 1.4mm (Package Code: DN)Note: 1.Dimensions are in millimeters.ArchitectureFigure 9: e·MMC Functional Block DiagramV V CCV CCQDAT[7:0]V SS1V SSQ1Note: 1.V SS and V SSQ are internally connected.MMC Protocol Independent of NAND Flash TechnologyThe MMC specification defines the communication protocol between a host and a de-vice. The protocol is independent of the NAND Flash features included in the device.The device has an intelligent on-board controller that manages the MMC communica-tion protocol.The controller also handles block management functions such as logical block alloca-tion and wear leveling. These management functions require complex algorithms anddepend entirely on NAND Flash technology (generation or memory cell type).The device handles these management functions internally, making them invisible tothe host processor.Defect and Error ManagementMicron e·MMC incorporates advanced technology for defect and error management. Ifa defective block is identified, the device completely replaces the defective block withone of the spare blocks. This process is invisible to the host and does not affect dataspace allocated for the user.The device also includes a built-in error correction code (ECC) algorithm to ensure thatdata integrity is maintained.To make the best use of these advanced technologies and ensure proper data loadingand storage over the life of the device, the host must exercise the following precautions:•Check the status after WRITE, READ, and ERASE operations.•Avoid power-down during WRITE and ERASE operations.CID RegisterThe card identification (CID) register is 128 bits wide. It contains the device identifica-tion information used during the card identification phase as required by e·MMC proto-col. Each device is created with a unique identification number.Table 4: CID Register Field ParametersCSD RegisterThe card-specific data (CSD) register provides information about accessing the devicecontents. The CSD register defines the data format, error correction type, maximum da-ta access time, and data transfer speed, as well as whether the DS register can be used.The programmable part of the register (entries marked with W or E in the following ta-ble) can be changed by the PROGRAM_CSD (CMD27) command.Table 5: CSD Register Field ParametersTable 5: CSD Register Field Parameters (Continued)Notes: 1.R = Read-onlyR/W = One-time programmable and readableR/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_nsignal, and any CMD0 reset, and readableTBD = To be determined2.Reserved bits should be read as 0.ECSD RegisterThe 512-byte extended card-specific data (ECSD) register defines device properties andselected modes. The most significant 320 bytes are the properties segment. This seg-ment defines device capabilities and cannot be modified by the host. The lower 192bytes are the modes segment. The modes segment defines the configuration in whichthe device is working. The host can change the properties of modes segments using theSWITCH command.Table 6: ECSD Register Field ParametersTable 6: ECSD Register Field Parameters (Continued)Table 6: ECSD Register Field Parameters (Continued)Table 6: ECSD Register Field Parameters (Continued)Table 6: ECSD Register Field Parameters (Continued)Table 6: ECSD Register Field Parameters (Continued)Notes: 1.R = Read-onlyR/W = One-time programmable and readableR/W/E = Multiple writable with the value kept after a power cycle, assertion of theRST_n signal, and any CMD0 reset, and readableR/W/C_P = Writable after the value is cleared by a power cycle and assertion of theRST_n signal (the value not cleared by CMD0 reset) and readableR/W/E_P = Multiple writable with the value reset after a power cycle, assertion of theRST_n signal, and any CMD0 reset, and readableW/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_nsignal, and any CMD0 reset, and not readableTBD = To be determined2.Reserved bits should be read as 0.3.Micron has tested power failure under best application knowledge conditions with posi-tive results. Customers may request a dedicated test for their specific application condi-tion.4.Can be set to 1Fh to enable reliability settings. This byte is one-time programmable.DC Electrical Specifications – Device PowerThe device current consumption for various device configurations is defined in the power class fields of the ECSD register.V CC is used for the NAND Flash device and its interface voltage; V CCQ is used for the controller and the e ·MMC interface voltage. A C REG capacitor must be connected to the V DDI terminal to stabilize regulator output on the system.Figure 10: Device Power DiagramCLK CMD DAT[7:0]V CCV DDI C V CCQNote: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect reliability.Table 7: Absolute Maximum RatingsNote:1.Voltage on any pin relative to V SS .Table 8: Operating ConditionsNote: 1.C REG is used to stabilize the internal regulator output to controller core logic voltages.Micron recommends using the following capacitor values:C VCC (capacitor for V CC) = 4.3µF.C VCCQ (capacitor for V CCQ) = 4.3µFC REG = 1.0µF.Revision HistoryRev. A – 06/12•Initial release8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: /productsupport Customer Comment Line: 800-932-4992Micron and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of their respective owners.This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.Although considered final, these specifications are subject to change, as further product development and data characterization some-times occur.2GB, 4GB, 8GB, 16GB, 32GB, 64GB: e·MMCRevision History。

single block writ e在单数据速率模式下，数据通过host输出，通过device时钟上升沿进行采样，在每个data line中有执行过程说明：1.首先通过CMD7(transfer state)选择device进行数据写的操作。

2.Host通过CMD16设置面向对象数据传输的有效数据长度。

CMD16只对单数据速率模式有效。

3.上述整个顺序从一个单块写命令CMD24开始，Ncr代表Host命令与Device回复的最小延迟时钟周期，且2≤Ncr≤64。

Device然后进行回复。

此回复为R1 Response。

R1 Response的具体device status详4.当host端接收到Response后，要经过Nwr个时钟周期才会进行数据的传输，即写入数据。

Nwr代表Device回复与开始写入数据的时钟周期。

Nwr≥25.在单数据速率模式下，在每个数据块传输过程中都有一个CRC来对每个block是否出现传输错误进行检测。

若在任意所动的data line上出现传输错误，Device将会发送一个CRC status，在write data 与发送CRC status中间会有Ncrc个最小延迟时钟周期。

Ncrc是为HS200定义的一个时序参数，只有6.若在任意所动的data line上出现传输错误，Device将会在DAT0上发送一个负极CRC status（101）。

若传输成功，将在DAT0上发送一个正极CRC status（010）。

然后开始进入数据编程过程。

7.当device进入编程时，将会拉低Dat0使device进入busy状态，这个busy状态与编程状态直接相关，当Device完成整个编程时，Device停止拉低DAT0.涉及寄存器说明：CSD：NameCSD bit Field Width Cell Type Remark。