HD66702中⽂资料HD66702/HD66701(Dot Matrix Liquid Crystal Display Controller/Driver)ADE-207-304(Z)'99.9Rev. 0.0 DescriptionThe HD66701/2 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of a 4- or 8-bit microprocessor. Since all the functions required for driving a dot-matrix liquid crystal display are internally provided on one chip, a minimal system can be interfaced with this controller/driver.A single HD66702 can display up to two 20-character lines, and a single HD66701 can display up to two 16-character lines. The low 3-V power supply of the HD66701/2 is suitable for any portable battery-driven product requiring low power dissipation.Features5 × 7 and 5 × 10 dot matrix possible80 × 8-bit display RAM (80 characters max.)7,200-bit character generator ROM160 character fonts (5 × 7 dot)32 character fonts (5 × 10 dot)64 × 8-bit character generator RAM8 character fonts (5 × 7 dot)4 character fonts (5 × 10 dot)16-common × 100-segment (HD66702) or 80-segment (HD66701) liquid crystal display driverProgrammable duty cycles1/8 for one line of 5 × 7 dots with cursor1/11 for one line of 5 × 10 dots with cursor1/16 for two lines of 5 × 7 dots with cursorHD66702/HD66701Maximum display charactersOne line1/8 duty cycle, 20-char. × 1-line (HD66702), 16-char. × 1-line (HD66701)1/11 duty cycle, 20-char. × 1-line (HD66702), 16-char. × 1-line (HD66701) Two lines1/16 duty cycle, 20-char. × 2-line (HD66702), 16-char. × 2-line (HD66701)Wide range of instruction functionsDisplay clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shiftChoice of power supply (V CC): 4.5 to 5.5V (standard), 2.7 to 5.5V (low voltage)Automatic reset circuit that initializes the controller/driver after power on (standard version only) Independent LCD drive voltage driven off of the logic power supply (V CC): 3.0 to 8.3VLow power dissipationLQFP2020-144-pin (HD66702), chip, chip wtith bumpOrdering InformationType No.Package Operating Voltage ROM FontHCD66702RA00L144-pin-chip 2.7 to 5.5V Standard Japanese HCD66702RA00BP144-pin-chip with bump 2.7 to 5.5V Standard Japanese HCD66702RA01L144-pin-chip 2.7 to 5.5V Communication system HCD66702RA02L144-pin-chip 2.7 to 5.5V European fontHD66702RA00F FP-144A 4.5 to 5.5V Standard Japanese HD66702RA00FL FP-144A 2.7 to 5.5V Standard JapaneseHD66702RA01F FP-144A 4.5 to 5.5V Communication font HD66702RA02F FP-144A 4.5 to 5.5V European fontHCD66701A00124-pin-chip 2.7 to 5.5V Standard JapaneseHD66702/HD66701 LCD-II Family ComparisonItem LCD-II(HD44780U)HD66702HD66701HD66710HD66712UPower supply voltage 2.7V to 5.5V 5 V ±10 %(standard)2.7 V to 5.5V(low voltage)2.7V to 5.5V 2.7V to 5.5VLiquid crystal drivevoltage3.0V to 11 V 3.0V to 8.3V 3.0V to 13.0V 2.7V to 11.0VMaximum display digits per chip 8 characters× 2 lines20 characters× 2 lines (HD66702)16 characters× 2 lines (HD66701)16 characters ×2 lines/8 characters ×4 lines24 characters ×2 lines/12 characters ×4 linesSegment display None None40 segments60 segments Display duty cycle1/8, 1/11, and 1/161/8, 1/11, and 1/161/17 and1/331/17 and 1/33CGROM9,920 bits(208 5 × 8 dotcharacters and 325 × 10 dotcharacters)7,200 bits(160 5 × 7 dotcharacters and 325 × 10 dotcharacters)9,600 bits(240 5 × 8 dotcharacters)9,600 bits(240 5 × 8 dotcharacters)CGRAM64 bytes64 bytes64 bytes64 bytes DDRAM80 bytes80 bytes80 bytes80 bytes SEGRAM None None8 bytes16 bytes Segment signals40100 (HD66702)80 (HD66701)4060 Common signals16163334 Liquid crystal drivewaveformA B B BBleeder resistor for LCD power supply External(adjustable)External(adjustable)External(adjustable)External(adjustable)Clock source External resistor orexternal clock External resistor orexternal clockExternal resistoror external clockExternal resistor orexternal clockRfoscillation frequency (frame frequency)270 kHz ±30% (59 to 110 Hz for1/8 and 1/16 dutycycle; 43 to 80 Hzfor 1/11 duty cycle)320 kHz ±30%(70 to 130 Hz for1/8 and 1/16 dutycycle; 51 to 95 Hzfor 1/11 duty cycle)270 kHz ±30%(56 to 103 Hz for1/17 duty cycle;57 to 106 Hz for1/33 duty cycle)270 kHz ±30%(56 to 103 Hz for1/17 duty cycle;57 to 106 Hz for1/33 duty cycle)Rfresistance91 k?: 5-Voperation;75 k?: 3-Voperation 68 k?: 5-Voperation;56 k?: (3-V91 k?: 5-Voperation;75 k?: 3-Voperation130 k?: 5-Voperation110 k?: 3-VoperationHD66702/HD66701Item LCD-II(HD44780)HD66702HD66701HD66710HD66712ULiquid crystal voltage booster circuit None None2-3 times step-up circuit2-3 times step-upcircuitExtension driver control signal Independentcontrol signalIndependentcontrol signal(HD66702)Used in commonwith a driveroutput pinIndependentcontrol signalReset function Power on automaticreset Power on automaticresetPower onautomatic resetPower onautomatic reset orInstructions LCD-II(HD44780)Fully compatiblewith the LCD-IIUppercompatiblewith the LCD-IIUpper compatiblewith the LCD-IINumber of displayed lines1 or 2 1 or 21, 2, or 41, 2, or 4 Low power mode None None Available Available Horizontal scroll Character unit Character unit Dot unit Dot unit Bus interface 4 bits/8 bits 4 bits/8 bits 4 bits/8 bits Serial;4 bits/8 bitsCPU bus timing 2 MHz: 5-Voperation;1 MHz: 3-Voperation 1 MHz 2 MHz: 5-Voperation;1 MHz: 3-Voperation2 MHz: 5-Voperation;1 MHz: 3-VoperationPackage QFP-1420-8080-pin bare chip LQFP-2020-144(HD66702)144-pin bare chipQFP-1420-100TQFP-1414-100100-pin bare chipTCP-128128-pin bare chipHD66702/HD66701 HD66702 Block DiagramHD66702/HD66701HD66702 Pad ArrangementHD66702/HD66701 HCD66702 Pad Location CoordinatesPad No.PadName X (µm)Y (µm)PadNo.PadName X (µm)Y (µm)1SEG34–2475235031SEG4–2475–16002SEG33–2475220532SEG3–2475–1735 3SEG32–2475206533SEG2–2475–1870 4SEG31–2475192534SEG1–2475–2010 5SEG30–2475179035GND–2475–2180 6SEG29–2475165536OSC2–2475–2325 7SEG28–2475152537OSC1–2445–2475 8SEG27–2475139538VCC–2305–24759SEG26–2475126539VCC–2165–2475 10SEG25–2475113540V1–2025–2475 11SEG24–2475100541V2–1875–2475 12SEG23–247587542V3–1745–2475 13SEG22–247574543V4–1595–2475 14SEG21–247561544V5–1465–2475 15SEG20–247548545CL1–1335–2475 16SEG19–247535546CL2–1185–2475 17SEG18–247522547M–1055–2475 18SEG17–24759548D–905–247519SEG16–2475–3549EXT–775–2475 20SEG15–2475–16550TEST–625–2475 21SEG14–2475–29551GND–495–2475 22SEG13–2475–42552RS–345–2475 23SEG12–2475–55553R/W–195–2475 24SEG11–2475–68554E–45–247525SEG10–2475–81555DB085–2475 26SEG9–2475–94556DB1235–2475 27SEG8–2475–107557DB2365–247528SEG7–2475–120558DB3515–2475 29SEG6–2475–133559DB4645–2475 30SEG5–2475–146560DB5795–2475HD66702/HD66701Pad No.PadName X (µm)Y (µm)PadNo.PadName X (µm)Y (µm)61DB6925–247591SEG88247595 62DB71075–247592SEG872475225 63COM11205–247593SEG86247535564COM21335–247594SEG852475485 65COM31465–247595SEG842475615 66COM41595–247596SEG83247574567COM51725–247597SEG822475875 68COM61855–247598SEG8124751005 69COM71990–247599SEG8024751135 70COM82125–2475100SEG7924751265 71COM92265–2475101SEG7824751395 72COM102410–2475102SEG7724751525 73COM112475–2290103SEG7624751655 74COM122475–2145104SEG752475179075COM132475–2005105SEG7424751925 76COM142475–1865106SEG7324752065 77COM152475–1730107SEG7224752205 78COM162475–1595108SEG7124752350 79SEG1002475–1465109SEG702320247580SEG992475–1335110SEG6921752475 81SEG982475–1205111SEG6820352475 82SEG972475–1075112SEG6718952475 83SEG962475–945113SEG6617602475 84SEG952475–815114SEG651625247585SEG942475–685115SEG6414952475 86SEG932475–555116SEG6313652475 87SEG922475–425117SEG6212352475 88SEG912475–295118SEG6111052475 89SEG902475–165119SEG60975247590SEG892475–35120SEG598452475HD66702/HD66701Pad No.PadName X (µm)Y (µm)PadNo.PadName X (µm)Y (µm)121SEG587152475133SEG46–8452475 122SEG575852475134SEG45–9752475 123SEG564552475135SEG44–11052475 124SEG553252475136SEG43–12352475 125SEG541952475137SEG42–13652475126SEG53652475138SEG41–14952475 127SEG52–652475139SEG40–16252475 128SEG51–1952475140SEG39–17602475 129SEG50–3252475141SEG38–18952475 130SEG49–4552475142SEG37–20352475 131SEG48–5852475143SEG36–21752475 132SEG47–7152475144SEG35–23202475 Notes: 1.Coordinates originate from the chip center.2.The above are preliminary specifications, and may be subject to change.HD66702/HD66701HD66701 Pad ArrangementHD66702/HD66701 HCD66701 Pad Location CoordinatesChip size : 5.2 × 5.2 mm2, Coordinate : PAD CENTER (µm),Orgin : CHIP CENTER, Pad Size : 90 (±10) × 90 (±10) µm2(The aperture area of a bonding pad)Pad No.PadName X (µm)Y (µm)PadNo.PadName X (µm)Y (µm)1SEG34–2475235031SEG4–2475–16002SEG33–2475220532SEG3–2475–1735 3SEG32–2475206533SEG2–2475–1870 4SEG31–2475192534SEG1–2475–2010 5SEG30–2475179035GND–2475–2180 6SEG29–2475165536OSC2–2475–2325 7SEG28–2475152537OSC1–2475–2475 8SEG27–2475139538VCC–2305–24759SEG26–2475126539VCC–2165–2475 10SEG25–2475113540V1–2025–2475 11SEG24–2475100541V2–1875–2475 12SEG23–247587542V3–1745–2475 13SEG22–247574543V4–1595–2475 14SEG21–247561544V5–1465–2475 15SEG20–2475485—Dummy–1335–2475 16SEG19–2475355—Dummy–1185–2475 17SEG18–2475225—Dummy–1055–2475 18SEG17–247595—Dummy–905–2475 19SEG16–2475–3545EXT–775–2475 20SEG15–2475–16546TEST–625–2475 21SEG14–2475–29547GND–495–2475 22SEG13–2475–42548RS–345–2475 23SEG12–2475–55549R/W–195–2475 24SEG11–2475–68550E–45–2475 25SEG10–2475–81551DB085–2475 26SEG9–2475–94552DB1235–2475 27SEG8–2475–107553DB2365–2475 28SEG7–2475–120554DB3515–2475 29SEG6–2475–133555DB4645–2475 30SEG5–2475–146556DB5795–2475HD66702/HD66701Pad No.PadName X (µm)Y (µm)PadNo.PadName X (µm)Y (µm)57DB6925–2475—Dummy247595 58DB71075–2475—Dummy2475225 59COM11205–2475—Dummy247535560COM21335–2475—Dummy2475485 61COM31465–247575SEG802475615 62COM41595–247576SEG79247574563COM51725–247577SEG782475875 64COM61855–247578SEG7724751005 65COM71990–247579SEG7624751135 66COM82125–247580SEG7524751265 67COM92265–247581SEG7424751395 68COM102410–247582SEG7324751525 69COM112475–229083SEG7224751655 70COM122475–214584SEG7124751790 71COM132475–200585SEG7024751925 72COM142475–186586SEG6924752065 73COM152475–173087SEG682475220574COM162475–159588SEG6724752350—Dummy2475–146589SEG6623202475—Dummy2475–133590SEG6521752475—Dummy2475–120591SEG6420352475—Dummy2475–107592SEG6318952475—Dummy2475–94593SEG6217602475—Dummy2475–81594SEG6116252475—Dummy2475–68595SEG6014952475—Dummy2475–55596SEG5913652475—Dummy2475–42597SEG5812352475—Dummy2475–29598SEG5711052475—Dummy2475–16599SEG569752475—Dummy2475–35100SEG558452475HD66702/HD66701Pad No.PadName X (µm)Y (µm)PadNo.PadName X (µm)Y (µm)101SEG541952475111SEG44–11052475 102SEG53652475112SEG43–12352475 103SEG52–652475113SEG42–13652475 104SEG51–1952475114SEG41–14952475 105SEG50–3252475115SEG40–16252475 106SEG49–4552475116SEG39–17602475 107SEG48–5852475117SEG38–18952475 108SEG47–7152475118SEG37–20352475 109SEG46–8452475119SEG36–21752475 110SEG45–9752475120SEG35–23202475 Notes: 1.Coordinates originate from the chip center.2.The above are preliminary specifications, and may be subject to change.HD66702/HD66701HD66702 Pin ArrangementHD66702/HD66701 Pin FunctionsTable 1Pin Functional DescriptionSignal I/O DeviceInterfaced with FunctionRS I MPU Selects registers0:Instruction register (for write)Busy flag: address counter (for read)1:Data register (for write and read)R/W I MPU Selects read or write0:Write1:ReadE I MPU Starts data read/writeDB4 to DB7I/O MPU Four high order bidirectional tristate data bus pins. Usedfor data transfer between the MPU and the HD66701/2.DB7 can be used as a busy flag.DB0 to DB3I/O MPU Four low order bidirectional tristate data bus pins. Usedfor data transfer between the MPU and the HD66701/2.These pins are not used during 4-bit operation.CL1 (HD66702)O Extension driver Clock to latch serial data D sent to the extension driver CL2 (HD66702)O Extension driver Clock to shift serial data DM (HD66702)O Extension driver Switch signal for converting the liquid crystal drivewaveform to ACD (HD66702)O Extension driver Character pattern data corresponding to each segmentsignalCOM1 to COM16O LCD Common signals that are not used are changed to non-selection waveforms. COM9 to COM16 are non-selection waveforms at 1/8 duty factor and COM12 toCOM16 are non-selection waveforms at 1/11 duty factor. SEG1 to SEG100(HD66702)SEG1 to SEG80(HD66701)O LCD Segment signalsV1 to V5—Power supply Power supply for LCD driveVCC , GND—Power supply VCC: +5V or +3V, GND: 0VTEST I—Test pin, which must be groundedEXT I—0:Enables extension driver control signals CL1, CL2,M, and D to be output from its corresponding pins.1:Drives CL1, CL2, M, and D as tristate, loweringpower dissipation.OSC1, OSC2——Pins for connecting the registers of the internal clockoscillation. When the pin input is an external clock, itmust be input to OSC1.HD66702/HD66701Function DescriptionRegistersThe HD66701/2 has two 8-bit registers, an instruction register (IR) and a data register (DR).The IR stores instruction codes, such as display clear and cursor shift, and address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can be selected (Table 2).Busy Flag (BF)When the busy flag is 1, the HD66701/2 is in the internal operation mode, and the next instruction will not be accepted. When RS = 0 and R/W = 1 (Table 2), the busy flag is output to DB7. The next instruction must be written after ensuring that the busy flag is 0.Address Counter (AC)The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction.After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1 (decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 (Table 2). Table 2Register SelectionRS R/W Operation00IR write as an internal operation (display clear, etc.)01Read busy flag (DB7) and address counter (DB0 to DB6)10DR write as an internal operation (DR to DDRAM or CGRAM)11DR read as an internal operation (DDRAM or CGRAM to DR)HD66702/HD66701 Display Data RAM (DDRAM)Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses and positions on the liquid crystal display.) is set in the address counter (AC) as hexadecimal.The DDRAM address (ADD1-line display (N = 0) (Figure 2)When there are fewer than 80 display characters, the display begins at the head position. For example, if using only theHD66702, 20 characters are displayed. See Figure 3.When the display shift operation is performed, the DDRAM address shifts. See Figure 3.Figure 1 DDRAM AddressFigure 3 1-Line by 20-Character Display ExampleHD66702/HD667012-line display (N = 1) (Figure 4)Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed from the head. Note that the first line end address and the second line start address are notconsecutive. For example, when just the HD66702 is used, 20 characters × 2 lines are displayed. See Figure 5.When display shift operation is performed, the DDRAM address shifts. See Figure 5.Figure 4 2-Line DisplayFigure 5 2-Line by 20-Character Display ExampleHD66702/HD66701 Case 2: For a 28-character × 2-line display, the HD66702 can be extended using one 40-output extension driver. See Figure 6.When display shift operation is performed, the DDRAM address shifts. See Figure 6.Figure 6 2-Line by 28-Character Display Example。
