MXP6008CT Preliminary Version

Voice Recording & Playback Device8 Minute Duration2002/5/10 Page 1APR6008Features•Multi-level analog storage-High quality audio recording and playback •Dual mode storage of analog and/or digital data -Eliminates the need for separate digital memory •Advanced, non-volatile Flash memory technology -No battery backup required •SPI interface-Allows any commercial microcontroller to control the device•Programmable Sampling Clock-Allows user to choose quality and duration levels•Single 3V power supply •Low power consumption-Playback operating current: 15 mA typical -Standby current: 1uA maximum -Automatic power-down•Multiple package options available -CSP, SOP, PDIP, Bare Die •On-board clock prescaler-Eliminates the need for external clock dividers •Automatic squelch circuit-Reduces background noise during quiet passagesGeneral DescriptionThe APR6008 offers non-volatile storage of voice and/or data in advanced Multi-Level Flash memory. Up to 8 minutes of audio recording and playback can be accommodated. A max-imum of 30K bits of digital data can be stored.devices can be cascaded for longer duration recording or greater digital storage. Device control is accomplished through an industry standard SPI interface that allows a microcontroller to manage message recording and playback.This flexible arrangement allows for the widest variety of messaging options. The APR6008 is ideal for use in cellular and cordless phones, telephone answering devices, personal digital assistants, personal voice recorders, and voice pag-ers.APLUS Integrated achieves this high level of storage capabi-lity by using a proprietary analog multi-level storage te chno l -logyi mplemented in an advanced non-volatile Flash memory process. Each memory cell can typically store 256 voltagelevels. This allows the APR6008 voice toreproduce audio signals in their natural form, eliminating the need for en co-ding and compression which can introduce distortion.Figure 1 APR6008 Pinout Diagrams/C SD I D O V S S D N C N C N CA N A O U T -A N A O U T+N C /R E S E T V S S A A U D O U T S Q L C A PS C L K V C C D E X TC L K /IN T S A C V S S A N C /B U S Y N C N C V C C A A N A IN +A N A IN -/S Q LO U TINTEGRATED CIRCUITS INC.APR6008Page 2Voice Recording & Playback DeviceRevision 2.1Functional DescriptionThe EXTCLK pin allows the use of an external sampling clock. This input can accept a wide range of frequencies depending on the divider ratio programmed into the divider that follows the clock. Alternatively, the programmable inter-nal oscillator can be used to supply the sampling clock. The Mux following both signals automatically selects the EXTCLK signal if a clock is present, otherwise the internal oscillator source is chosen. Detailed information on how to program the divider and internal oscillator can be found in the explanation of the PWRUP command, which appears in the OpCode Command Description section. Guidance on how to choose the appropriate sample clock frequency can be found in the Sampling Rate & Voice Quality section.The audio signal containing the content you wish to record should be fed into the differential inputs ANAIN-, and ANAIN+. After pre-amplification the signal is routed into the anti-aliasing filter. The anti-aliasing filter automatically adapts its response based on the sample rate being used. No exter-nal anti-aliasing filter is therefore required.After passing through the anti-alias filter, the signal is fed into the sample and hold circuit which works in conjunction with the Analog Write Circuit to store each analog sample in a flash memory cell.When a read operation is desired the Analog Read Circuit extracts the analog data from the memory array and feeds the signal to the Internal Low Pass Filter. The low pass filter converts the individual samples into a continuous output. The output signal then goes to the squelch control circuit and di-ff e rential output driver. The differential output driver feeds the ANAOUT+ and ANAOUT- pins. Both differential output pins swing around a 1.23V potential.The squelch control circuit automatically reduces the output signal by 6 dB during quiet passages. A copy of the squelch control signal is present on the SQLOUT pin to facilitate reducing gain in the external amplifier as well. For more infor-mation, refer to the Squelch section.After passing through the squelch circuit the output signal goes to the output amplifier. The output amplifier drives a sin-gle ended output on the AUDOUT pin. The single ended out-put swings around a 1.23V potential.All SPI control and hand shaking signals are routed to the Master Control Circuit. This circuit decodes all the SPI signals and generates all the internal control signals. It also contains the status register used for examining the current status of the APR6008.Figure 2 APR6008 Block DiagramSAC Low PassM a s t e r C o n t r o l C i r c u i tAmp SCLK/CS DI DO /INT /RESET AUDOUT /SQLOUTSquelchAmpA N A O U T +A N A O U T -/BUSY SQLCAPR o w D e c o d e rColumn DecoderColumn AddressRow AddressSingle Analog Memory Cell 1.92 Mcell Memory ArrayWrite CircuitLow PassRead CircuitAnalog input/output to Memory arrayPre-AmpANAIN+ANAIN-Programmable InternalOscillatorMuxEXTCLKProgrammable DividerAPR6008Voice Recording & Playback Device Page 3Revision 2.1Memory OrganizationThe APR6008 memory array is organized to allow the great-est flexibility in message management and digital storage.The smallest addressable memory unit is called a “sector”.The APR6008 contains 640 sectors.Figure 3 Memory Map.Sectors 0 through 639 can be used for analog storage. Du -ring audio recording one memory cell is used per sample clock cycle. When recording is stopped an end of data (EOD)bit is programed into the memory. This prevents playback of silence when partial sectors are used. Unused memory that exists between the EOD bit and the end of the sector can not be used.Sectors 0 through 9 are tested and guaranteed for digital storage. Other sectors, with the exception of sector 639, can store data but have not been tested, and are thus not guaran-teed to provide 100% good bits. This can be managed with error correction or forward check-before-store methods.Once a write cycle is initiated all previously written data in the chosen sector is lost.Mixing audio signals and digital data within the same sector is not possible.Note: There are a total of 15bits reserved for addressing. The APR6008 only requires 10 bits. The additional 5 bits are used for larger devices within the APR6008family.SPI InterfaceAll memory management is handled by an external host pro-cessor. The host processor communicates with the APR6008through a simple Serial Peripheral Interface (SPI) Port. The SPI port can run on as little as three wires or as many as seven depending on the amount of control necessary. This section will describe how to manage memory using the APR6008 SPI Port and associated OpCode commands.This topic is broken down into the following sections:•Sending Commands to the Device•OpCode Command Description •Receiving Device Information•Current Device Status (CDS)•Reading the Silicon Identification (SID) •Writing Digital Data •Reading Digital Data •Recording Audio Data •Playing Back Audio Data•Handshaking SignalsSending Commands to the DeviceThis section describes the process of sending OpCodes to the APR6008 All Opcodes are sent in the same way with the exception of the DIG_WRITE and DIG_READ commands .The DIG_WRITE and DIG_READ commands are described in the Writing Digital Data and Reading Digital Data sections that follow. The minimum SPI configuration needed to send commands uses the DI, /CS, and SCLK pins. The device will accept inputs on the DI pin whenever the /CS pin is low.OpCode commands are clocked in on the rising edge of the SPI clock. Figure 4 shows the timing diagram for shifting OpCode commands into the device. Figure 5 is a description of the OpCode stream.You must wait for a command to finish executing before send-ing a new command. This is accomplished by monitoring the /BUSY pin. You can substitute monitoring of the busy pin by inserting a fixed delay between commands. The required delay is specified as T next1,T next2,T next3 or T next4. Figure 6shows the timing diagram for sending consecutive com-mands. T able 1 describes which T next specification to use.Sector 0Sector 1Sector 639Can Not be Used for Digital DataSAC Trigger PointAPR6008APR6008Page 4Voice Recording & Playback DeviceRevision 2.1Figure 4Sending SPI CommandsFigure 5OpCode FormatFigure 6Opcode Stream TimingOp4 Op3 Op2 Op1T suDI A1A2T fCST rCS~~~~~~T hDI/CSSCLKDI~~~~~~A0T pSCLKT loSCLKT hiSCLKT next1, T next2, T next3, T next4Op4Op3 Op1Op0A14A13A12A11A10 A9 A8 A7 A6Op2{{First bit shifted inLast bit shifted inA5 A4 A3 A2 A1OpCode CommandOpCode Param eterA0Current Com m andNext C om m andT next1,T next2,T next3,T next4/CSSCLKDIVoice Recording & Playback Device Page 5Revision 2.1Table 1 Sequential Command TimingOpCode Command DescriptionDesigners have access to a total of 14 OpCodes. TheseOpCodes are listed in T able 2. The name of the Opcode appears in the left hand column. The following two columns represent the actual binary information contained in the 20 bit data stream. Some commands have limits on which com-mand can follow them. These limits are shown in the “Allow-able Follow on Commands ” column. The last column summarizes each command.Combinations of OpCodes can be used to accommodate almost any memory management scheme.Table 2APR6008 Operational CodesCurrent CommandNext commandTiming Symbol NOP SID Any Command T next1 5u SEC PWRUP Any CommandT next2 5m SEC STOP_PWDN PWRUPT next2 5m SECSET_REC REC STOP , STOP_PWDN, SET_REC, REC,NOPWithin SAC Low TimeSET_PLAY PLAY STOP , STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP SET_FWD FWD SET_FWD, FWD, STOP , STOP_PWDN DIG_WRITE DIG_READ DIG_ERASE Any Digital Command, STOP , STOP_PWDNNote: For partial DIG_READ T next2 is measured from the extra clock low that follows the 8K sampling rate: 376m SEC4K sampling rate: 752 m SEC rise of /CS, not from the rise of /CST next3STOPAny CommandT next4 470m SECInstructionNameOpCode(5 bits) Opcode Parameters (15bits)Allowable Followon CommandsSummary[Op4 - Op0][Address MSB - Address LSB][Address 14 - Address 0]NOP [00000] [Don’t Care] All Commands No Operation SID [00001][Don’t care]All Commands Causes the silicon ID to be read. SET_FWD[00010]Sector Address [A14 - A0]SET_FWD, FWD, STOP , STOP_PWDN Starts a fast forward operation from the sector address specified.FWD [00011][Don’t care]SET_FWD, FWD, STOP , STOP_PWDNStarts a fast forward operation from the current sector address.PWRUP [00100][A14-A10]: all zeros [A9-A2]: EXTCLK divider ratio [A1-A0]: Sample Rate FrequencyAll Commands Resets the device to initial conditions.Sets the sample frequency and divider ratios. STOP [00110][Don’t care]All Commands Stops the current operation.STOP_PWDN[00111][Don’t care]PWRUPStops the current operation. Causes the device to enter power down mode.APR6008APR6008Page 6Voice Recording & Playback DeviceRevision 2.1The NOP command performs no operation in the device. It is most often used when reading the current device status. For more information on reading device status see the Current Device Status section.THE SID operation instructs the device to return the contents of its silicon ID register. For more information see the Read-ing the SID section.The SET_FWD command instructs the device to fast forward from the beginning of the sector specified in the OpCode parameter field. The device will fast forward until either an EOD bit, or the end of the sector is reached. If no EOD bit or forthcoming command has been received when the end of the sector is reached, the device will loop back to the begin-ning of the same sector and begin the same process again. If an EOD bit is found the device will stop and generate an interrupt on the /INT pin. The output amplifiers are muted dur-ing this operation.The FWD command instructs the device to fast forward from the start of the current sector to the next EOD marker. If no EOD marker is found within the current sector the device will increment to the next sequential sector and continue looking.The device will continue to fast forward in this manner until either an EOD is reached, a new command is sent, or the end of the memory array is reached. When an EOD is reached the device will stop and generate an interrupt on the /INT pin.The output amplifiers are muted during this operation. The PWRUP command causes the device to enter power up mode and set the internal clock frequency and EXTCLK divider ratio. To select an Internal oscillator frequency set the [A1 - A0] bits according to the following binary values:If you are using an external sample clock signal you must also set the EXTCLK divider ratio. This divider ratio is equal to N:1 where N is an integer between 1 and 256, excluding 2.The N value should be selected to satisfy the following equa-SET_REC [01000]Sector Address [A14 - A0]STOP , STOP_PWDN, SET_REC, REC,NOP Starts a record operation from the sector address specified.REC [01001] [Don’t care]STOP , STOP_PWDN, SET_REC, REC,NOPStarts a record operation from the current sector address.DIG_ERASE [01010]Sector Address [A14 - A0]All Commands Erases all data contained in specified sec-tor. You must not erase a sector before recording voice signals into it. You must erase a sector before storing digital data in it.DIG_WRITE [01011][A14 - A0][XXXX][D0 - D3004][XXXX]All CommandsThis command writes data bits D0 - D3003 starting at the specified address. All 3004 bits must be written.DIG_READ [01111]Sector Address [A14 - A0]All Commands This command reads data bits D0 - D3003starting at the specified address.SET_PLAY[01100]Sector Address [A14 - A0]STOP , STOP_PWDN, SET_FWD, FWD, SET_PLAY ,PLAY ,NOP Starts a play operation from the sector address specified.PLAY [01101][Don’t care]STOP , STOP_PWDN, SET_FWD, FWD, SET_PLAY ,PLAY ,NOPStarts a play operation from the current sector address.InstructionNameOpCode(5 bits) Opcode Parameters (15bits)Allowable Followon CommandsSummary[Op4 - Op0][Address MSB - Address LSB][Address 14 - Address 0]A1 A0 Sample rate 0 0 6.4 kHz 0 1 4.0 kHz 1 0 8.0 kHz 115.3 kHzVoice Recording & Playback Device Page 7Revision 2.1tion as closely as possible:EXTCLK freq = (N) * (128) * (selected sampling frequency)Example:Suppose that 8.0 KHz sampling is desired. Assume thatthe frequency of the signal present on EXTCLK = 8MHz.Rounding up, N = 8The Op Code Parameter bit stream, composed of bits [A9 - A2][A1 - A0], therefore becomes binary [00001000][10].The STOP Command causes the device to stop the current operation.The STOP_PWDN command causes the device to stop the current command and enter power down mode. During power down the device consumes significantly less power. The PWRUP command must be used to force the device into power up mode before any commands can be executed.The SET_REC command instructs the device to begin recording at the sector address specified. The device will continue to record until the end of the current sector is reached. If no forthcoming command has been received when the end of the sector is reached the device will loop back to the beginning of the same sector and overwrite the previously recorded material. If the next command is another SET_REC or REC command the device will execute the com-mand immediately following the end of the current sector so that no audio information is lost. For more information see the section entitled Recording Audio Data .The REC command instructs the device to begin recording in the current sector. If no new command is received before the device reaches the end of the sector the device will automati-cally increment to the next sequential sector and continue recording. The device will continue to record in this manner until the memory is exhausted or a STOP or STOP_PWDN command is received. For more information see the section entitled Recording Audio Data .The DIG_ERASE command erases all data contained in the sector specified. Erase should not be done before recording voice signals into a sector. Erase must be done before storing digital data in a sector.The DIG_WRITE command stores 3K bits of digital data in the specified sector. All 3K bits must be written, no partial usage of the sector is possible. The memory acts as a FIFO,the first data bit shifted in will be the first data bit shifted out. A sector must be erased using the DIG _ERASE command BEFORE data can be written to the sector. For more informa-tion on storing digital data, see the section entitled Writing Digital Data .The DIG_READ command instructs the device to retrievedigital data that was previously written to the specified sector.The first bit shifted out is the first bit that was written. The last bit shifted out is the last bit that was written. For more infor-mation on reading digital data see the section entitled Read-ing Digital Data.The SET_PLAY command instructs the device to begin play-back at the specified sector. If no forthcoming command is received, or EOD bit encountered, before the end of the sec-tor is reached the device will loop back to the beginning of the same sector and continue playback with no noticeable gap in the audio output. If the next command is another SET_PLAY or PLAY command the device will execute the command immediately following the end of the current sector so that no gap in playback is present. For more information see the sec-tion entitled Playing Back Audio Data.The PLAY command instructs the device to begin playback at the current sector. If no forthcoming command is received, or EOD bit encountered, before the device reaches the end of the sector the device will automatically increment to the next sequential sector and continue playing. The device will con-tinue to play in this manner until the memory is exhausted or a STOP or STOP_PWDN command is received. For more information see the section entitled Playing Back Audio Data.N 80000001288000()-------------------------7.8125==APR6008APR6008Page 8Voice Recording & Playback DeviceRevision 2.1Receiving Device InformationThe device communicates data to the user by shifting out data on the DO pin. The device will shift out data according to the timing parameters given in figure 7. The device can shiftout three different types of data streams: Device status, Sili-con ID, and user stored data. Device status and silicon ID are described in the next two sections. Retrieval of user data is described in the Reading Digital Data section.Figure 7 Data Out TimingCurrent Device Status (CDS)As described in the previous section, three different types ofdata streams are shifted out on the DO pin as data is shifted in on the DI pin. One of these steams is the current device status. The CDS will be shifted out unless the previous com-mand is SID command. Figure 8 shows the format of the CDS bit stream. The first bit shifted out, D0, is the Overflow flag. The Overflow flag is set to a binary 1 if an attempt was made to record beyond the available memory. The Overflow flag is set to a 0 if an overflow has not occurred. This flag iscleared after it has been read. The D1 bit is the End of Data flag. The EOD flag is set when the device stops playing, or fast forwarding as a result of an EOD bit in memory. The EOD flag is cleared after it has been read. The D2 bit is the Illegal Address flag. The Illegal Address flag is set whenever an ille-gal address is sent to the device. The D3 bit is the Lbat flag.This flag is set when the device senses a supply voltage below specification. The D4 bit is not used and should be ignored. The last fifteen bits represent the address of the cur-rent or last active sector.Figure 8Format for CDS Bit StreamOp4 Op3 Op2 Op1 A1A2A0/CSSCLKDID0 D1 D2 D18 D17 D19D16 D3~~~~~~DOT fcsDOT fSCLKT hzD0D15~~A3LbatOVFEODIllegal AddressD0D1 D3 D4D5 D6 D7 D8D9D10 D11 D12 D13 D14D2~~D19}First bit shifted outLast bit shifted out Sector AddressSector Addre ss MSB Sector Add res sLSBAPR6008Voice Recording & Playback Device Page 9Revision 2.1Reading the SIDEach device in the APR60XX series family contains anembedded Silicon Identification (SID). The SID can be read by the host processor to identify which family / family member is being used. Reading the device SID requires issuing twoOpCode commands; a SID command followed by any other command, usually a NOP command. The device will clock the SID data out on the DO pin as the command that follows the SID command is clocked in. Figure 9 is a diagram that describes the process necessary for reading SID information.Figure 9SID TimingThe SID information follows the format given in Figure 10.The first bit shifted out, D0, is the Overflow bit. The Overflow bit is set to a binary 1 if an attempt was made to record beyond the available memory. The Overflow bit is set to a 0 if an overflow has not occurred. This bit is cleared after it has been read. The D1 bit is the End Of Data (EOD) bit. The EOD bit is set when the device stops playing or fast forwarding as a result of EOD bit in memory. The EOD bit is cleared after it has been read. The D2 bit is the Illegal Address Bit. The Ille-gal Address Bit is set whenever an illegal address is sent tothe device. The D3 bit is the Lbat bit. This bit is set when the device senses a supply voltage below specification. The fol-lowing five bits represent the product family. The APR60XX product family code is binary 01000 as shown in Figure 10.The next four bits represent the device code. The APR6008device code is binary 0100 as shown in Figure 10 The last seven bits are random data and should be ignored.Figure 10SID Bit StreamSID Com m and Next Com m and/CSSCLKDI CD S O utput D ata SID O utput DataDOLbatOVFEODIllegal AddressD0D1D3D4D5D6D7D8D9D10D11D12D13D14D2}ProductFamily}01~~D1910Device Code }APR60XX SeriesFamily (Binary)}APR6008 DeviceCode (Binary)}Ignore These BitsFirst bit shifted outLast bit shifted outPage 10Voice Recording & Playback DeviceRevision 2.1Writing Digital DataDigital data is written into the device using the DIG_WRITE command. No mixing of analog data and digital data within a sector is possible. Sectors 0 through 9 are tested and guar-anteed for digital storage. Other sectors, with the exception of sector 639, can store data but have not been tested, and are thus not guaranteed to provide 100% good bits. This can be managed with error correction or forward check-before-store methods. Issuing a DIG_ERASE command on sector 639 will cause data throughout all sectors to be lost.A sector must be erased, using the DIG_ERASE command,before digital data can be written to it. This requirement is necessary whether analog data or digital data was previously stored in the sector. A sector should not be erased more than once between analog or digital write operations. Executing multiple erase operations on a sector will permanently dam-age the sector. A sector can be reallocated to either analog storage or digital storage at any time.The process of storing digital data begins by sending a DIG_WRITE command. The DIG_WRITE command is fol-lowed immediately by four buffer bits. These bits will not be stored in the array and must be considered don’t care bits.Immediately following the four buffer bits should be the data that you wish to store. All 3004 bits must be stored. Four additional buffer bits must be clocked into the device follow-ing the stored data. These bits will not be stored in the array and must be considered don’t care bits. Ending a digital write command early will permanently damage the sector. The DO pin will clock out the normal 20 bit CDS followed by five don’t care bits, a copy of the 3004 data bits, and finally three don’t care bits.Figure 11 shows a timing diagram which describes the digital storage process. All timing with the exception of T pSCLK should adhere to the specifications given in Figure 4 and Fig-ure 7. The T pSCLK specification is replaced by the DT pSCLK when storing digital data.Note: The DIG_ERASE command should not be used before storing analog data. The device will perform its own internal erase before analog storage.Figure 11 does not show the DIG_ERASE command which must be executed on a sector before digital data can be stored.Figure 11Writing Digital Data/CSSCLKD IDOCDSCopy of the input data (delayed one clock cycle)Four Don’t Care BitsT otal 3032 clock cyclesXX X X X X X X DIG_WRITECOMMAND 3004 bits of data to be stored X XX X X X X XAPR6008Reading Digital DataDigital data is read from the device using the DIG_READ command. To read data you must send a DIG_READ com-mand immediately followed by 3012 don’t care bits during the same /CS cycle. The data previously stored in the specified sector will begin to appear on the DO pin after the current device status or SID and four buffer bits. The next 3004 bits are the previously stored data. The first bit shifted out is the first bit that was written. The last bit shifted out is the last bit that was written. There are four random don’t care bits follow-ing the 3004 bits of user data.An incomplete read of the sector is allowed. An incomplete read is defined a a read with less than 3032 clock cycles. All incomplete read cycles require one extra SCLK cycle after the /CS signal returns high.Figure 12 shows a timing diagram which describes the entire process for a complete sector read. All timing with the excep-tion of T pSCLK should adhere to the specifications given in Figure 4 and Figure 7. The T pSCLK specification is replaced by the DT pSCLK when reading digital data.Figure 12Reading Digital Data/CSSCLKDI DODIG_READ COMMAND 3012 don’t Care BitsTotal 3032 clock cyclesSID or CDS 3004 bits of previously stored data X XX X X X X X A P R 6008Page 12Voice Recording & Playback DeviceRecording Audio DataWhen a SET_REC or REC command is issued the device will begin sampling and storing the data present on ANAIN+ and ANAIN- to the specified sector. After half the sector is used the SAC pin will drop low to indicate that a new command can be accepted. The device will accept commands as long as the SAC pin remains low. Any command received after the SAC returns high will be queued up and executed during the next SAC cycle.Figure 13 shows a typical timing diagram and OpCode sequence for a recording operation. In this example the SET_REC command begins recording at the specified mem-ory location after T arec time has passed. Some time later thelow going edge on the SAC pin alerts the host processor that the first sector is nearly full. The host processor responds by issuing a REC command before the SAC pin returns high.The REC command instructs the APR6008 to continue recording in the sector immediately following the current sec-tor. When the first sector is full the device automatically jumps to the next sector and returns the SAC signal to a high state to indicate that the second sector is now being used. At this point the host processor decides to issue a STOP command during the next SAC cycle. The device follows the STOP command and terminates recording after TS arec .The /BUSY pin indicates when actual recording is taking place.Figure 13Typical Recording Sequence/CSSCLKDITarecTSarecSET_RECSTOPSACANAOUT+ANAOUT-ANAOUT/BUSYREC APR6008。

Page: 1 of 7 RELEASE NOTES for Power Xpert (TM) PXM4000/6000/8000 Meter(C) Copyright Eaton Corporation 2017Meter Version 13.4.0.10Built: 09/21/2017These release notes are provided as a guide to help troubleshoot issues withalready installed Power Xpert meters from previous releases.This document is not intended to be all-inclusive.--------------------------------------------------------------------------------Table of Contents1.0 Product Description2.0 System Requirements3.0 Compatible Devices4.0 New Features5.0 Known Issues--------------------------------------------------------------------------------1.0 Product Description--------------------------------------------------------------------------------The Eaton Power Xpert PXM4000/6000/8000 Meter is a multifunctional revenue-accuratepower meter providing power quality analysis. It consists of a panel-mounted DisplayModule and a Base Meter Module that can be attached to the Display Module or mountedremotely. The Power Xpert Meter is a multi-processor based electrical distributionsystem monitor that provides extensive:• Metering• Trending• Logging• Waveform capture• Transient capture• Remote input monitoring• Control relaying/Alarming• Communication capabilities• Built-in Web server for browsing via the internetIn addition, it incorporates a number of value added features such as self-learning,adaptive reporting, networked display, user levels, intuitive graphic displays,and user text descriptions.--------------------------------------------------------------------------------2.0 System Requirements--------------------------------------------------------------------------------2.1 LAN RequirementsFor web-page access on LAN/WAN, port 80 must be open [inbound]For web-service access on LAN/WAN, port 8080 must be open [inbound]For web-service access on LAN/WAN, port 8081 must be open [outbound]For secure web-service (SSL) access on LAN/WAN, port 443 must be open [inbound]For Modbus TCP access on LAN/WAN, port 502 must be open [inbound and outbound]For firmware upgrades on LAN/WAN, port 7693 must be open [inbound and outbound]For network time protocol (NTP), UDP port 123 must be open [inbound and outbound]For email notifications, port 25 must be open [outbound]For SNMP, ports 161 and 162 must be open [inbound and outbound]For FTP data on LAN/WAN, port 20 must be open [outbound]For DNP 3.0 port 20000 must be open [inbound and outbound].2.2 Supported Browser RequirementsPage: 2 of 7 IE : 11.0.37Chrome : 55.0.2883.87Safari : 9.1.1Edge : 14--------------------------------------------------------------------------------3.0 Compatible Devices--------------------------------------------------------------------------------3.1 Option Card DefinitionsPXMIO-B (Discrete Input/Output - Optional)PXMCE-B (Communication Expansion - Optional)PXMCM-1 (Communication Main - Standard)PXMPS-1 Power Supply Card - Standard)--------------------------------------------------------------------------------4.0 New Features and Fixes--------------------------------------------------------------------------------METER FIRMWARE 13.4.0.10 (SEPT 2017)•Fix for coreapp "sendqueue" reboot in variable frequency mode.•Fix to post last updated total energy accumulation in Modbus registers after rebootingin zero voltage condition.•Provided ITIC curve graph and fixed trigger tab issues on HTML5.•Provided fix for incorrect Phasors in delta configuration on HTML5.•Updated 3rd party components & general security improvements.•Improved system peformance.•Includes pruning of .csv files under low disk space condition.METER FIRMWARE 13.4.0.8 (JUNE 2017)•Fix for DSP lockup & eventual "Rebooted by coreapp sendqueue" when configured for 50Hz• Removes changes made in 13.4.0.5 and 13.4.0.7METER FIRMWARE 13.4.0.7 (MAY 2017)•Fix for event-flurry seen in meters that booted up on a dead bus.•Includes fix for “sendqueue” reboot caused by DSP inactivity on dead bus.METER FIRMWARE 13.4.0.5 (MAR 2017)•Changes in DSP initialization for 50Hz Meter frequency.METER FIRMWARE 13.4.0.4 (FEB 2017)•Added Modbus registers for firmware version starting at 10000.•Fixed HTML5 UI to enable saving of Apparent Power Phase B trigger.•Fixed incorrect PXM4000 display of EVEN/ODD/INTER HARMONIC under Quality Page.METER FIRMWARE 13.4.0.2 (DEC 2016)•Includes new HTML 5 UI as default. The old UI still accessible underhttp://<meterip>/java.html•Reverted automatic NAND-flash repartitioning. Meter Firmware now Updates the NANDFirmware if deemed old.•Reverted DSP Sendqueue reboot added in 13.3.7.0•Modbus registers for Current Phase Angle and Voltage Phase Angle now updated properly.•Fix to address problem with auto backoff of Trigger Thresholds.•Account lockout and Password expiration should be disabled by default.METER FIRMWARE 13.3.7.0 (AUGUST 2016)•NAND Maintenance reboot feature (with hard reset of scsi drive) added to preventdepletion of spare areas on the NAND module.•Includes fix for “sendqueue” reboot caused by DSP issue when PXM is running on DC inthe absence of AC signal.METER FIRMWARE 13.3.6.5 (JUNE 2016)•Recovery added for NAND storage error.•Includes the Modbus registers for THD voltage and THDcurrent values now available atPage: 3 of 7 the location 14200 to 14302.•Includes the Modbus registers for THD current and TDD current percentages added to theModbus map from the location 14304 to 14406 .•Includes the THD magnitude and THDVoltage/TDD Current percentage registers valuesavailable on BACnet through EPICS files.•Includes changes in EPICS file format.•Includes newer glibcMETER FIRMWARE 13.3.6.1 (DEC 2015)•Includes support for extended waveform capture.•Fix for PXDCM unable to discover the meter.METER FIRMWARE 13.3.5.10 (OCT 2015)•Includes support for periodic harmonic waveform capture.•Local LAN configuration port now works on http.METER FIRMWARE 13.3.5.6 (MAY 2015)•Includes migration to TLSv1.2 with disabling of SSLv3 and weak ciphers for TLS•Fixes the glibc security issue i.e. Qualys Security Advisory CVE-2015-0235 -GHOST:glibc gethostbyname•Fixes the Network Time Protocol Vulnerabilities - ICS-VU-644440•Fixes the issue that Modbus Trend and Profile Query Registers do not behave asdocumented in instruction manual•Com1 port default setting changed to "Slave(RTU)" to work with the HMI automaticallywithout requiring a setup session to configure the port•Fixes the PXMeter468K Discovery on BACnet network i.e. sending an I-Am message inresponse to a Broadcast Who-Is messageMETER FIRMWARE 13.3.5.4 (DEC 2014)•Modbus network disconnect feature disabled•Fix for Local Timeout Error occurred during firmware upgrade•Includes Support for BACnet/IP•Includes support for Secure FTP•Includes Enhanced 60 cycle FFT with .CSV output•Includes ability to use custom strings for discrete inputs•Fixes inconsistent performance with PXM Status input triggered events•Fixes ITIC Sag Event incorrect labelling•Fixes FTP being accessible after Factory Reset of the meter. By default SFTP is enabledand FTP disabled•Capture parameter functionality for Sub-cycle Disturbance Event and Fast TransientTriggers updatedMETER FIRMWARE 13.3.5.3 (Nov 2014)•Includes Support for BACnet/IP•Includes support for Secure FTP•Includes Enhanced 60 cycle FFT with .CSV output•Includes ability to use custom strings for discrete inputs•Fixes inconsistent performance with PXM Status input triggered events•Fixes ITIC Sag Event incorrect labelling•Fixes FTP being accessible after Factory Reset of the meter. By default SFTP is enabledandFTP disabled•Updated captured parameters for Sub-cycle Disturbance Event and Fast Transient Triggers updatedMETER FIRMWARE 13.3.5.0 (Apr 2014)•Security fix for NTPMETER FIRMWARE 13.3.4.3 (Jan 2014)•Adds Semi-F47 sag triggers•Includes updated Java JVM•Fixes incorrect data points in the energy profile•Fixes empty source path for channel alarms via BACnetWS+•Fixes the calculation of the minimum fast-transient reset threshold•Fixes instance in the UI where the Save Table button did not save the trend data for the displayed attribute on the Meter tab•Fixes an issue that would cause the loss of communication within 3 hours of rebootPage: 4 of 7 •Fixes instance where the phase-to-phase voltage in Events List > Captured Parameterswould bedisplayed incorrectly•Fixes a number of text errors.•Disables DNP in default configurationMETER FIRMWARE 13.3.2.10 (Apr 2013)•Adds DNP3.0 protocol support•Adds Chinese user interface support to Java•Adds manual Fast Transient Capture to the PXM8000METER FIRMWARE 13.3.1.11 (Feb 2012)•Improves Modbus TCP socket handling to prevent false error counts when checking forextra datathat occurs from a subsequent request•Changes NetPhy driver to use Synchronous mode. This reduces the number of framingerrors forlarge packets, especially during firmware upgrades.[The root cause of framing errors was the lack of termination on the unused Ethernet TXclock]METER FIRMWARE 13.3.1.8 (Jan 2012)•Adds support for replacement real-time-clock chip and moved its FRAM functions to newSPI FRAM•Reduces SPI FRAM clock from 40MHz to 20MHz and simplified user-space drivers•Adds factory backup of EEPROM contents in first 256 bytes of SPI FRAM•Fixes Modbus master driver fix for RS485 to articulate Modbus TCP Transaction IDMETER FIRMWARE 13.3.1.3 (Jan 2012)•Includes support for new PXMCM-1 and PXMCE-B with backward compatibility with older CM and CE cards (see Manual addendum for description of new cards)•Fixes scenarios where MAC addresses and calibration would be lost whenconnected to a LAN with a 192.168.x.x subnet.•Adds Com Reset feature to restore EEPROM calibration and MAC addresses to the state as shipped from the factory when mode switches SW1 and SW2 are in theON position. The Com Reset functions with the other modes remain unchanged.-OFF OFF: Resets Local Configuration port to 192.168.1.1 and LAN to DHCP-ON OFF: Reset/Cycle NetPhy-OFF ON: Resets Local Configuration port to 192.168.1.1 and sets LAN to 10.1.1.1-ON ON: Resets EEPROM calibration, MAC addresses, IP addresses etc. to the state as shipped from the factory• Improves Modbus timing to account for masters that cannot handle immediate responses• Updates Linux kernel to 2.6.35.7--------------------------------------------------------------------------------5.0 Known Issues--------------------------------------------------------------------------------- Mask Field for Modbus TCP access does not accept X.X.X.X on HTML5- In variable frequency mode, performance is not consistent across entire frequencyrangge.Ripple in RMS values have been observed in this mode and this can lead to a flurry ofevents.- On HTML5 GUI, for voltage unbalance, lower magnitude current phasor line appears tooshort.- Last Demand Reset time stamps in the bottom left corner on the TOU page are incorrect.They are not as per the selected time zone. Time is displayed as UTC time.- On the HTML UI, ITIC curve requires a page refresh to update event counts.On the event list, ITIC events are updated automatically.- For all energy & demand options on Energy Page, user can only save the graph data in the viewable data for the selected page. User can access FTP files to get the entire data.Page: 5 of 7 - Only 5 maximum web connections are working on HTML UI.- On an IPAD, the Home quality card is not responsive and buttons get cut off.- On an HMI Display, the user needs to set the IE resolution <100% to get thefull screen view. Scroll bar is not visible.- For Apparent Power Phase B trigger not saving on HTML UI, but on the Java UI usercan save this trigger.- Waveform distortion at zoom level 6 and Zoom Level 7 at Quality and Meter Page causedby decimation of the waveform data determined by screen resolution.- For PXM4000 meter - Improper UI display of EVEN/ODD/INTER HARMONIC under Quality Pageeventhoughthese options are not applicable for PXM4000.- Upgrade of daisy-chained meters, slaves meters via master meter or the slavedisplays not supported with HTML. F/W upgrade via HTML5 requires Ethernet communications session to each meter.- The system log on the local display is limited to the 60 most recently logged items.- CSV Profile data occasionally has duplicate values and incorrect date/time stampingUTC vs Local time.- Some trigger-list items for the Relay Output selections are misnamed or irrelevant.For example, L1sags and L1swells do not generate events. The “Modbus None” item isreally the “Capture Waveform” command that Foreseer software initiates through ModbusRegister#2901 control 00030001.- The meter’s setup screens contain items for many of the PXM4000/6000/8000features, regardless of whether they are installed. For example, there isa Vaux PT ratio setting on the QuickSetup page that only applies to meters withVaux channels [V6, V7 and V8].- When the LAN IP address and Local Configuration port addresses are inconflict, the meter reassigns the local address from 192.168.1.1 to 10.1.1.1.Given this, try 10.1.1.1 when the Local Configuration port fails to respondto 192.168.1.1. In order to get the Local Configuration back to 192.168.1.1,temporarily set the LAN address to 10.1.1.1. At that point the meter's LocalConfiguration IP address changes back to 192.168.1.1.- The Diagnostics section includes the Event Counts web page; however, items arenot clearly defined.- Because the Pst and Plt flicker values update at 10-minute intervals, themin, max and average values would be the same at Zoom1 (5-minute interval).For this reason the Zoom1 for these values omit the min and max. However,these values will appear as duplicates in the Modbus register set.- Blanks appear in the Energy Comparison tables When the meter is notoperational at midnight. Blanks may also occur when the time zone is changedafter historical data has been accumulated- When discrete inputs are used to trigger Waveform captures, trigger delaysettings of more than a 2 seconds could result in no waveform being captured.The system includes a circular buffer of waveform data that may be overwrittenwhen long delays are specified.- The interpretation of Energy & Demand Profiles & Comparisons become unclearwhen the meter loses power. The daily demand is the average demand for thetime that the meter was running. As a result, the daily energy estimate usedto generate comparison charts and tables may exceed the accumulated energyreported in the meter's energy rate accumulators. That is, for relativePage: 6 of 7 comparison purposes, the Energy Comparison charts and tables assume that powerconsumption during times when the meter was not operating can best be estimatedusing the daily average power measured by the meter while it was operating.The energy rate accumulators do not make any assumptions about energyconsumption while the meter is not in operation. Energy rate accumulators andpeak demands report precisely what is measured.- There are several setup requirements for the PXM4000/6000/8000 to send email.1)Hostname must have no spaces (e.g. PowerXpertMeter)2)Domain name must be valid (automatic when using DHCP)3)Domain Name Server (DNS) must be valid (automatic when using DHCP)4)SMTP server must be valid (e.g. )5)Use an Account/ID and Password that is valid for the selected SMTP server.- Trend Table is missing min and max values when power goes from forward to reverse.Meanwhile, the graph of power above the table is correct.- The waveform graphs on the Quality page incorrectly indicate “%” when Current TDD%or Voltage THD% are selected. Waveforms are always displayed in either Volts or Amperes.- The harmonic spectrum graphs on the Quality page incorrectly indicate “%” when CurrentTDD% or Voltage THD% are selected. The spectrum and table always present Volts andAmperes.- When viewing a transient waveform, zooming in beyond the selected sampling rate resultsin waveform that looks like a staircase.- On the Energy page: peak demands are displayed as positive, even on the Reverse andNet Energy graphs.- A reboot is required when changing Com3 settings- Resetting Energy or Demand also clears the last reset value of both- On the Home page, initial gauge levels are incorrect until voltage is present- On the local display, the "Incoming L-L voltage" setting has no function.Instead, use the "Line to Line Voltage" setting in QuickSetup.- When viewing the Harmonic Spectrum at Zoom2 or Zoom3, the x-axis labels are only correctwhen the measured system frequency is in the range of 49.5Hz-50.5Hz or 59.5-60.5Hz- Meters used as a Master-Gateway must be rebooted manually following a firmware upgrade- When configuring a communications port as Master-Gateway, a reboot is recommended afterthe configuration change- As shipped from the factory, a new meter requires 4-5 minutes to create default filestructures and settings on power up.- QuickSetup of CT ratios, PT ratios, Wiring Configuration and Incoming VLL are required.In the initial boot-up as received from the factory, the CT ratio appears to be set for5000:5, but it is really 5:5 until the next reboot.- The meter’s real-time clock is set for factory time but with the default UTC/GMT timezone.- In the meter’s default mode-switch configuration, the Com Reset button forces theLAN/WANto DHCP operation. As a result, a fixed IP address would be lost.- Until a load is measured, the Gauges on the Home page default to the middle positionrather than the bottom position as would be consistent with 0 Amperes.- The Com1 and Com2 settings cannot be changed with the local display interface, only withGUI through the display's Ethernet port.Page: 7 of 7 - When viewing a VAUX VBC waveform on the local display, the only way out is via theBack button.- Following a Reboot or Power Cycle, the Transient counter on the ITIC Summary page issubject to error. The filtered view on the Event list page shows the correct events inthe list, but the filtered count shown at the top of the Event list may not be correct.- When creating User Names special characters should not be used. RestrictUser Names to Alpha-Numeric values. Do not use spaces, underscores, dashesor other non Alpha-numeric values.- The Comtrade formatted event waveforms contain Vng, even for configurations withouta neutral. The Vng waveform should be ignored in systemswithout a neutral.- In some instances upgrading PXM 4/6/8K might result in the Meter lock-up i.e. meter doesnot recover after the upgrade. To recover the unit you may have to powercycle severaltimes.Updated 26SEPT2017。

Datasheet Fujitsu Desktop ESPRIMO G9012Fujitsu recommends Windows 11 ProA smart and ultra-compact Mini PC for advanced office needsThe Fujitsu E SPRIMO G9012 is a smart Mini PC which offers advanced Desktop PC functionality in an ultra- compact, space-saving design. Making it a perfect device for working from home or in flexible workplaces with its single cable USB Type-C ® connection. Provided with the latest 13th generation Intel ® Core™ processors and Intel vPro ® technology, the devices empower impressive performance/volume ratio.A smart Mini PC with ultra-compact design Eye-catching exclusive modern design• Low noise Mini PC thus providing ergonomic, clean, and clutter-free working environment • Offers advanced desktop PC functionality with a volume of only 0.87 liters •Impressive performance/volume ratio and is easy to set up in minutesSmall in size but grand in performanceHigh performance in a small Mini PC design• Latest Intel chipset technology and 13th generation Intel ® Core™ processor family • With Intel vPro ® version for latest out-of-band management features •Next generation Intel integrated graphicsFlexibility without limitsPleasant working environment due to quiet system• Concept with different heights allows ODD and upgrade options like power supply and PCIe slot • Flexibility for later device upgrades •Various mounting optionsUltimate usability - Perfect fit for modern offices and workplaces• Integrated into Fujitsu AIO Display P2410 enables a space saving all-in-one system• Can be used for horizontal or vertical operations and easy upgrade of major components • VESA mount for attaching the PC to displays, stands or walls•Ideal device to use for home office scenarios due to its mobility and one cable solutionLow power consumption and environmental impact Reduced environmental impact and reduced energy bills•Highly efficient AC adapter 80Plus PLATINUM or internal power supply as optionSpecificationESPRIMO G9012 ESPRIMO G9012 ESTARxProcessor Intel® Core™ i7-13700 processor (16 Cores (8+8)/24 Threads, 2.1 GHz, 30 MB, Intel® UHD Graphics 770)**^ Intel® Core™ i5-13500 processor (14 Cores (6+8)/20 Threads, 2.5 GHz, 24 MB, Intel® UHD Graphics 770)*Intel® Core™ i5-13400 processor (10 Cores (6+4)/16 Threads, 2.5 GHz, 20 MB, Intel® UHD Graphics 730)*Intel® Core™ i3-13100 processor (4 Cores/8 Threads, 3.4 GHz, 12 MB, Intel® UHD Graphics 730)*Intel® Core™ i7-12700 processor (12 Cores(8+4)/20 Threads, 2.1 GHz, 25 MB, Intel® UHD Graphics 770) **Intel® Core™ i5-12500 processor (6 Cores/12 Threads, 3.0 GHz, 18 MB, Intel® UHD Graphics 770) *Intel® Core™ i5-12400 processor (6 Cores/12 Threads, 2.5 GHz, 18 MB, Intel® UHD Graphics 730) *Intel® Core™ i3-12100 processor (4 Cores/8 Threads, 3.3 GHz, 12 MB, Intel® UHD Graphics 730) *Intel vPro® Platform Logo (optional) with Intel® Core™ i5-12500, i5-13500 and Intel® Core™ i7 processors*With Intel® Turbo Boost Technology 2.0 (clock speed and performance will vary depending on workload andother variables)**With Intel®Turbo Boost Max Technology 3.0 (clock speed and performance will vary depending onworkload and other variables)^90 Watt AC adapter is required for maximum CPU performanceOperating systemsOperating system pre-installed Windows 11 Pro. Windows 11 Home.Windows 10 Pro (Via Windows 11 Pro Downgrade Option) Fujitsu recommends Windows 11 Pro for business.Memory modules16 GB (1 module(s) 16 GB) DDR4, unbuffered, non-ECC, 3,200 MT/s, SO DIMM.8 GB (1 module(s) 8 GB) DDR4, unbuffered, non-ECC, 3,200 MT/s, SO DIMM4 GB (1 module(s) 4 GB) DDR4, unbuffered, non-ECC, 3,200 MT/s, SO DIMMGraphics Entry 3D: NVIDIA®T600, 4 GB, PCIe x16, 4 x miniDPEntry 3D: NVIDIA®T400, 4 GB, PCIe x16, 3 x miniDPOthers: MiniDP to DP Adapter Cable*Optional in Int. PSU versionHDD 2.5 inch size HDD SATA III, 5,400 rpm, 1000 GB, 2.5-inch HDDSATA III, 5,400 rpm, 2000 GB, 2.5-inchM.2 SSD SSD PCIe, 2048 GB M.2 NVMe (Gen4), SEDSSD PCIe, 1024 GB M.2 NVMe (Gen4), SEDSSD PCIe, 512 GB M.2 NVMe (Gen4), SEDSSD PCIe, 256 GB M.2 NVMe (Gen4), Value, SEDHard disk notes One Gigabyte equals one billion bytes, when referring to hard disk drive capacity. SSD(Solid State Disk)SED (Self-Encrypting Drive)2.5-inch bay for devices with 7mm heightDurability in accordance with the manufacturer’s indications on read and write cycles.Optical drive DVD Super Multi ultra slim (tray), SATA (optional)Wireless LAN Intel® Wi-Fi 6E AX211 (2x2/160) Gig+ and Bluetooth 5.2 vPro (depends on OS support); SRD cat.1 (6E frequency only in dedicated regions)Wireless LAN Notes WI-FI 6E: The device does not operate in 6GHz band in all countries, depending on individual local regulations.Expansion notes The listed product components and optionalfunctions are not available in all region/countries;System is available in 3 different housing versions: Smallversion (0.87 Liter)ODD bay version (1.23 Liter)Internal Power supply/ PCIe Slot version (1.85 Liter) The listed product components and optional functions are not available in all region/countries; Energy Star certification only with Windows operating system;Base unit for TCO Certified generation 9; System is available in 3 different housing versions: Small version (0.87 Liter)ODD bay version (1.23 Liter)Internal Power supply/ PCIe Slot version (1.85 Liter)Base unitESPRIMO G9012 ESPRIMO G9012 ESTARxMainboardMainboard type D4014-A (base system)Formfactor ProprietaryChipset Intel® Q670Processor socket LGA1700Processor Qty (max.) 1Supported RAM (max.) 64 GBMemory slots 2 DIMM (DDR4)Memory frequency 3,200 MT/sMemory notes Dual channel supportFor dual channel performance, 2 memory modules have to be ordered. Capacity per channel has to be thesame. 3200 MHz may be clocked down to 2933/2400MHz depending on processor and memory configuration LAN 10/100/1,000 MBit/s Intel® I219LMIntegrated WLAN Optional; The device does not operate in 6GHz band in all countries, due to national regulations.BIOS version AMI Aptio VUEFI Specification 2.6BIOS features BIOS Flash EPROM update by softwareRecovery BIOSUnified Extensible Firmware Interface (UEFI)Audio type On boardAudio codec Realtek ALC257NAudio features Internal speaker supports audio playback, High Definition audioI/O controller on boardSerial ATA total 2Controller functions Serial ATA III (6 Gbit)NCQAHCIRAID 1/0InterfacesFront audio: headset 1USB front 1x USB 3.2 Gen1 (5 Gbps) Type-A1x USB 3.2 Gen2 (10 Gbps) Type-A1x USB 3.2 Gen2x2 (20 Gbps) Type-C (provides up to 15W)USB rear Base system:1x USB 2.0 Type-A (plus 2 ports optional*)3x USB 3.2 Gen2 (10 Gbps) Type-A1x USB 3.2 Gen2 (10 Gbps) Type-C (supports DisplayPort 1.4 and power delivery sink**)ESPRIMO G9012 ESPRIMO G9012 ESTARxDisplayPort 1x (DisplayPort 1.4, DP++) (2nd port optional*, DP)Serial (RS-232) 1 (optional*)HDMI 1x HDMI 2.1(2nd port optional*)Ethernet (RJ-45) 1x RJ-45Interface Module notes Only one of the interfaces marked as “optional” can be configured at the same time.**With power delivery sink support, the system is operated by the power from peripherals, e.g. portreplicators or displays. An extra power supply for the system is not needed. Peripherals must provide min.90Watt (for maximum CPU performance).Input deviceInput devices (optional) KeyboardMouseDrive baysDrive bays total 22.5-inch internal bays 15.25-inch external bays 1Drive bay notes 5.25” bay: for slim optical disc drive only as option with ODD bay housing version;M.2-2280 1 x on mainboard (PCIe 4.0 x4; up to 64Gbit/s)Slots1 x (168 mm / 6.61 inch)PCI-Express 3.0 x4(mech. x16)M.2-2230 On mainboard for WLAN moduleGraphics on boardGraphics brand name Intel® UHD Graphics 770, Intel® UHD Graphics 730 *Depends on CPUShared video memory Up to half size of total system memoryGraphics features Support for up to four independent displaysDirectX® 12HDCP supportOpenCL™ 2.1OpenGL® 4.6Vulkan™DisplayPort interface supports Ver. 1.4 incl. Multi-StreamHDMI™ 2.1Digital audio formats are supported, including Dolby Digital Plus (7.1 channels)Electrical valuesPower efficiency note 90 Watt AC adapter: power supply efficiency at 115/230V: 89% average efficiencyRated voltage range 100 V - 240 VRated frequency range 50 Hz - 60 Hz90 V - 264 VOperatingvoltage rangeESPRIMO G9012 ESPRIMO G9012 ESTARx Operating linefrequency range47 Hz - 63 HzMax. output of single power supply AC Adapter: 90 Winternal PLATINUM power supply (optional): 150 WNoise emissionStandard noiseemissionAccording to ISO 7779:2010, ECMA-74Standard noise notes / description A-weighted sound power level Lwad (in B) / Workplace related A-weighted sound pressure level LpAm (in dB(A))Dimensions / Weight / EnvironmentalDimensions (W x D x H) 146.5 x 164.5 x 36 mm (5.77 x 6.48 x 1.42 inch)Dimension notes With ODD drive bay, the dimensions are: 146.5 x 164.5 x 51 mm (5.77 x 6.48 x 2.01 inch) With internal power supply / PCIe slot version, the dimensions are:146.5 x 176.9 x 71 mm (5.77 x 6.97 x 2.80 inch)Operating position Vertical / Horizontal (feet included)Weight Base: Min:0.86kg; 1x mem,1xSDD / Max:1.025kg; 2x mem,2xSSD,HDD,Flexi,WLANODD version: Min:1.2kg/Max:1.29kgInt. PSU version: Min:1.45kg/Max:1.59kg*Weight of AC adapter and power cord are not includedWeight notes Actual weight may vary depending on configurationOperating ambienttemperature10 - 35 °C (50 - 95 °F)Operating relativehumidity5 - 85 % (relative humidity)ComplianceModel MPCGCertification CERoHS (Restriction of hazardous substances)CCC (In progress)BSMI (In progress) ENERGY STAR®RoHS (Restriction of hazardous substances) CCC (In progress)BSMI (In progress)Compliance link https:///sites/certificates Additional SoftwareAdditional software (preinstalled) McAfee® LiveSafe™ (provides award-winning antivirus protection for your PC and much more. 30 days trial pre-installed)Microsoft Office (1 month trial for new Microsoft® Office 365 customers. Buy Microsoft Office.)ESPRIMO G9012 ESPRIMO G9012 ESTARxAdditional software (optional) Recovery DVD for Windows®Drivers & Utilities DVD (DUDVD)Nero Essentials XLMicrosoft® Office Professional 2021Microsoft® Office Home and Business 2021(Need to buy license to activate the pre-installed Microsoft Office. Purchase and activation only in the region in which it was acquired.)Additional software (notes) Use of accompanying and/or additional Software is subject to proactive acceptance of the respective License Agreements /EULAs/ Subscription and support terms of the Software manufacturer as applicable for the relevant Software whether preinstalled or optional. The software may only be available bundled with a software support subscription which – depending on the Software - may be subject to separate remuneration.SecurityPhysical Security Kensington Lock supportEye for padlockSystem and BIOS Security Embedded security (TPM 2.0)EraseDiskCredential Guard Ready and Device Guard Capable (requires 8 GB or more system RAM and SSD PCIe NVME) Modern Standby and Legacy Standby selectableWrite protect option for the Flash EPROMControl of all USB interfacesExternal USB ports can be disabled separatelyControl of external interfacesNIST SP800-193 Platform Firmware Resiliency supportedNIST SP800-155 BIOS Integrity Measurement supportedNIST SP800-147 BIOS Protection supportedUser Security User and supervisor BIOS passwordHard disk passwordAccess protection via SmartCard reader (optional)AuthConductor Client Basic (secure authentication solution)Security Notes The properties of the product provide a baseline for product security and therefore end-customer IT security.However, these properties are not sufficient on their own to protect the product from all existing threats,such as intrusion attempts, data exfiltration and other forms of cyberattacks. To customize security settings,please use the configuration options as available for the respective product. During operation, the IT securityof this product is within the responsibility of the respective administrator/end-user of the product. Pleasenote, that Fujitsu as a manufacturer does not make any policy prescriptions or advocacy statements regardingIT security best practices and/or general product operation.ManageabilityManageability technology DeskUpdate Driver management PXE 2.1 Boot codeWake up from S5 (off mode) Intrusion switchWoL (Wake on LAN)Intel AMT 16.0 (depending on processor)Manageability software DeskView ClientDeskView Instant BIOS ManagementDeskView components BIOS Management incl. SecurityInventory ManagementESPRIMO G9012 ESPRIMO G9012 ESTARxDriver ManagementAlarm ManagementSupported standards DMI (Desktop Management Interface)SMBIOS (System Management BIOS)PXE (Preboot Execution Environment)WMI (Windows Management Instrumentation)WBEM (Web Based Enterprise Management)CIM (Common Information Model)Manageability link /fts/manageabilityPackaging informationPackaging dimension (mm) 489 x 218 x 165mmMax. quantity / pallet48Packaging material weight 702gWarrantyhttps:///hk/ap/warrantyWarranty Terms &ConditionsFujitsu recommends Windows 11 ProMore informationThe word “Uvance” embodies a concept of “Making all (Universal) things move forward(Advance) in a sustainable direction.Fujitsu Uvance will leverage Fujitsu’s technological capabilities and problem-solvingexpertise across seven key focus areas, including Sustainable Manufacturing, ConsumerExperience, Healthy Living, Trusted Society, Digital Shifts, Business Applications, and HybridIT, to offer unprecedented value to customers, while contributing to the achievement of itsultimate purpose —"to make theworld more sustainable by building trust in society through innovation."Through Fujitsu Uvance, we are committed to transforming the world into a place where people can live their lives, enjoying prosperity and peace of mind. Empowering each other to make the world more sustainable.For more information of Fujitsu Uvance, please visit https:///global/uvanceTo grow in an uncertain world, it is imperative to stay resilient and agile to respond complex and unforeseen challenges.Under the global business brand – Uvance, Fujitsu provides a full range of reliable and best-in-class product, service, and solution offerings with digital innovation, from sustainable manufacturing to smart city ecosystem, to create a more sustainable world and resolve social issues. This empowers customers to strengthen resilience through Fujitsu’s trusted solutions using cutting-edge technologies, while increasing their business agility and improving the reliability of their IT operations.For more information, please visit https:///globalContact UsHONG KONG SINGAPORE CHINAFujitsu Business Technologies Asia Pacific Ltd. Fujitsu Asia Pte Ltd. Fujitsu (China) Holdings Co., Ltd. – Tel: (852) 3910-8228 Tel: (65) 6512-7555 PC China DivisionEmail:***********************.com Email:*********************Tel: 86 (21) 58871000-8721/pc /pc Email:*************************.com/pcINDONESIA PHILIPPINES MALAYSIAPT Fujitsu Indonesia Fujitsu Philippines, Inc. Fujitsu (Malaysia) Sdn. BhdTel: (62) 21-570-9330 Tel: (63) 2-8841-8488 Tel: (60) 3-8230-4188Email:********************.com Email:********************************Email:************************* /pc /pc /pcTAIWAN THAILAND VIETNAMFujitsu Taiwan Ltd. Fujitsu (Thailand) Co., Ltd. Fujitsu Vietnam LimitedTel: (886) 2-2311-2255 Tel: (66) 0-2302-1500 Tel: (84-24) 2220-3113Email:************************Email:*******************Email:********************/pc /pc /pcNote: For countries not listed above, please contact Hong Kong office.Specification disclaimersNot all features are available in all editions or versions of Windows. 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FLIR SC6000 SeriesMWIR science grade cameraHIGH SENSITIVITY, HD THERMAL IMAGESFLIR SC6000 Series incorporate a cooled Indium Antimonide (InSb) detector that operates in the 3 to 5 or 1 to 5 micron waveband. It produces crisp thermal images of 640 x 512.Four active preset operating modes provide adjustable integration times,embedded non-uniformity correction, and bad pixel replacement. An exclusive SC6700 4-position motorized filter wheel permits effortless filter exchange in any environment.FAST FRAME RATES AND TRIGGERINGFLIR SC6000 Series features fast frame rates with a high speed 50 megapixel clock that streams 14-bit digital data up to 126 Hz at full resolution. They support FPA windowing for even higher frame rates. Output frame rates are adjustable from 0.0015 Hz to the maximum frame rate at a given window size and integration time with 0.1 Hz resolution.Advanced triggering options through external BNC input, IRIG time, or asoftware trigger; clock out single images, multiple images, or multiple images from multiple presets. IRIG-B timing is built directly into camera for on-board deterministic time-stamping of each frame and advanced triggering options.INTERFACE FLEXIBILITYMultiple simultaneous analog and digital outputs include S-video, composite (BNC) NTSC and PAL, SVGA, and industry-standard digital Camera Link and Gigabit Ethernet.SOFTWAREThe FLIR SC6000 Series cameras work seamlessly together with FLIRResearchIR Max software enabling intuitive viewing, recording and advanced processing of the thermal data provided by the camera. Each camera comes standard with this especially for R&D applications developed software. A Software Developers Kit (SDK) is optionally available.MATHWORKS® MATLABControl the SC6000 Series and capture data directly into MathWorks ® Matlab software for advanced image analysis and processing.KEY FEATURES• High image quality: 640 x 512 pixels • High speed• Configuration flexibility • Filter wheel• On-camera Radiance and Thermographic Calibration737 across the sunStop-motion image of spinning tireImaging SpecificationsSpecifications are subject to change without notice©Copyright 2014, FLIR Systems, Inc. All other brand and product names are trademarks of their respective owners. The images displayed may not be representative of the actual resolution of the camera shown. Images for illustrative purposes only. (Created 08/14) NASDAQ: FLIRPORTLANDCorporate Headquarters FLIR Systems, Inc.27700 SW Parkway Ave.Wilsonville, OR 97070USAPH: +1 866.477.3687BELGIUMFLIR Systems Trading Belgium BVBALuxemburgstraat 22321 Meer BelgiumPH: +32 (0) 3665 5100SWEDENFLIR Systems AB Antennvägen 6, PO Box 7376SE-187 66 Täby SwedenPH: +46 (0)8 753 25 00NASHUAFLIR Systems, Inc.9 Townsend West Nashua, NH 06063USAPH: +1 603.324.7611UKFLIR Systems UK 2 Kings Hill Avenue Kings HillWest Malling - Kent ME19 4AQUnited KingdomPH: +44 (0)1732 220 011。

MISSION-CRITICAL CONVERGED TETRA AND LTE PORTABLE DEVICEThe MXP7000 provides versatile communications. It delivers mission-critical TETRA and 4G LTE broadband voice and data communications, in a secure and rugged Android device.It’s easy to use and operate the MXP7000. The large push-to-talk button lets users connect instantly, and the field-swappable battery helps them stay connected longer. Innovative audio technology enables your personnel to hear and be heard clearly, even in noisy and windy conditions. It has a 5-inch touchscreen and the device can run applications for optimal workforce productivity.The MXP7000 is easy to deploy and manage, and it supports Bluetooth® 5.1 for data transfer. It has a GCAI-mini connector, so you can provide your teams with accessories tailored to their needs.No matter their mission, the MXP7000is a device that helps your teams getthe job done.MXP7000TETRA AND LTE PORTABLE DEVICE YOUR APPS. YOUR COMMS. YOUR TEAM. TOGETHERGENERAL SPECIFICATIONSDimensions Height: 210mm (with antenna) Height: 150mm (without antenna) Width: 80mmDepth: 29.85mm (with battery)Weight440g (with battery and antenna) Battery Options5600mAh IMPRES™ 2Housing Colour BlackGreen (selected models)Display 5.0”, 1280 x 720 Capacitive, touch-screen with Corning® Gorilla® glassSupports use with disposable and combat glovesControls Large Push-to-talk button Emergency buttonDual function rotary knob 2 configurable side buttonsMemory 4GB RAM64GB Internal Storage Supports microSDSIM Slots TETRA SIM: 2FF (Mini SIM) LTE: 4FF (Nano SIM)Camera Rear 13MP, with integrated flash Front 8MPVideo Recording Quality1080p at 60 fpsSensors Proximity Ambient Light Accelerometer Barometer GyroscopeE-CompassPorts GCAI-mini USB-CDEVICE SECURIITYUser Authentication PIN or passwordKey Storage Hardware-backed encryption with Trusted Execution Environment (TEE)Trusted Boot Process Included with the use of tamper resistant hardware OS Hardening Android OS hardening and SELinux access controlAuditing Auditing / logging functionality, with security logs captured and stored in a secured mannerData-at-Rest Using Android’s AES256 File Based Encryption Data-in-Transit Encryption with IPSec VPN supportSecured Device Management With the use of Integrated Terminal Management (iTM) solutionRestricted Recovery Mode Included to avoid unauthorised access to features AUDIOAudio Power at Rated2WAudio Distortion at Rated<1%Audio Power at Maximum3WMax loudness99PhonNoise supression Adaptive Multi-Microphone Beam-Forming Number of Microphones3 dedicated + 1 loudspeaker as microphone TETRA SERVICEAuthentication Infrastructure initiated and made mutual by radio terminal Air Interface Encryption- AlgorithmsTEA 1, TEA 2, TEA 3Protocols - Security ClassesClass 1 (Clear)Class 2 (SCK)Class 3 (DCK/CCK, OTAR-CCK, OTAR-SCK)Class 3G (GCK, OTAR-GCK)End-to-End Encryption SIM based encryption including BSIOther Security FeaturesTemporary disable (stun)Permanent disable (either ETSI standard orcustomer restorable)CONNECTIVITYBluetooth Versions Supported Bluetooth 5.1 (data transfer only)Bluetooth Profiles Generic Attribute (GATT)Attribute Protocol (ATT)Generic Access Profile (GAP)Serial Port Profile (SPP)Personal Area Networking Profile (PAN) Object Push Profile (OPP)Headset Profile (HSP)LOCATION SERVICESConstellation Supported GPS, aGPS, Galileo, GLONASS, BDS (BeiDou) GNSS Antenna Internal antennaGNSS Tracking Sensitivity GPS:-158dBm (50% Fix losses) -162dBm (typical)Horizontal Accuracy, 2D <5m (95% probable, -130dBm) TTFF Cold Start<60 sec (95% probable at -130dBm) ProtocolsETSI LIP (short and long), Motorola Solutions LRRP KEY FEATURES & SETTINGSTalkgroup Management User friendly, flexible, fast and efficient interface TalkgroupsTMO folders: up to 256, TMO talkgroups: up to 10000DMO folders: up to 128, DMO talkgroups: up to 2000 Favourite Talkgroup Folders Up to 3Contacts Management Rapid search to find the contact easilyContacts Up to 1000 contactsMultiple Dialling Methods Dialling direct, scroll and select via touchscreenCall Alert Vibrate alert and set ringtones via Android SettingsFall Alert (Man-down)Triggers an emergency alert if the device is continuouslytilted beyond a pre-defined angleMessage ManagementDistinct folders for each message type forflexible message managementText Message ListUp to 200 entries (short messages)At least 20 entries for outbox(long messages up to 1000 characters)At least 10 entries for inbox(long messages up to 1000 characters)Status ListUp to 100 user-defined messagesAssignable to One Touch ButtonsText Entry Touchscreen for ease of useTransmit Inhibit Disables TETRA transmit and puts device into Airplane Mode 1 TETRA communications is still availableDEVICE MANAGEMENT SOLUTIONSIntegrated Terminal Management (iTM)Supports iTM version 8.0 onwardsENVIRONMENTAL SPECIFICATIONSOperating Temperature 2-20°C to + 60°C Storage Temperature -40°C to +85°CHumidity (High) , Low and High Temperature ETSI 300 019-1-7 class 7.3E Shock (bumps & shock), vibration (random)ETSI 300-019 1-7 class 5M3Dust and Water Ingress ProtectionBlack model: IP68 per IEC 60529Green model: IP67 per IEC 60529 Compliance to US Military Standard 810See table to the right2Performance may be limited when operating at extreme temperatures.US MILITARY STANDARD MATRIXMethodProc/CatLow Pressure 500.6II High Temperature 501.7I/A1,II Low Temperature 502.7I,II Thermal Shock 503.7I-C Solar Radiation 505.7I/A1Humidity 507.6II / AggravatedSalt Fog509.7-Blowing Sand 510.7II Vibration 514.8I/Cat 24,II/Cat 5Shock 3516.8I,IV,VI3Drop test is covered as part of Shock Method 516.8 Proc IV, VIMotorola Solutions UK Limited, Nova South, 160 Victoria Street, London, SW1E 5LB.All specifications are subject to change without notice.MOTOROLA, MOTO, MOTOROLA SOLUTIONS and the Stylised M Logo are trademarks or registered trademarks of Motorola Trademark Holdings, LLC and are used under licence. The Bluetooth ® word mark and logos are registered trademarks owned by Bluetooth SIG, Inc. and any use of such marks by Motorola Solutions, Inc. is under licence. All other trademarks are the property of their respective owners. © 2023 Motorola Solutions, Inc. All rights reserved. (09-23)For more information, please visit us at /mxp7000。

IT8687RI/O Buffer Chip Preliminary Specification V0.6Revision HistoryNote: Words in bold lettering in the revisions below indicate the changes.Document Release Date Revision Page No.5 Release Version 0.63/6/98On page 5, change the parameter name of O18 TypeBuffer on Table 6-1. DC Electrical Characteristics toO12 Type Buffer.On page 5, change the Min. of V IH of ISH Type Buffer5from 1.0 to 3.0.On page 5, change the Max. of V IL of IS Type Buffer5from 0.6 to 0.7.5On page 5, change the Max. of V IL of ISH Type Bufferfrom -1 to 0.9.5On page 5, change the Conditions of V OL under O12Type Buffer from I OL=18mA to “I OL=12mA.”5On page 5, change the Conditions of V OH under O12Type Buffer from I OH=-6mA to “I OH=-4mA.”ContentsPage1. Features (1)2. General Description (1)3.Pin Configuration (1)4. Block Diagram (2)5. IT8687R Pin Description (3)6.DC Electrical Characteristics (5)7.AC Characteristics (6)8.Package Information (8)9.Ordering Information (9)TablesPage 5-1.IT8687R Signal Names (by pin numbers in alphabetical order) (2)6-1.DC Electrical Characteristics (5)7-1.AC Characteristics (6)IT8687R Preliminary V0.6I/O Buffer Chip Specifications subject to Change without Notice ITPA-PN-98012 Joseph. Mar. 061. Featuresn Contains six (6) line drivers (1488)and ten (10) line receivers(1489)n Supports two (2) RS-232 serial portsn Very low power consumption (150mW)n Four power supply inputs:0V,5V,-12V,+12V n High voltage CMOS processn 48-pin SSOP packagen Supports one (1) crystal oscillator clock generator 2. General DescriptionIT8687R integrates six (6) line drivers, ten (10) line receivers, one ISA signal encoder, one (1) UART signal-mixing control logic, and one 24/48 MHz clock generator. The ISA signals; (1) SA12, SA13, SA14, SA15, DACK0#, DACK1#, DACK2#, DACK3#, AEN, RESET are encoded into three (3) signals -- RAD0, RAD1, RAD2. 16 UART interface signals are encoded into UIF0, UIF1, UIF2, UIF3, UIF4 to minimize the pin count and the package cost. This low power consumption chip is designed to serve as an interface between data terminal equipment and data communication equipment in conformance with the EIA standard RS-232 specifications.3. Pin ConfigurationUIF4/LTX1UIF3/LRTS1UIF2/LRLSD1UIF1/LRX1UIF0/LDTR1GNDCLKOUTX2X1RAD2/LDSR1RAD1/LCTS1RAD0/LRI1VCC DACK3#/LRLSD2 DACK2#/LRX2DACK1# DACK0#/LTX2AEN/LDSR2GNDSA15/LCTS2SA14/LRI2SA13/LRTS2SA12/LDTR2RESET MODE VDD TX1 RTS1 DTR1 VSS NC RLSD1 RX1 DSR1 CTS1 RI1 RLSD2 RX2 DSR2 CTS2 RI2NC VSS TX2 RTS2 DTR2 VDD NC4. Block DiagramNRTS1,NDTR1,NTX1NRTS2,NDTR2,DTR1#RTS1#TX1,DTR2#RTS2#TX2,NRX1,NCTS1NDSR1,NRLSD1NRI1,RX1,CTS1#DSR1#,RLSD1#RI1#NRX2,NCTS2NDSR2,NRLSD2NRI2RX2,CTS2#DSR2#,RLSD2#RI2#UIF0,UIF1UIF2,UIF3UIF4AENRESET,DACK1#DACK0#,DACK3#DACK2#,SA12,SA13SA14,SA15RAD0,RAD1RAD2NTX2MODECLKOUTX1X25. IT8687R Pin DescriptionTable 5-1. Signal Names (by pin numbers in alphabetical order)Pin No.Symbol I/O Description1UIF4/LTX1IS Serial ports 1,2 signals sample clock input. The second function is SerialPort 1 TX line driver input.2UIF3/LRTS1IS Serial ports 1,2 transfer cycle indicator. The second function is Serial Port 1RTS line driver input.3UIF2/LRLSD1O18Serial port 2 signals RLSD2, RX2, DSR2, CTS2, RI2 mixing-signal outputpin. The second function is Serial Port 1 RLSD line receiver output.4UIF1/LRX1O18Serial port 1 signals RLSD1, RX1, DSR1, CTS1, RI1 mixing-signal outputpin. The second function is Serial Port 1 RX line receiver output.5UIF0/LDTR1IS Serial ports 1,2 signals TX1, TX2, RTS1, RTS2, DTR1, DTR2 mixing-signalinput pin. The second function is Serial Port 1 DTR line driver input.7CLKOUT O8Output clock generated by the crystal oscillator8X2O Crystal oscillator output9X1I Crystal oscillator input10RAD2/LDSR1O18ISA signal encoding output pin 2. The second function is Serial Port 1 DSRline receiver output.11RAD1/LCTS1O18ISA signal encoding output pin 1. The second function is Serial Port 1 CTSline receiver output.12RAD0/LRI1O18ISA signal encoding output pin 0. The second function is Serial Port 1 RIline receiver output.14DACK3#/ LRLSD2I/O18ISA DMA Acknowledge 3, active low. The second function is Serial Port 2RLSD line receiver output.15DACK2#/ LRX2I/O18ISA DMA Acknowledge 2, active low. The second function is Serial Port 2RX line receiver output.16DACK1#IS ISA DMA Acknowledge 1, active low17DACK0#/ LTX2IS ISA DMA Acknowledge 0, active low. The second function is Serial Port 2TX line driver input.18AEN/LDSR2I/O18Address Enable, active high indicates system is in DMA transfer mode. Thesecond function is Serial Port 2 DSR line receiver output.20SA15/LCTS2I/O18ISA I/O Address 15. The second function is Serial Port 2 CTS line receiveroutput.21SA14/LRI2I/O18ISA I/O Address 14. The second function is Serial Port 2 RI line receiveroutput.Table 5-1. Signal Names (by pin numbers in alphabetical order) [cont’d]Pin No.Symbol I/O DescriptionISA I/O Address 13. The second function is Serial Port 2 RTS line driver 22SA13/LRTS2ISinput.ISA I/O Address 12. The second function is Serial Port 2 DTR line driver 23SA12/LDTR2ISinput.24RESET IS System reset, active high27DTR2O16H Serial port 2 DTR line driver output28RTS2O16H Serial port 2 RTS line driver output29TX2O16H Serial port 2 TX line driver output32RI2ISH Serial port 2 RI line receiver input33CTS2ISH Serial port 2 CTS line receiver input34DSR2ISH Serial port 2 DSR line receiver input35RX2ISH Serial port 2 RX line receiver input36RLSD2ISH Serial port 2 RLSD line receiver input37RI1ISH Serial port 1 RI line receiver input38CTS1ISH Serial port 1 CTS line receiver input39DSR1ISH Serial port 1 DSR line receiver input40RX1ISH Serial port 1 RX line receiver input41RLSD1ISH Serial port 1 RLSD line receiver input44DTR1O16H Serial port 1 DTR line driver output45RTS1O16H Serial port 1 RTS line driver output46TX1O16H Serial port 1 TX line driver outputPrimary function is selected when this pin is low; secondary function is 48MODE ISselected when it is high.25,31NC No Connection426,19GND Ground13VCC+5V power30,43VSS-12V power26,47VDD+12V power6. DC Electrical CharacteristicsAbsolute Maximum RatingsAmbient Operating Temperature………..…..0°C to +70°C Storage Temperature….…….……………-55°C to +150°C Supply Voltage to Ground Potential….-0.5V to VCC+0.3V Supply Hi-Voltage to Ground Potential……±0.5V to ±12V Applied Normal Output Voltage………0.5V to VCC+0.3V Applied Normal Input Voltage.…………………-0.5V to 7V Applied I/O High Voltage…………………….-0.5V to +15V Power Dissipation……….…………………………..300mW *CommentsStresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.Table 6-1. DC Electrical CharacteristicsSymbol Parameter Min.Typ.Max.Unit Conditions IS Type Buffer (VCC=5V)I IL Input Low Leakage10µA V IN = 0I IH Input High Leakage-10µA V IN = VCCV IL Input Low Voltage0.7VV IH Input High Voltage 3.0VI Type Buffer (VCC=5V)I IL Input Low Leakage10µA V IN = 0I IH Input High Leakage-10µA V IN = VCC O8 Type Buffer (VCC=5V)V OL Output Low Voltage0.4V I OL = 8mA V OH Output High Voltage 2.4V I OH = -4mA O12 Type Buffer (VCC=5V)V OL Output Low Voltage0.4V I OL = 12 mA V OH Output High Voltage 2.4V I OH = -4 mA ISH Type Buffer (VDD=+12V, VSS=-12V)I IL Input Low Leakage10µA V IN = -12 VI IH Input High Leakage-10µA V IN = +12 VV IL Input Low Voltage0.9VV IH Input High Voltage 3.0VO16H Type Buffer (VDD=+12V, VSS=-12V)V OL Output Low Voltage-8V I OL = 8 mA V OH Output High Voltage8V I OH = -4 mA7. AC CharacteristicsTable 7-1. AC CharacteristicsSymbolParameterMin.Typ.Max.Unitt1X1 ↑ to X2 ↓2030ns t2X1 ↓ to X2 ↑2540ns t3RESET/DACK0-3#/AEN/SA15-12change state to RAD0-2 ↑5070ns t4RESET/DACK0-3#/AEN/SA15-12change state to RAD0-2 ↓4060ns t5UIF4 ↓ to DTR1/2, RTS1/2, TX1/2 ↑100120ns t6UIF4 ↓ to DTR1/2, RTS1/2, TX1/2 ↓95110ns t7UIF4 ↑ to UIF1,UIF2 ↑6080ns t8UIF4 ↑ to UIF1,UIF2 ↓5080nsX1X2RESET AEN SA15~12RAD0-2UIF1SSOP 48L Outline Dimensionsunit: inches/mmDetail F25e 1A 1A 2ASymbol Dimension in inchesDimension in mmA 0.110 Max. 2.79 Max.A 10.004 Min.0.10 Min.A 2 0.090 ± 0.005 2.29 ± 0.12b 0.010+0.0030.25+0.08−0.002−0.05C 0.008+0.0020.20+0.05−0.002−0.05D 0.625 Typ. (0.637 Max.)15 Typ. (16.18 Max.)E 0.295 ± 0.0057.49 ± 0.13e 0.025 ± 0.0060.64 ± 0.15e 10.370 NOM. 9.40 NOM.H E 0.408 ± 0.01210.36 ± 0.31L 0.030 ± 0.0100.76 ± 0.26L E 0.057 ± 0.008 1.45 ± 0.20S 0.035 Max.0.89 Max.y 0.004 Max.0.10 Max.θ0° ~ 10°0° ~ 10°Notes:1.The maximum value of dimension D includes end flash.2.Dimension E does not include resin fins.3.Dimension e 1 is for PC Board surface mount pad pitch design reference only.4.Dimension S includes end flash.Part No.Package IT8687R SSOP 48L。

Table of Contents1. General Description (3)2. Applications (3)3. Features (3)4. Standards Supported (3)5. IC Block Diagram (4)6. Pinout (5)7. Pin Descriptions (6)7.17.27.3 7.4 7.5 7.6 7.7 7.87.98. 11 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.88.99. 16 9.1 9.2 9.39.4 Normal / Test Mode (19)10. Packaging (20)11. Ordering Information (21)12. Reference Design (21)13. Revision History (22)M AX L INEARM X L251I NTEGRATED C ABLE R ECEIVER1. General DescriptionThe MxL251 is an ultra-low-power single-chip receiver IC compliant with all global digital-cable standards including ITU-T J.83 Annex A [DVB-C], Annex B [US Cable], Annex C,costs.operates using 3.3V, 1.8V and 1.2V supplies. It is available in a small 7 x 7 mm 2 footprint 48-pin QFN package.2. ApplicationsMxL251 enables high-performance receivers for digital-cable applications including: ∙ STBs∙ Cable DTAs ∙ Cable Gateways3. Features∙Dual integrated tuner / demodulators can be independently tuned over the entire 44 to 1002 MHz cable spectrum∙ Supports OOB signals from 70 to 130 MHz ∙ SCTE55-1 ∙ SCTE55-2∙ OC-SP-CCIF2.0 (OpenCable CableCARDInterface 2.0)5.IC Block DiagramThe MxL251 Integrated Cable Receiver, illustrated in Figure 1, accepts a single differential RF input. The signal first passes through a high-gain LNA to minimize noise figure and is then routed to dual narrowband tuners, each of which can be independently tuned from 44 to 1002 MHz to capture a 6 or 8 MHz channel. The captured channels are then routed to QAM demodulators where they are demodulated into serial MPEG Transport Streams. If a tuner is tuned to an out-of-band (OOB) channel, the resulting output is not a Transport Stream but rather an OpenCable CCIF 2.0 compliant serial bitstream (DRX) and clock (CRX).Automatic Gain Control ensures that optimal power levels are maintained throughout the signal-Figure 1: MxL251 Integrated Cable Receiver6. PinoutN C N CV D D _1p 8_A 8N CN CV D D _1p 8_A 7N CN CS D AS C LG N DV D D _1p 2_D 37.Pin Descriptions7.1Table 2: RF interface7.2MPEG T RANSPORT S TREAMThe MxL251 supports two serial MPEG Transport Stream interfaces: a 3-wire interface and a 4-wire interface. Both interfaces have the following features:∙Maximum MPEG clock frequency is 64 MHz∙MPEG DATA output can be programmed as either MSB first or LSB first∙Data may be clocked by either the rising or falling edge of the clock∙The polarity of the MPEG VALID and MPEG SYNC signals can be invertedFigure 3: MPEG 4-Wire Interface7.2.23-W IRE I NTERFACEIn the 3-Wire Transport Stream Interface, only three signals are used to convey information: Data, Sync, and Valid. MPEG Data is a serial bitstream clocked by MPEG CLK and organized as 188-byte packets. MPEG SYNC is asserted concurrent with the 1st byte (ie. the sync byte) of each packet as in the 4-wire mode. This time, however, the MPEG CLK and MPEG VALID signals of the 4-wire mode are logically ANDed to form a gated clock which is presented on MPEG VALID. Thus, VALID toggles for the entire 188-byte packet but is silent between packets. Timing waveforms for the 3-wire interface are shown in Figure 4.on page 15. SCL and SDA are open-drain pins and should be pulled-up to VDD_IO using a 4.7k ohm resistor.Pin Name Direction DescriptionI2C Address SelectAS InputSCL Bi-directional I2C Clock (open-drain)SDA Bi-directional I2C Data (open-drain)Table 5: I2C Interface7.5I NTERRUPTThe MxL251 has one interrupt pin which can be used to alert the Host Processor of six events: FEC Lock/Unlock, QAM Lock/Unlock, and MPEG Lock/Unlock.Pin Name Direction Description(open-drain)INTERRUPT Output InterruptTable 6: Interrupt Pin7.6S UPPLY AND G ROUNDThe MxL251 requires three supply voltages to operate: 3.3V, 1.8V, and 1.2V.Table 8: Reset Pin7.8C RYSTAL /C LOCKMxL251 designs may be clocked using either an external crystal or an external clock. A reference clock output is available to facilitate cascading of devices to increase the number of available Transport Streams. When cascading, the clock output of one chip should be connected to the XTAL_P input of the next chip.Pin Name Direction Type DescriptionplusXTAL_P Input AnalogXTALXTALminusXTAL_N Input Analogclock output for use in cascaded designs CLOCK_OUT Output Analog ReferenceTable 9: Crystal / Clock Pins7.9N O C ONNECTPins marked ‘NC’ should be left unconnected.Pin Name Direction Type DescriptionNC No connect Do not connect8.Electrical Specifications8.1A BSOLUTE M AXIMUM R ATINGSStresses beyond those listed in Table 11 may cause permanent damage to the device. This is a stress rating only and functional operation of the device above these, or any other conditions beyond those “recommended” is not implied. Exposure to conditions above those “recommended” for extended periods of time may affect device reliability.Table 12: Required Operating Conditions1 Shall be connected to 3.3V for all new designs. Current designs using 1.8V can continue to use 1.8V if LT, SPLT are not used; however, in no circumstances shall this pin be left disconnected.8.3C URRENT AND P OWER C ONSUMPTIONTable 13 shows worst-case power consumption for the operational modes described in Table 14. Note that VDD_IO is treated as a 3.3V supply for these calculations. All numbers are adjusted for temperature and process variations.Table 14: Operational ModesApplications using the Loop-Through (LT) or Splitter outputs in any mode of operation will see increased power consumption as detailed in Table 15. Therefore, to ascertain total current/powerconsumption, designers should add the numbers in Table 15 to those in Table 13 as needed to reflect their specific design.Tamb = 25ºC, VDD_LT_SPLT = 3.3V unless otherwise specifiedMode of Operation Supply Pin1Additional Current (mA) Additional Power (mW) Min Typ Max Min Typ MaxLTOn VDD_3p3_An 66 218 SplitterOn VDD_3p3_An 66 218 Both LT and Splitter On VDD_3p3_An 132 436 Table 15: Incremental Current and Power Consumption (LT and/or Splitter ON)1 VDD_3p3_An represents the 3 pins VDD_LT_SPLT, VDD_3p3_A1, and VDD_3p3_A2. Numbers in the table reflect the total combined current/power for all power pins in the set.Table 16: Receiver Specifications1 Measured using TDK Balun ATB 2012-75011.2 Assumes factory calibration.3 Clock output swing is specified with 10pF load capacitance. Specific program information is described in the MxL251 Reference Design Guide.4 Loop-Through (LT) is used for analog pass through applications. All parameters include input and output balun.5 Details on determining Thermal Resistance (Junction to Ambient) are described in the MxL251 Reference Design Guide.8.5M O CA R EJECTIONWhen MoCA is present either inside or outside the box, external filtering is required for the MxL251 toTable 18: Digital IO Operating Conditions1 For VDD_IO = 1.8V, IO Drive Strength must be increased from default to meet V OH, V OL specification at 3mA source/sink current.8.7I2C A DDRESS S ELECTIONThe Address Select Pin (AS) is a four-level input with typical values shown in Table 19. Depending on the voltage applied, the chip will respond to one of four possible I2C addresses. Typically, the voltage is derived from 1.8V using a simple resistive voltage divider network as described in the MxL251 Reference Design Guide.I2C Address Min Typical Max Units0x50 0 0 0.2 V0x51 0.4 0.6 0.8 V0x52 1.0 1.2 1.4 V0x53 1.6 1.6 1.8 VTable 19: I2C Address Selection1pF, refer to HW Design Guide for details on how to compute crystal drive level and verify it does not exceed that specified by the crystal datasheet.8.9ESD P ERFORMANCEAll pins pass ESD testing of 1000V using the Human Body Model (HBM) and 250V using the Charged Device Model (CDM).9.Timing Specifications9.1MPEG T RANSPORT S TREAMTiming diagrams for the MPEG TS signals are shown in Figure 5 and Figure 6. The corresponding specifications are shown in Error! Reference source not found..Figure 5: MPEG serial output timingFigure 6: MPEG output rise and fall timeTamb = 25ºC, VDD_IO = 3.3V unless otherwise specifiedParameter SymbolMPEG clock duty cycle00.9foTable 22: MPEG Transport Stream Timing1 Measurements with drive strength = 4x2 Capacitive load = 10pf9.2I2CI2C input and output timing diagrams are shown in in Figure 7 and Figure 8, respectively. Corresponding specifications are shown in Table 23.Tamb = 25ºC, VDD_IO = 3.3V unless otherwise specifiedMin Typical Max Units Parameter SymbolI2CSetup time (Figure 7) t s 62 ns Hold time (Figure 7) t h187 ns Propagation delay (Figure 8) t pd1 445 nsTable 23: I2C TimingFigure 7: I2C input timingFigure 8: I2C output timing9.3P OWER U P AND R ESETThe MxL251 requires three supply voltages to operate: 3.3V, 1.8V, and 1.2V. They can be powered up in any order as shown in Figure 9, and no power-up sequence rules need be followed; however, RESET_N should be asserted (held low) until all voltage supplies have been stable for at least 10 µs (T1≥10 µs).Tramp_Down > 10usFigure 10:VDD_3p3_An Supply Ramp-down TimingAll VDDs10us < Tramp <5msFigure 11: Voltage Supply Ramp-up Timing 9.4N ORMAL /T EST M ODEFigure 12: Normal / Test Mode Timing10. PackagingQFN48 package dimensions: 7x7x0.85 mm311. Ordering InformationMarketing Part Number OrderingPart NumberPackage Dimension ShippingMxL251 MXL251-AF-TSAWNQFN487 x 7 x 0.85mm3 Tray MxL251 MXL251-AF-R SAWN QFN48 7 x 7 x 0.85mm3Tape and ReelTable 24: Ordering Information12. Reference DesignTwo supplementary guides are available to customers incorporating this chip into their designs: (a) MxL251 Reference Design Guide, and (b) MxL251 MxLWare DRV API User Guide. Please contact13. Revision HistoryRev 1.0, October 27, 20101. First datasheet for Engineering Sample.Rev 2.1.RC6, July 5, 20111.First datasheet for 251 V2.。