NRWP332M10V18X40F中文资料

PRECHARGE OperationInput A10 determines whether one bank or all banks are to be precharged and, in thecase where only one bank is to be precharged, inputs BA[2:0] select the bank.When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After abank is precharged, it is in the idle state and must be activated prior to any READ orWRITE commands being issued.SELF REFRESH OperationThe SELF REFRESH operation is initiated like a REFRESH command except CKE is LOW.The DLL is automatically disabled upon entering SELF REFRESH and is automaticallyenabled and reset upon exiting SELF REFRESH.All power supply inputs (including V REFCA and V REFDQ) must be maintained at valid lev-els upon entry/exit and during self refresh mode operation. V REFDQ may float or notdrive V DDQ/2 while in self refresh mode under certain conditions:•V SS < V REFDQ < V DD is maintained.•V REFDQ is valid and stable prior to CKE going back HIGH.•The first WRITE operation may not occur earlier than 512 clocks after V REFDQ is valid.•All other self refresh mode exit timing requirements are met.The DRAM must be idle with all banks in the precharge state (t RP is satisfied and nobursts are in progress) before a self refresh entry command can be issued. ODT mustalso be turned off before self refresh entry by registering the ODT ball LOW prior to theself refresh entry command (see On-Die Termination (ODT) ( for timing requirements).If R TT,nom and R TT(WR) are disabled in the mode registers, ODT can be a “Don’t Care.”After the self refresh entry command is registered, CKE must be held LOW to keep theDRAM in self refresh mode.After the DRAM has entered self refresh mode, all external control signals, except CKEand RESET#, are “Don’t Care.” The DRAM initiates a minimum of one REFRESH com-mand internally within the t CKE period when it enters self refresh mode.The requirements for entering and exiting self refresh mode depend on the state of theclock during self refresh mode. First and foremost, the clock must be stable (meetingt CK specifications) when self refresh mode is entered. If the clock remains stable andthe frequency is not altered while in self refresh mode, then the DRAM is allowed to exitself refresh mode after t CKESR is satisfied (CKE is allowed to transition HIGH t CKESRlater than when CKE was registered LOW). Since the clock remains stable in self refreshmode (no frequency change), t CKSRE and t CKSRX are not required. However, if theclock is altered during self refresh mode (if it is turned-off or its frequency changes),then t CKSRE and t CKSRX must be satisfied. When entering self refresh mode, t CKSREmust be satisfied prior to altering the clock's frequency. Prior to exiting self refreshmode, t CKSRX must be satisfied prior to registering CKE HIGH.When CKE is HIGH during self refresh exit, NOP or DES must be issued for t XS time. t XSis required for the completion of any internal refresh already in progress and must besatisfied before a valid command not requiring a locked DLL can be issued to the de-vice. t XS is also the earliest time self refresh re-entry may occur. Before a command re-quiring a locked DLL can be applied, a ZQCL command must be issued, t ZQOPER tim-ing must be met, and t XSDLL must be satisfied. ODT must be off during t XSDLL.exit mode precharge power-down. A summary of the two power-down modes is listed inTable 82 (page 188).While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stableclock signal must be maintained. ODT must be in a valid state but all other input signalsare “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out ofpower-down mode and go into the reset state. After CKE is registered LOW, CKE mustremain LOW until t PD (MIN) has been satisfied. The maximum time allowed for power-down duration is t PD (MAX) (9 × t REFI).The power-down states are synchronously exited when CKE is registered HIGH (with arequired NOP or DES command). CKE must be maintained HIGH until t CKE has beensatisfied. A valid, executable command may be applied after power-down exit latency,t XP, and t XPDLL have been satisfied. A summary of the power-down modes is listed be-low.For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-to-power-down-entry sequence, the number of clock cycles between power-down exitand power-down entry may not be sufficient to keep the DLL properly updated. In addi-tion to meeting t PD when the REFRESH command is used between power-down exitand power-down entry, two other conditions must be met. First, t XP must be satisfiedbefore issuing the REFRESH command. Second, t XPDLL must be satisfied before thenext power-down may be entered. An example is shown in Figure 108 (page 194).Table 82: Power-Down ModesFigure 104: REFRESH to Power-Down EntryCK CK#CommandCKET0T1T2T3Ta0Ta1Ta2Tb0Don’t CareIndicates breakin time scale Note: 1.After CKE goes HIGH during t RFC, CKE must remain HIGH until t RFC is satisfied.Figure 105: ACTIVATE to Power-Down EntryCK CK#Command Address CKET0T1T2T3T4T5T6T74Gb: x4, x8, x16 DDR3L SDRAM Power-Down Mode。

PLC工控板WS3U-F精速系列产品使用说明书--V1.8适用于以下型号：WS3U-14MR/MT-FWS3U-24MR/MT-FWS3U-32MR/MT-FWS3U-48MR/MT-FWS3U-56MR-F产品目录第一章产品概述 (1)1.1产品概述 (1)1.2基本参数 (1)1.3使用环境及安装方式 (1)第二章产品展示 (2)2.1产品主要硬件说明 (2)2.2产品正面效果图 (2)第三章电气设计参考 (3)3.1电源及功耗 (3)3.2232通讯口说明 (3)3.3485通讯口说明 (4)3.4输入内部等效电路与接线说明 (5)3.5输出内部等效电路与接线说明.....................6-73.6模拟量输入说明 (7)3.7模拟量输出说明 (7)3.8产品接线图 (8)3.9高速脉冲输出与脉宽调制 (8)3.10中断说明 (9)3.1产品接线图....................................9-11第四章编程参考 (12)4.1应用环境 (12)4.2元件号的分配和功能概要 (12)4.3基本指令 (13)4.4应用指令....................................13-164.5此版本不支持指令列表, (16)第五章常见问题及解决方案 (17)第六章保修条款 (17)第一章产品概述1.1产品概述·WS3U精速系列，采用ARMCortex-M332位MISC内核芯片，运算速度快，存储空间大。

·下载速度为38.4Kbps(特殊情况也可申请改9.6k);直接使用三菱GX Developer或者GX Works2编程、下载、调试、监视（不支持监控写入）.·采用DC24V供电;输出继电器均不打开条件下，静态电流30MA;每打开一路增加10MA电流，如3U-48mr输出继电器全打开后电流为270MA（6.48W）。

地址：厦门市软件园观日路44号3层 1 总机：0592-*******无 线 路 由 器F3323 EDGE ROUTER目 录第一章产品简介 (3)1.1产品概述 (3)1.2产品特点 (3)1.3系统组成 (3)1.4工作原理 (3)1.5技术参数 (4)第二章 安装 (5)2.1概述 (5)2.2 开箱 (5)2.3安装与电缆连接 (5)2.4电源说明 (7)2.5指示灯说明 (7)2.6复位按钮说明 (7)第三章参数配置 (8)3.1 配置连接图 (8)3.2 登录到配置页面 (8)3.3 配置和管理 (9)附录 (23)地址：厦门市软件园观日路44号3层 2 总机：0592-*******地址：厦门市软件园观日路44号3层 3 总机：0592-******* 第一章 产品简介1.1产品概述F3323 EDGE ROUTER(本文简称ROUTER) 利用EDGE 网络平台，为用户提供高速、永远在线、透明传输的数据通道。

可广泛应用于电力、工控、交通、气象、金融、环保、煤矿、油田、证券等行业的数据传输。

同时，为了满足客户组网方面的需要，可实现虚拟数据专用网。

1.2产品特点¾ 支持VPN 、IPsec 、数据加密等安全功能¾ 支持无线视频监控和动态图像传输¾ 采用高性能的32位嵌入式处理器，可高速处理协议和大量数据 ¾ 支持TCP/IP 、UDP 、TELNET 、FTP 、HTTP 等完善的网络协议 ¾ 采用完备的防掉线机制，保证数据终端永远在线¾ WDT 看门狗设计，保持系统稳定¾ 智能型数据终端，上电即可进入数据传输状态 ¾ 使用方便，灵活，多种工作模式选择 ¾ 宽电源输入（DC 5~35V ）¾ 方便的系统配置和维护接口（WEB 方式或RS-232方式） ¾ 支持操作系统Windows 9x/ME/NT/2000/XP Linux Unix1.3系统组成ROUTER 系统主要由下列部分组成：¾ 高性能工业级ARM9 CPU ，主频200M ¾ 16MB SDRAM & 4MB FLAH ¾ 高性能工业级EDGE 无线模块1.4工作原理ROUTER 原理框图如下：1.5技术参数ROUTER技术指标：支持GSM850/900/1800/1900MHz支持全速率，增强全速率和半速率支持双音多频(DTMF)支持完善的AT命令GPRS Class B编码方案：CS1 - CS4符合SMG31bis技术规范接口:天线接口 50Ω/SMA（阴头）SIM卡 3V/1.8V自动检测支持RS232/485/422接口，数据速率110~230400bits/s支持10/100M 以太网接口供电:标准电压+12VDC/1.5A电压范围+5~+35VDC通信电流：<400 mA (12V)其他参数:尺寸157x97x25 mm (不包括天线和安装件)工作环境温度-25~+65ºC储存温度-40~+85ºC相对湿度 95%(无凝结)地址：厦门市软件园观日路44号3层 4 总机：0592-*******地址：厦门市软件园观日路44号3层 5 总机：0592-******* 第二章 安装2.1概述ROUTER 必须正确安装方可达到设计的功能，通常设备的安装必须在本公司认可合格的工程师指导下进行。

8、产品主要技术参数（含所用机芯、屏、电源的规格）
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误区1、用软布（眼镜布）或纸巾来擦拭液晶屏幕，建议使用专用的液晶擦拭布 千万不能用眼 镜布和纸巾来擦拭液晶屏幕，很容易划伤“娇气”的液晶屏幕。对于第一类灰尘，我们可以使用专 用的液晶擦拭布如supermax2020在液晶面板上轻轻擦拭，一般来说指纹和油污并非如前者那样 容易清除，但是如果使用专用的液晶擦拭布，这就不是一个难题了，因为专用的液晶擦拭布采用 的是特殊纤维，具有比一般高档眼镜布要好的多的擦拭效果，而且柔软不会擦伤屏幕，同时还具 有消散静电的独特功能； 特别提醒： 一般的布和纸巾是液晶面板的杀手！ 误区2、用清水清洁液晶屏幕。 使用清水，液体极易滴入液晶显示器和设备内部，这样会造成设备电路短路，从而烧坏昂贵的电 子设备。对于指纹和油污，清水照样无能为力。 误区3、用酒精和其它一些化学溶剂清洁液晶屏幕。 一般来说，酒精是一种常用的有机溶剂，可以溶解一些不容易擦去的污垢，如果只是用来清洁显 示器外壳，也没什么不良影响。但一定不要用酒精来清洁液晶屏幕，因为现在的液晶屏幕，都在 屏幕上涂有特殊的涂层，使屏幕具有更好的显示效果，一旦使用酒精擦拭显示器屏幕，就会溶解 这层特殊的涂层， 对显示效果造成不良影响。 用化学溶剂就更不可取，这种化学制剂对“骄气” 的液晶面板简直就是毁灭性的打击。 如果您的屏幕不小心沾上了果汁、口水或者咖啡等不易清楚的污渍，千万不要用纸巾或者眼镜布 之类的来使劲擦拭，因为这样很容易在擦掉污渍的同时也擦伤液晶屏幕；您可以用液晶专用擦拭 布如supermax2020喷加适量无离子水，使supermax2020略具潮湿感，然后再去擦拭，就可以 既让污渍无踪迹也不会擦伤您的液晶屏幕。
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NO NO yes NO yes yes no NO NO yes Stereo 2 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 1 3D NO 支持 NO 支持 支持 支持 支持 支持 NO 支持 支持 支持 NO