KL5BUDV002中文资料
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GND SIE_DAT[3] SIE_DAT[4] VDD SIE_DAT[5] SIE_DAT[6] SIE_DAT[7] VDD GND GND SIE_DAT[8] SIE_DAT[9] VDD SIE_DAT[10] SIE_DAT[11] GND SIE_DAT[12] SIE_DAT[13] SIE_DAT[14] CKOUT SIE_DAT[15] GND PU_SE0N FS_HSN CRCACT TXACT WDVLD VDD GND TXRDY RXERR CRCERR RXVLD RXACT VDD GND
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元器件交易网
KL5BUDV002
USB2.0 to PCI BUS Pin Diagram 144LQFP
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元器件交易网
KL5BUDV002
USB2.0 to PCI BUS General Description
The Kawasaki KL5BUDV002 is a high performance device that transfers data between the USB2.0 highspeed BUS and the PCI 33MHz, 32 bit BUS. This device easily interfaces with our USB 2.0 transceivers, the KL5KUSB200 and KL5KUSB201. The KL5BUDV002 is an ideal solution to convert a PCI device to a USB2.0 interface with its HS_SIE USB2.0 Transceiver interface, 4 sets of high-speed bulk packet size buffers, PCI interface and PCI master 2DMA channel support.
Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice form Kawasaki LSI April 2002 • ©Copyright 2002 • Kawasaki LSI • Printed in U.S.A
Block Diagram
HS D+ HS DRpu RPU_EN A
KL5BUDV002
KL5KUSB 200/201
SIE 16 b
PCI 32 b
HS_SIE
USB 2.0 D+ Rs 30 MHz USB 2.0 DRs
DBUF
PCI IF
33 MHz
Clock Generator
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • Ver. 1.3
ቤተ መጻሕፍቲ ባይዱ
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KL5BUDV002
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GND VDD AD[28] AD[27] GND AD[26] AD[25] AD[24] VDD GND GND VDD CBEN[3] IDSEL AD[23] GND GND AD[22] AD[21] AD[20] GND VDD AD[19] AD[18] GND GND VDD AD[17] AD[16] CBEN[2] GND VDD FRAMEN IRDYN GND TRDYN
AD[29] AD[30] AD[31] GND REQN GNTN CLK RSTN INTAN VDD VDD GND TESTO TESTI[0] TESTI[1] TESTI[2] TESTI[3] VBDET GND GND P_MODE[0] P_MODE[1] P_MODE[2] MODE[0] MODE[1] MODE[2] MODE[3] URSTN VDD VDD SUSPN BSTAT[0] BSTAT[1] SIE_DAT[0] SIE_DAT[1] SIE_DAT[2]
Features
• • • • • • • 33MHz PCI interface 30MHz USB 2.0 SIE BUS for High-Speed SIE operation Double packet buffer - 512x2 HS, 64Bx2 FS Internal DMA operation between the High-Speed SIE and Double Buffer Interfaces with USB 2.0 PHY High-Speed chirp protocol High-Speed/Full-Speed compatibility • • • • • • • • USB basic operation and transaction control Up to 5 endpoints PCI interface for Target and Master (2 DMA) modes Page and Descriptor DMA Modes USB data access by PCI target or DMA 0.35u Std cell technology Vdd = 3.3V, Ta = 0~70°C 144 pin LQFP package (20 mm2)
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • Ver. 1.3
DEVSELN STOPN GND VDD PAR CBEN[1] GND AD[15] AD[14] AD[13] GND VDD AD[12] AD[11] GND GND GND VDD AD[10] AD[9] AD[8] GND VDD CBEN[0] AD[7] GND AD[6] AD[5] AD[4] GND VDD AD[3] AD[2] GND AD[1] AD[0]