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基于遗传算法的非线性系统时变时滞的在线估计方法
张泳健;周东华
【期刊名称】《控制与决策》
【年(卷),期】2000(15)6
【摘要】针对系统输入带有纯时滞的一类非线性系统 ,选择有限点的输出误差的平方和构成适应度函数 ,采用十进制编码技术 ,提出一种基于遗传算法的非线性系统时变时滞的在线估计方法 ,该方法具有一定的抗噪声能力。
仿真实验结果验证了所提出方法的有效性。
【总页数】3页(P756-758)
【关键词】遗传算法;非线性系统;时变时滞;估计;在线估计
【作者】张泳健;周东华
【作者单位】清华大学自动化系
【正文语种】中文
【中图分类】O231.2;TP271
【相关文献】
1.具有时变时滞非线性动态系统的在线时滞估计 [J], 谭永红
2.非线性时变系统时滞和参数在线联合估计的SMSA方法 [J], 王凌;李令莱;郑大钟;周东华
3.基于Razumikhin方法的二阶随机非线性时变时滞系统的输出反馈控制 [J], 王妍;王天成
4.基于Razumikhin方法的n阶随机非线性时变时滞系统的输出反馈控制 [J], 尹力;王天成
5.基于Razumikhin方法的三阶非线性时变时滞系统的输出反馈镇定 [J], 庄迪;王天成
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一种可变步长时延估计方法
吴振英
【期刊名称】《光盘技术》
【年(卷),期】2009(000)004
【摘要】推导基于参数模型的自适应时延估计算法,分析提高收敛速度的可变步长方法,针对实际应用,给出一种利用功率因子估值估计实际环境中噪声与信号功率的方法.实验结果表明,基于可变步长的自适应时延估计算法具有更快的收敛速度和更小的稳态均方估计误差.
【总页数】2页(P38-39)
【作者】吴振英
【作者单位】苏州工业职业技术学院,江苏,苏州,215004
【正文语种】中文
【中图分类】TP301.6
【相关文献】
1.可变步长自适应时延估计方法研究 [J], 夏崔春;钱进
2.一种基于可变步长量化调制的地理数据库水印方法 [J], 汪传建;葛贺飞;丁卵;彭智勇;彭煜玮;宋伟;王俊舟
3.一种改进的广义循环相关熵时延估计方法 [J], 邱天爽;刘浩;张家成;李景春;李蓉
4.一种互谱相位在时延估计中的应用方法 [J], 丁超;陈喆;张宗堂;程玉胜
5.一种改进加权函数的GCC时延估计方法研究 [J], 魏文亮;茅玉龙
因版权原因，仅展示原文概要，查看原文内容请购买。
机器学习算法与电力设备故障预测分析在当前信息时代，机器学习算法正逐渐渗透到各行各业中，其中包括电力设备故障预测分析领域。
机器学习算法可以通过学习历史数据、提取特征并建立模型，进一步预测电力设备的故障情况，从而提前采取相应的维修和保养措施，降低设备故障对电力系统的影响。
一、机器学习算法在电力设备故障预测分析中的应用在电力设备故障预测分析中，机器学习算法可以应用于以下几个方面：1. 数据采集与处理：不同类型的电力设备存在不同的故障模式，因此需采集大量的设备运行数据，并对其进行处理和预处理。
2. 特征提取：特征提取是机器学习算法中的重要步骤，通过对采集到的数据进行分析，提取出与设备故障相关的特征，如振动信号中的频谱分析、温度变化等。
3. 模型建立：通过机器学习算法，可根据特征提取的结果建立相应的预测模型，如基于神经网络、支持向量机等算法建立故障预测模型。
4. 故障预测与评估：使用机器学习算法的模型对新的数据进行预测，从而提前发现电力设备可能存在的故障情况。
同时，对预测结果进行评估，不断优化模型的准确性和可靠性。
二、机器学习算法在电力设备故障预测分析中的优势在电力设备故障预测分析中应用机器学习算法有以下优势：1. 高效准确：机器学习算法能够基于历史数据对电力设备的运行状态进行全面分析，从而准确预测设备的故障情况。
相比传统的手动分析方法，机器学习算法在效率和准确性上更具优势。
2. 自动化处理：机器学习算法能够自动化地完成数据处理、特征提取和模型建立等过程，减轻人工操作的工作量，并提高预测与分析的效率。
3. 预防性维护：机器学习算法能够提前预测设备的故障情况，使得电力系统可以采取预防性维护措施，避免设备故障对电力供应和生产造成的损失。
4. 模型优化：机器学习算法的模型建立过程中，可以不断根据新的运行数据对模型进行优化和调整，提高预测准确性和稳定性。
三、机器学习算法在电力设备故障预测分析中的实际应用案例1. 基于神经网络的变压器故障预测：某电力公司利用神经网络算法分析变压器的抽头电流和温度变化等参数，建立了变压器故障预测模型。
网络故障模型之TransitionDelayVSPathDelay随着集成电路工艺技术的不断进步，今天的集成电路产品具有体积小，集成度高，性能好等特点。
一个合格的集成电路产品不仅要实现特定的功能，更要在满足一定性能要求的前提下功能正确。
而在130nm及以下的工艺中，人们越来越多的观测到这样一个问题：低频时钟的时候，制造出的芯片功能正确；但当提高到一定程度时就会导致芯片不能正常工作。
这种性能相关，导致芯片产品不能满足时序设计需求的制造缺陷正越来越成为影响芯片质量的主要因素之一。
Transition Delay VS Path Delay传统的stuck-at故障模型已不能充分覆盖这一类问题，因而新的delay故障模型应运而生。
对delay故障模型求解的结果就是产生出所谓的at-speed测试向量。
此类测试向量的应用对减少芯片DPM(Defect Per Million)，提高产品良率有着非常明显的效果。
本文的重点不是介绍at-speed测试向量，而是通过对两类主流的delay故障模型的比较，让读者更好得了解相关问题，并彻底掌握delay故障模型。
Transition delay和path delay是业界广泛采用的两种delay故障模型。
下面我们就从不同的方面来比较剖析这两种故障模型。
1、模型定义Delay故障是一个很直观的概念，它是指在芯片某区域的过度延迟导致其不能在一个系统时钟周期内完成数据的传递。
Transition delay模型是模拟CUT(circuit under test)中某一node上的过度延迟，该延迟大到令所有经过其的时序路径都不能在系统时钟周期内完成数据的传递。
在具体实现中，定义中的node通常是指gate的输入输出信号。
Path delay模型则是模拟时序路径上的gate及连线的累积delay。
相比较transition delay模型，Path delay更接近于芯片中的实际问题。
电力电子系统阻抗测量的分段二叉树法岳小龙;卓放;张政华;师洪涛;张东【摘要】在分析和设计包含电力电子变换器的系统时,由于阻抗和系统稳定性之间的密切关系,阻抗测量就显得十分重要.传统的扫频法采用等频率间隔的方式注入扰动信号并测量电力电子系统阻抗,由于不能在测量结果和测量过程之间建立起有效的联系,因此是一种低准确性、低效率和低可靠性的开环测量方法.通过建立阻抗测量结果准确度和测量频率间隔之间的数学关系,提出了一种分段二叉树阻抗测量方法.使用该方法,可以根据结果的准确度要求自动地确定测量频率点的位置,与传统的扫频法相比,本文提出的方法可以更加准确和有效地测量电力电子系统阻抗.单相交流系统和三相交流系统的阻抗测量结果证明了提出的方法的有效性.【期刊名称】《电工技术学报》【年(卷),期】2015(030)024【总页数】8页(P76-83)【关键词】电力电子系统;阻抗测量;频率扫描;二叉树;误差校验【作者】岳小龙;卓放;张政华;师洪涛;张东【作者单位】西安交通大学电气工程学院西安 710049;西安交通大学电气工程学院西安 710049;西安交通大学电气工程学院西安 710049;西安交通大学电气工程学院西安 710049;西安交通大学电气工程学院西安 710049【正文语种】中文【中图分类】TM46;TM934电力电子变换器的恒功率特性会导致系统因为负阻抗而不稳定［1-14］，因此，在包含电力电子变换器的系统设计中，小信号稳定性分析就显得非常重要。
一种常见的方法是建立系统的小信号模型，通过零极点来分析系统的稳定性。
但是，在实际应用中，建模需要的参数很难准确获取，因而限制了这种方法的使用。
自从1976年R. D. Middlebrook第一次提出系统稳定性和输入、输出阻抗之间的关系［2］，基于阻抗的稳定性判据开始获得广泛的应用。
尤其是当系统的各部分组件由不同制造商提供时，阻抗稳定性判据显得更加方便，因为测量输入、输出阻抗比建立小信号模型容易的多。
基于机器学习的电力设备故障预测在当今这个高度依赖电力的时代，电力设备的稳定运行对于社会的正常运转至关重要。
然而，电力设备在长期运行过程中，不可避免地会出现各种故障。
这些故障不仅会影响电力的正常供应，还可能给企业和社会带来巨大的经济损失。
因此，如何提前预测电力设备的故障，以便及时进行维护和修理，成为了电力行业亟待解决的重要问题。
传统的电力设备故障检测方法主要依赖人工巡检和定期维护，但这种方法存在效率低下、准确性不高以及无法及时发现潜在故障等缺点。
随着科技的不断发展，机器学习技术的出现为电力设备故障预测带来了新的思路和方法。
机器学习是一种让计算机通过数据学习和自动改进的技术。
在电力设备故障预测中，机器学习可以通过对大量历史数据的分析，挖掘出设备运行状态与故障之间的潜在关系，从而实现对未来故障的准确预测。
首先，我们需要收集大量的电力设备运行数据，包括电压、电流、功率、温度、湿度等参数。
这些数据就像是设备的“健康档案”，记录了设备在不同时间和工作条件下的状态。
然后，通过对这些数据进行预处理，例如去除噪声、填补缺失值等，为后续的分析做好准备。
在选择机器学习算法时，需要根据具体的问题和数据特点进行选择。
常见的算法包括决策树、随机森林、支持向量机、神经网络等。
以决策树为例，它通过对数据进行一系列的逻辑判断，构建出一棵类似于流程图的树状结构，从而实现对故障的预测。
而随机森林则是由多个决策树组成的集成模型，通过综合多个决策树的预测结果，提高预测的准确性和稳定性。
支持向量机则是通过寻找一个最优的超平面，将正常数据和故障数据分开。
神经网络则是模拟人类大脑的神经元网络，通过大量的训练来学习数据中的复杂模式。
在实际应用中，我们可以将收集到的数据分为训练集、验证集和测试集。
训练集用于训练模型，让模型学习数据中的规律；验证集用于调整模型的参数，选择最优的模型；测试集则用于评估模型的性能，检验模型在新数据上的预测能力。
为了提高预测的准确性，还可以采用特征工程的方法。
同济大学结构动力学期末考试1.What are the step-by-step methods for calculating structural dynamicresponse? (有哪些方法)Interpolation of excitation methodCentral difference methodNewmark’s methodWilson-methodState space method2.Degree of freedom:(1)The number of independent displacement required to define thedisplaced positions of all the masses relative to their original positions is called the number degrees of freedom(DOFs) (chopra)(2)The number of displacement quantities that must be considered torepresent the effects of all significant inertia force is called the number of freedoms of a system. Roy R. Craig3.Effect of damping in vibration:a)Natural frequency of damped systemb)Natural Period of damped systemc)Existence of damping will reduce the natural frequencyd)For normal structuree)The displacement amplitude decays exponentially with timef)The effect of damping is on the rate at which free vibrationdecays4.Mode Shape: it associates with frequency. And, it is deformed modeof object at that frequency. Example: resonance occurred when , it makes the maximum deformation, different shape (deformation), different frequency.Mode shape is the proportional relationship among the displacement of DOFs.Mode shape is most likely to occur in the form of the deformation, and the first mode is the easiest one. Therefore, shape functionsare selected as close as possible to the mode shape to simplify theanalysis.s of methods for determining the first several vibrations modesof a MDOF system?Superposition methodRayleigh-Ritz methodReyleigh methodMatrix iteration methodJacobi iteration methodSubspace iteration methodStodola iteration method6.For SDOF system under harmonic loading, when the frequency rationis very small the amplitude factor is close to 1, when becomes very large becomes very small, explain why?1.单自由度系统承受谐波荷载，当频率比很小时，振幅放大系数接近于1，当频率比很大时，振幅放大系数较小。
SAMPLING, ADVANCEDDIGITALĆTOĆANALOGD5-V Tolerant Digital InputsESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.PRODUCTIONconform to specificationsProduction processingPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20062ORDERING INFORMATIONPRODUCTPACKAGEPACKAGE CODEOPERATION TEMPERATURERANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA°°PCM1798DB Tube PCM1798DB 28-lead SSOP 28DB–25C to 85CPCM1798PCM1798DBRT ape and reelABSOLUTE MAXIMUM RATINGSover operating free-air temperature range unless otherwise noted (1)PCM1798V CC 1, V CC 2L, V CC 2R –0.3 V to 6.5 V Supply voltageV DD–0.3 V to 4 V Supply voltage differences: V CC 1, V CC 2L, V CC 2R±0.1 V Ground voltage differences: AGND1, AGND2, AGND3L, AGND3R, DGND ±0.1 V LRCK, DATA, BCK, SCK, FMT1, FMT0, MONO, CHSL, DEM, MUTE, RST ,–0.3 V to 6.5 VDigital input voltage ZERO–0.3 V to (V DD + 0.3 V) < 4 V Analog input voltage–0.3 V to (V CC + 0.3 V) < 6.5 VInput current (any pins except supplies)±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°CJunction temperature 150°C Lead temperature (soldering)260°C, 5 s Package temperature (IR reflow, peak)260°C(1)Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.ELECTRICAL CHARACTERISTICSall specifications at T A = 25°C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data, unless otherwise notedPCM1798DB PARAMETERTEST CONDITIONSMINTYP MAXUNIT RESOLUTION 24BitsDATA FORMATAudio data interface format Standard, I 2S, left-justified Audio data bit length 16-, 24-bit selectable Audio data formatMSB first, 2s complement f SSampling frequency 10200kHzSystem clock frequency128, 192, 256, 384, 512, 768 f SDIGITAL INPUT/OUTPUTLogic familyTTL compatibleV IH 2V IL Input logic level 0.8VDC I IH V IN = V DD 10A I IL Input logic current V IN = 0 V –10µV OH I OH = –2 mA 2.4V OLOutput logic levelI OL = 2 mA0.4VDCPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20063ELECTRICAL CHARACTERISTICS (Continued)all specifications at T A = 25°C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data, unless otherwise notedPCM1798DB PARAMETERTEST CONDITIONSMINTYPMAXUNITDYNAMIC PERFORMANCE (1)(2)f S = 44.1 kHz 0.0005%0.001%THD+N at V f S = 96 kHz0.001%OUT = 0 dBf S = 192 kHz0.0015%EIAJ, A-weighted, f S = 44.1 kHz120123EIAJ, A-weighted, f S = 96 kHz 123Dynamic rangeEIAJ, A-weighted, f S = 192 kHz 123dBEIAJ, A-weighted, f S = 44.1 kHz 120123EIAJ, A-weighted, f S = 96 kHz 123Signal-to-noise ratioEIAJ, A-weighted, f S = 192 kHz 123dB f S = 44.1 kHz116119f S = 96 kHz 118Channel separation f S = 192 kHz 117dB Level linearity errorV OUT = –120 dB±1dB DYNAMIC PERFORMANCE (MONO MODE) (1)(2)(3)f S = 44.1 kHz 0.0005%THD+N at V f S = 96 kHz0.001%OUT = 0 dBf S = 192 kHz0.0015%EIAJ, A-weighted, f S = 44.1 kHz126EIAJ, A-weighted, f S = 96 kHz 126Dynamic rangeEIAJ, A-weighted, f S = 192 kHz 126dBEIAJ, A-weighted, f S = 44.1 kHz 126EIAJ, A-weighted, f S = 96 kHz 126Signal-to-noise ratioEIAJ, A-weighted, f S = 192 kHz126dB (1)Filter condition:THD+N: 20-Hz HPF , 20-kHz AES17 LPFDynamic range: 20-Hz HPF , 20-kHz AES17 LPF , A-weightedSignal-to-noise ratio: 20-Hz HPF , 20-kHz AES17 LPF , A-weighted Channel separation: 20-Hz HPF , 20-kHz AES17 LPFAnalog performance specifications are measured using the System Two t Cascade audio measurement system by Audio Precision in the averaging mode.(2)Dynamic performance and dc accuracy are specified at the output of the postamplifier as shown in Figure 24.(3)Dynamic performance and dc accuracy are specified at the output of the measurement circuit as shown in Figure 25.Audio Precision and System Two are trademarks of Audio Precision, Inc.Other trademarks are the property of their respective owners.PCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20064ELECTRICAL CHARACTERISTICS (Continued)all specifications at T A = 25°C, V CC 1 = V CC 2L = V CC 2R = 5 V, V DD = 3.3 V, f S = 44.1 kHz, system clock = 256 f S , and 24-bit data, unless otherwise notedPCM1798DB PARAMETERTEST CONDITIONSMINTYPMAXUNITANALOG OUTPUTGain error–7±27% of FSR Gain mismatch, channel-to-channel –3±0.53% of FSR Bipolar zero error At BPZ –2±0.52% of FSR Output current Full scale (0 dB)4mA p-p Center currentAt BPZ–3.5mADIGITAL FILTER PERFORMANCEDe-emphasis error±0.1dBFILTER CHARACTERISTICS–1: SHARP ROLLOFF±0.0002 dB 0.454 f S Pass band –3 dB0.49 f S Stop band 0.546 f SPass-band ripple ±0.0002dB Stop-band attenuation Stop band = 0.546 f S–98dB Delay time38/f SsFILTER CHARACTERISTICS–2: SLOW ROLLOFF±0.001 dB 0.21 f S Pass band –3 dB0.448 f SStop band 0.79 f SPass-band ripple ±0.001dB Stop-band attenuation Stop band = 0.732 f S–80dB Delay time38/f SsPOWER SUPPLY REQUIREMENTS V DD 33.3 3.6VDC V CC 1V CC 2L Voltage rangeV CC 2R 4.755 5.25VDCf S = 44.1 kHz 79I f S = 96 kHz 13DDSupply current f S = 192 kHz 25mA (1)f S = 44.1 kHz 1823I f S = 96 kHz 19CCf S = 192 kHz20mAf S = 44.1 kHz 115150Power dissipation f S = 96 kHz 140(1)f S = 192 kHz180mWTEMPERATURE RANGEOperation temperature–2585°C θJA Thermal resistance 28-pin SSOP100°C/W(1)Input is BPZ data.PCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20065PIN ASSIGNMENTS1234 5678910111213142827262524232221201918171615MONO CHSL DEM LRCK DATA BCK SCK DGND V DD MUTE FMT0FMT1ZERO RST V CC 2L AGND3L I OUT L–I OUT L+AGND2V CC 1V COM L V COM R I REF AGND1I OUT R–I OUT R+AGND3R V CC 2RPCM1798(TOP VIEW)PCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20066Terminal Functions TERMINALNAME PINI/O DESCRIPTIONSAGND119–Analog ground (internal bias)AGND224–Analog ground (internal bias)AGND3L27–Analog ground (L-channel DACFF)AGND3R16–Analog ground (R-channel DACFF)BCK6I Bit clock input (1)CHSL2I L-, R-channel select (1)DATA5I Serial audio data input (1)DEM3I De-emphasis enable (1)DGND8–Digital groundFMT011I Audio data format select (1)FMT112I Audio data format select (1)I OUT L+25O L-channel analog current output +I OUT L–26O L-channel analog current output –I OUT R+17O R-channel analog current output +I OUT R–18O R-channel analog current output –I REF20–Output current reference bias pinLRCK4I Left and right clock (f S) input (1)MONO1I Monaural mode enable (1)MUTE10I Mute control (1)RST14I Reset(1)SCK7I System clock input(1)V CC123–Analog power supply, 5 VV CC2L28–Analog power supply (L-channel DACFF), 5 V V CC2R15–Analog power supply (R-cahnnel DACFF), 5 V V COM L22–L-channel internal bias decoupling pinV COM R21–R-channel internal bias decoupling pinV DD9–Digital power supply, 3.3 VZERO13O Zero flag(1)Schmitt-trigger input, 5-V tolerantPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20067FUNCTIONAL BLOCK DIAGRAMPower SupplyFMT1S C KAdvanced Segment DAC ModulatorBias and VrefA G N D 2V D DV C C 1V C C 2LV C C 2RA G N D 18OversamplingDigital Filter and Function ControlAudio Data InputI/FLRCK BCK DATADEM RSTA G N D 3LA G N D 3RD G N DCurrent Segment DACI REF Function Control I/FZero DetectZEROSystem Clock ManagerFMT0MUTE Current Segment DACMONO CHSLV COM LV COM RI OUT L+I OUT L–I/V and FilterV OUT LI OUT R+I OUT R–I/V and FilterV OUT RPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20068TYPICAL PERFORMANCE CURVESDIGITAL FILTERDigital Filter ResponseFigure 1. Frequency Response, Sharp RolloffFrequency [× f S ]−160−140−120−100−80−60−40−20001234A m p l i t u d e – d BAMPLITUDEvsFREQUENCYFrequency [× f S ]−5−4−3−2−10123450.00.10.20.30.40.5A m p l i t u d e − d BAMPLITUDEvsFREQUENCY0.0005−0.0001−0.00050.00030.00040.00020.0001−0.0004−0.0003−0.0002Figure 2. Pass-Band Ripple, Sharp RolloffFigure 3. Frequency Response, Slow RolloffFrequency [× f S ]−160−140−120−100−80−60−40−20001234A m p l i t u d e – d BAMPLITUDEvsFREQUENCYFigure 4. Transition Characteristics, Slow RolloffFrequency [× f S ]−20−18−16−14−12−10−8−6−4−200.00.10.20.30.40.50.6A m p l i t u d e – d BAMPLITUDEvsFREQUENCYPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 20069De-Emphasis FilterFigure 5f – Frequency – kHz−10−9−8−7−6−5−4−3−2−1002468101214161820D e -E m p h a s i s L e v e l – d BDE-EMPHASIS LEVELvsFREQUENCYf S = 44.1 kHzFigure 6f – Frequency – kHz−0.5−0.4−0.3−0.2−0.1−0.00.10.20.30.40.502468101214161820DE-EMPHASIS ERRORvsFREQUENCYD e -E m p h a s i s E r r o r – d Bf S = 44.1 kHz0.0PCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 200610ANALOG DYNAMIC PERFORMANCESupply Voltage CharacteristicsFigure 74.504.755.00 5.25 5.50V CC – Supply Voltage – V TOTAL HARMONIC DISTORTION + NOISEvsSUPPLY VOLTAGE0.010.0010.0001f S = 96 kHzT H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %f S = 48 kHzf S = 192 kHzFigure 8V CC – Supply Voltage – V1161181201221241264.504.755.00 5.25 5.50D y n a m i c R a n g e – d BDYNAMIC RANGEvsSUPPLY VOLTAGEf S = 96 kHz f S = 48 kHzf S = 192 kHzFigure 9V CC – Supply Voltage – V 1161181201221241264.504.755.00 5.25 5.50S N R – S i g n a l -t o -N o i s e R a t i o – d BSIGNAL-to-NOISE RATIOvsSUPPLY VOLTAGEf S = 48 kHzf S = 192 kHzf S = 96 kHzFigure 10V CC – Supply Voltage – V1121141161181201224.504.755.00 5.25 5.50C h a n n e l S e p a r a t i o n – d BCHANNEL SEPARATIONvsSUPPLY VOLTAGEf S = 96 kHzf S = 192 kHzf S = 48 kHzNOTE:PCM mode, T A = 25°C, V DD = 3.3 V, measurement circuit is Figure 24.Temperature CharacteristicsFigure 11−50−250255075100TOTAL HARMONIC DISTORTION + NOISEvsFREE-AIR TEMPERATURE0.010.0010.0001f S = 192 kHzT H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %f S = 48 kHzT A – Free-Air Temperature – °C f S = 96 kHzFigure 12T A – Free-Air Temperature – °C116118120122124126−50−250255075100D y n a m i c R a n g e – d BDYNAMIC RANGEvsFREE-AIR TEMPERATUREf S = 96 kHzf S = 48 kHzf S = 192 kHzFigure 13T A – Free-Air Temperature – °C 116118120122124126−50−250255075100S N R – S i g n a l -t o -N o i s e R a t i o – d BSIGNAL-to-NOISE RATIOvsFREE-AIR TEMPERATUREf S = 96 kHzf S = 48 kHzf S = 192 kHzFigure 14T A – Free-Air Temperature – °C112114116118120122−50−250255075100C h a n n e l S e p a r a t i o n – d BCHANNEL SEPARATIONvsFREE-AIR TEMPERATUREf S = 192 kHzf S = 96 kHzf S = 48 kHzNOTE:PCM mode, V DD = 3.3 V, V CC = 5 V, measurement circuit is Figure 24.NOTE:f S = 48 kHz, 32768 point 8 average, T A = 25°C, V DD = 3.3 V,V CC = 5 V, measurement circuit is Figure 24.Figure 15. –60-db Output Spectrum, BW = 20 kHz f – Frequency – kHz−160−140−120−100−80−60−40−20002468101214161820A m p l i t u d e – d BAMPLITUDEvsFREQUENCYNOTE:f S = 96 kHz, 32768 point 8 average, T A = 25°C, V DD = 3.3 V,V CC = 5 V, measurement circuit is Figure 24.Figure 16. –60-db Output Spectrum, BW = 100 kHzf – Frequency – kHz−160−140−120−100−80−60−40−2000102030405060708090100A m p l i t u d e – d BAMPLITUDEvsFREQUENCYNOTE:f S = 48 kHz, T A = 25°C, V DD = 3.3 V, V CC = 5 V,measurement circuit is Figure 24.Figure 17. THD+N vs Input Level, PCM Mode−90−80−70−60−50−40−30−20−10Input Level – dBFSTOTAL HARMONIC DISTORTION + NOISEvsINPUT LEVEL100.10.010.0010.0001T H D +N – T o t a l H a r m o n i c D i s t o r t i o n + N o i s e – %1SYSTEM CLOCK AND RESET FUNCTIONSSystem Clock InputThe PCM1798 requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1798 has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. T able 1 shows examples of system clock frequencies for common audio sampling rates.Figure 18 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. One of the T exas Instruments PLL1700 family of multiclock generators is an excellent choice for providing the PCM1798 system clock.Table 1. System Clock Rates for Common Audio Sampling FrequenciesSYSTEM CLOCK FREQUENCY (f SCK ) (MHz)SAMPLING FREQUENCY128 f S 192 f S 256 f S 384 f S 512 f S 768 f S 32 kHz 4.096 6.1448.19212.28816.38424.57644.1 kHz 5.64888.467211.289616.934422.579233.868848 kHz 6.1449.21612.28818.43224.57636.86496 kHz 12.28818.43224.57636.86449.15273.728192 kHz24.57636.86449.15273.728–(1)–(1)(1)This system clock rate is not supported for the given sampling frequency.t (SCKH)t (SCY)System Clock (SCK)t (SCKL)2 V0.8 V HLPARAMETERSMIN MAXUNITS t (SCY)System clock pulse cycle time13ns t (SCKH)System clock pulse duration, HIGH 0.4 t (SCY)ns t (SCKL)System clock pulse duration, LOW0.4 t (SCY)nsFigure 18. System Clock Input TimingPower-On and External Reset FunctionsThe PCM1798 includes a power-on reset function. Figure 19 shows the operation of this function. With V DD > 2 V,the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V DD > 2 V.The PCM1798 also includes an external reset capability using the RST input (pin 14). This allows an external controller or master reset circuit to force the PCM1798 to initialize to its default reset state.Figure 20 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The external reset is especially useful in applications where there is a delay between the PCM1798 power up and system clock activation.ResetReset Removal1024 System ClocksV DD2.4 V (Max)2 V (Typ)1.6 V (Min)Internal ResetSystem ClockFigure 19. Power-On Reset TimingReset Reset Removal1024 System ClocksInternal ResetSystem ClockRST (Pin 14)t (RST)1.4 VPARAMETERSMIN MAXUNITS t (RST)Reset pulse duration, LOW20nsFigure 20. External Reset TimingAUDIO DATA INTERFACEAudio Serial InterfaceThe audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1798 on the rising edge of BCK. LRCK is the serial audio left/right word clock.The PCM1798 requires the synchronization of LRCK and the system clock, but does not need a specific phase relation between LRCK and the system clock.If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is initialized within 1/f S and the analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system clock is completed.PCM Audio Data Formats and TimingThe PCM1798 supports industry-standard audio data formats, including standard right-justified, I 2S, and left-justified. The data formats are shown in Figure 22. Data formats are selected using FMT0 (pin 11) and FMT1(pin 12) as shown in Table 2. All formats require binary twos-complement, MSB-first audio data. Figure 21 shows a detailed timing diagram for the serial audio interface.DATAt (BCH)1.4 VBCKLRCKt (BCL)t (LB)t (BCY)t (DS)t (DH)1.4 V 1.4 Vt (BL)PARAMETERSMIN MAXUNITS t (BCY)BCK pulse cycle time 70ns t (BCL)BCK pulse duration, LOW 30ns t (BCH)BCK pulse duration, HIGH 30ns t (BL)BCK rising edge to LRCK edge 10ns t (LB)LRCK edge to BCK rising edge 10ns t (DS)DATA setup time 10ns t (DH)DATA hold time 10ns—LRCK clock data50% ± 2 bit clocksFigure 21. Timing of Audio Interface141516121516MSBLSB121516222324LSB12322412322421MSBLSB12241224LSB1224211224BCKL-ChannelDATAR-Channel1/f SDATALRCKAudio Data Word = 16-BitAudio Data Word = 24-BitBCKL-ChannelDATAR-Channel1/f SLRCKAudio Data Word = 24-Bit23232323BCKL-ChannelDATAR-Channel1/f SLRCKAudio Data Word = 24-BitMSBMSB(2) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW(1) Standard Data Format (Right-Justified); L-Channel = HIGH, R-Channel = LOW(3) I 2S Data Format; L-Channel = LOW, R-Channel = HIGHFigure 22. Audio Data Input FormatsFUNCTION DESCRIPTIONSAudio data formatAudio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1798 also supports monaural mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1798 can select the DF rolloff characteristics.Table 2. Audio Data Format SelectMONO CHSL FMT1FMT0FORMAT STEREO/MONO DF ROLLOFF 0000I2S Stereo Sharp0001Left-justified format Stereo Sharp0010Standard, 16-bit Stereo Sharp0011Standard, 24-bit Stereo Sharp0100I2S Stereo Slow0101Left-justified format Stereo Slow0110Standard, 16-bit Stereo Slow0111Digital filter bypass Mono–1000I2S Mono, L-channel Sharp1001Left-justified format Mono, L-channel Sharp1010Standard, 16-bit Mono, L-channel Sharp1011Standard, 24-bit Mono, L-channel Sharp1100I2S Mono, R-channel Sharp1101Left-justified format Mono, R-channel Sharp1110Standard, 16-bit Mono, R-channel Sharp1111Standard, 24-bit Mono, R-channel SharpSoft MuteThe PCM1798 supports mute operation. When MUTE (pin 10) is set to HIGH, both analog outputs are transitioned to the bipolar zero level in –0.5-dB steps with a transition speed of 1/f S per step. This system provides pop-free muting of the DAC output.De-EmphasisThe PCM1798 has a de-emphasis filter for the sampling frequency of 44.1 kHz. The de-emphasis filter is controlled using DEM (pin 3).Zero DetectionWhen the PCM1798 detects that the audio input data in the L-channel and the R-channel is continuously zero for 1024 LRCKs in the PCM mode, or that the audio input data is continuously zero for 1024 WDCKs in the external filter mode, the PCM1798 sets ZERO (pin 13) to HIGH.APPLICATION INFORMATIONTYPICAL CONNECTION DIAGRAMDATA 24232221201918171615567891011121314PCM1798BCK SCK DGND V DDMUTE FMT0FMT1ZERO RST AGND2I OUT R–V CC 1V COM L V COM R I REF I OUT R+AGND3R AGND1–+MONO 1234CHSL DEM LRCK 28272625V CC 2L AGND3L I OUT L–I OUT L+V OUTL-Channel5 V V CC 2R0.1 µFController10 µF3.3 V PCM Audio Data Source0.1 µF10 µFC f R fDifferentialto Single Converter With Low-Pass Filter47 µF 5 V10 µF10 k Ω–+C f R f–+V OUTR-ChannelC f R fDifferentialto Single Converter With Low-Pass Filter–+C f R f0.1 µF10 µF 5 V+++++Figure 23. Typical Application CircuitAPPLICATION CIRCUITThe design of the application circuit is very important in order to actually realize the high S/N ratio of which the PCM1798 is capable. This is because noise and distortion that are generated in an application circuit are not negligible.In the third-order LPF circuit of Figure 24, the output level is 2.1 V RMS, and 123 dB S/N is achieved.I/V SectionThe current of the PCM1798 on each of the output pins (I OUT L+, I OUT L–, I OUT R+, I OUT R–) is 4 mA p-p at 0 dB (full scale). The voltage output level of the I/V converter (Vi) is given by following equation:Vi = 4 mA p–p × R f (R f : feedback resistance of I/V converter)An NE5534 operational amplifier is recommended for the I/V circuit to obtain the specified performance. Dynamic performance such as the gain bandwidth, settling time, and slew rate of the operational amplifier affects the audio dynamic performance of the I/V section.Differential SectionThe PCM1798 voltage outputs are followed by differential amplifier stages, which sum the differential signals for each channel, creating a single-ended I/V op-amp output. In addition, the differential amplifiers provide a low-pass filter function.The operational amplifier recommended for the differential circuit is the low-noise type.–+R1 820 Ω2 375864C110.1 µFC1722 pF V CCC12700 pFC120.1 µF V EEU1NE5534I OUT––+R2 820 Ω2 375864C130.1 µFC1822 pF V CCC22700 pFC140.1 µF V EEU2NE5534I OUT+–+2374C150.1 µFV CCC160.1 µFV EEU3NE5534R9100 ΩC38200 pFR5200 ΩC48200 pFR6200 ΩR3220 ΩR4220 ΩV CC = 15 VV EE = –15 Vf c = 50 kHzC527000 pFR7180 ΩR8180 Ω586C1922 pFFigure 24. Measurement CircuitI OUT –Figure 24 CircuitI OUT +I OUT L– (Pin 26)I OUT L+ (Pin 25)OUT+123Balanced OutI OUT –Figure 24 CircuitI OUT +I OUT R– (Pin 18)I OUT R+ (Pin 17)OUT–Figure 25. Measurement Circuit for Monaural ModePCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006APPLICATION FOR EXTERNAL DIGITAL FILTER INTERFACEDATA 24232221201918171615567891011121314PCM1798BCK SCK DGND V DDMUTE FMT0FMT1ZERO RSTAGND2I OUT R–V CC 1V COM L V COM R I REF I OUT R+AGND3R AGND1MONO 1234CHSL DEM LRCK 28272625V CC 2L AGND3L I OUT L–I OUT L+V CC 2RDATA AnalogOutput Stage (See Figure 23)WDCK BCK SCKExternal Filter DeviceV DDFigure 26. Connection Diagram for External DIgital Filter (Internal DF Bypass Mode) Application Application for Interfacing With an External Digital FilterFor some applications, it may be desirable to use a programmable digital signal processor as an external digital filter to perform the interpolation function. The following pin settings enable the external digital filter application mode.D MONO (pin 1) = LOW D CHSL (Pin 2) = HIGH D FMT0 (Pin 11) = HIGH DFMT1 (pin 12) = HIGHThe pins used to provide the serial interface for the external digital filter are shown in the connection diagram of Figure 26. The word clock (WDCK) must be operated at 8× or 4× the desired sampling frequency, f S .Pin Assignment When Using the External Digital Filter InterfaceD LRCK (pin 4): WDCK as word clock input D DATA (pin 5): Monaural audio data input D BCK (pin 6): Bit clock inputPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006Audio FormatThe PCM1798 in the external digital filter interface mode supports the 24-bit right-justified audio format as shown in Figure 27.BCK1/4 f S or 1/8 f SWDCKAudio Data Word = 24-BitMSBLSB1612345678910111213141524232017181924212223DATAFigure 27. Audio Data Input Format for External Digital Filter (Internal DF Bypass Mode) Application System Clock (SCK) and Interface TimingThe PCM1798 in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK. Interface timing among WDCK, BCK, and DATA is shown in Figure 28.DATAt (BCH)1.4 VBCKWDCKt (BCL)t (LB)t (BCY)t (DS)t (DH)1.4 V 1.4 Vt (BL)PARAMETERMIN MAXUNITS t (BCY)BCK pulse cycle time 20ns t (BCL)BCK pulse duration, LOW7ns t (BCH)BCK pulse duration, HIGH 7ns t (BL)BCK rising edge to WDCK falling edge 5ns t (LB)WDCK falling edge to BCK rising edge 5ns t (DS)DATA setup time 5ns t (DH)DATA hold time5nsFigure 28. Audio Interface Timing for External Digital Filter (Internal DF Bypass Mode) ApplicationPCM1798SLES102A – DECEMBER 2003 – REVISED NOVEMBER 2006ANALOG OUTPUTTable 3 and Figure 29 show the relationship between the digital input code and analog output.Table 3. Analog Output Current and Voltage800000 (–FS)000000 (BPZ)7FFFFF (+FS)I OUT N [mA]–1.5–3.5–5.5I OUT P [mA]–5.5–3.5–1.5V OUT N [V]–1.23–2.87–4.51V OUT P [V]–4.51–2.87–1.23V OUT [V]–2.980 2.98NOTE:V OUT N is the output of U1, V OUT P is the output of U2, and V OUT is the output of U3 in themeasurement circuit of Figure 24.−6−5−4−3−2−1Input Code – HexI OUT NI O – O u t p u t C u r r e n t – m AOUTPUT CURRENTvsINPUT CODE800000(–FS)000000(BPZ)7FFFFF(+FS)I OUT PFigure 29. The Relationship Between Digital Input and Analog OutputPACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)PCM1798DB ACTIVE SSOP DB 2847Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCM1798DBG4ACTIVE SSOP DB 2847Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCM1798DBR ACTIVE SSOP DB 282000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM PCM1798DBRG4ACTIVESSOPDB282000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge andbelief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM11-Dec-2006。
一种快速鲁棒自适应故障估计方法设计随着工业自动化的快速发展，工业生产过程中的故障检测和诊断变得越来越重要。
故障估计是一种在工业生产中广泛应用的技术，它可以对生产过程中的故障进行快速、准确的诊断和定位。
本文将介绍一种快速鲁棒自适应故障估计方法的设计和实现。
一、研究背景工业生产过程中，故障的发生率很高，而且故障的类型和原因也非常复杂。
传统的故障检测方法通常是基于模型的方法，需要对生产过程建立模型，并且需要使用专业的工具进行模型的建立和参数的识别。
这种方法存在着模型建立时间长、模型精度不高等问题。
因此，研究一种快速鲁棒自适应故障估计方法成为了当前研究的热点。
二、研究内容本文提出的快速鲁棒自适应故障估计方法主要包括两个部分：数据预处理和故障估计。
1. 数据预处理数据预处理是一种对原始数据进行处理，以便于后续的故障估计。
在数据预处理过程中，我们首先需要对原始数据进行滤波，以去除噪声和干扰。
然后，我们需要进行特征提取，提取出与故障相关的特征。
最后，我们需要对特征进行归一化处理，使得特征之间的尺度相同，方便后续的处理。
2. 故障估计故障估计是本文的核心内容。
我们采用的是一种基于支持向量机（SVM）的故障估计方法。
SVM是一种基于统计学习理论的分类器，它可以对数据进行分类和预测。
在故障估计过程中，我们首先需要对SVM进行训练，以建立故障分类模型。
然后，我们需要对新的数据进行预测，以判断是否存在故障。
最后，我们需要对预测结果进行评估，以确定故障的类型和位置。
三、实验设计为了验证本文提出的快速鲁棒自适应故障估计方法的有效性，我们进行了一系列的实验。
实验使用的数据是从一台工业机器人系统中采集的。
我们将数据分为训练集和测试集，其中训练集用于建立故障分类模型，测试集用于验证模型的准确性。
在实验中，我们比较了本文提出的方法和传统的基于模型的故障检测方法。
实验结果表明，本文提出的方法具有更高的准确率和更快的响应速度。
同时，本文提出的方法具有良好的鲁棒性，可以有效地应对数据的变化和噪声的干扰。
第 36 卷第 4 期2023 年8 月振 动 工 程 学 报Journal of Vibration EngineeringVol. 36 No. 4Aug. 2023周期与色噪声联合作用下分数阶Duffing振子非平稳响应的无记忆方法李书进1，张志聪1，孔凡2，韩仁杰1（1.武汉理工大学土木工程与建筑学院，湖北武汉 430070；2.合肥工业大学土木与水利工程学院，安徽合肥 230009）摘要: 基于统计线性化提出了一种求解周期与色噪声激励联合作用下分数阶Duffing系统非平稳响应的无记忆方法。
将系统响应分解为确定性周期和零均值随机分量之和，则原非线性运动方程可等效地化为一组耦合的、分别以确定性和随机动力响应为未知量的分数阶微分方程。
利用无记忆化方法将确定性和随机分数阶微分方程转化为相应的常微分方程。
利用统计线性化方法处理随机常微分方程，得到关于随机响应二阶矩的李雅普诺夫方程。
利用数值算法联立求解李雅普诺夫微分方程和确定性常微分方程。
通过Monte Carlo模拟，验证此方法的适用性和精度。
关键词: 非平稳响应；分数阶系统；无记忆方法；统计线性化；联合激励中图分类号: O324； O322 文献标志码: A 文章编号: 1004-4523（2023）04-0923-11DOI：10.16385/ki.issn.1004-4523.2023.04.005引言分数阶微积分近几十年在工程界得到广泛的关注［1］。
分数阶微积分的一个重要工程应用是黏弹性材料的力学模型的建立。
与标准线性固体模型（Standard Linear Solid Model）相比，分数阶导数模型能以较少的参数拟合实验获得黏弹性松驰和蠕变数据［2］；此外，分数阶微分方程可很好地描述动力激励下装备黏弹性控制装置（如：天然橡胶支座［3］、黏滞阻尼器［4］和黏弹性阻尼器［5⁃6］等）的动力行为。
因此，研究这类分数阶运动方程的求解方法成为学者们关注的重点。
