GS881E36T-11.5I中文资料

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GS881E18/36T-11/11.5/100/80/66512K x 18, 256K x 36 ByteSafe™8Mb Sync Burst SRAMs100 MHz–66 MHz3.3 V V DD 3.3 V and 2.5 V I/O100-Pin TQFP Commercial TempIndustrial Temp1.10 9/2000Featuresoperation• Dual Cycle Deselect (DCD) operation• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable• 3.3 V +10%/–5% core power supply• 2.5 V or 3.3 V I/O supply• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Common data inputs and data outputs• Clock Control, registered, address, data, and control• Internal self-timed write cycle• Automatic power-down for portable applications• 100-lead TQFP packageFunctional DescriptionApplicationsThe GS881E18//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controlsand power down control (ZZ) are asynchronous inputs. Burst Burst mode, subsequent burst addresses are generated counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.DCD Pipelined ReadsThe GS881E18//36T is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.ByteSafe™ Parity FunctionsThe GS881E18/36T features ByteSafe data security functions. See detailed discussion following.Sleep ModeLow power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS881E18//36T operates on a 3.3 V power supply, and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (V DDQ) pins are used to decouple output noise from the internal circuit.-11-11.5-100-80-663-1-1-1t KQI DD4.0 ns225 mA4.0 ns225 mA4.0 ns225 mA4.5 ns200 mA5.0 ns185 mAThrough 2-1-1-1KQtCycleI DD15 ns180 mA15 ns180 mA15 ns180 mA15 ns175 mA20 ns165 mAGS881E18/36T-11/11.5/100/80/66GS881E18 100-Pin TQFP Pinout807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B1DQ B2V SS V DDQ DQ B3DQ B4FT V DD DP V SS DQ B5DQ B6V DDQ V SS DQ B7DQ B8DQ B9V SS V DDQ V DDQ V SS DQ A8DQ A7V SS V DDQ DQ A6DQ A5V SS QE V DD ZZ DQ A4DQ A3V DDQ V SS DQ A2DQ A1V SS V DDQ L B O A 5A 4A 3A 2A 1A 0T M S T D I V S SV D DT D O T C K A 10A 11A 12A 13A 14A 16A 6A 7E 1E 2 N C N C B BB AA 17C K G W B W VD DV S SG A D S C A D S P A D V A 8A 9A 15512K X 18Top ViewDQ A9A 18NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881E18/36T-11/11.5/100/80/66GS881E36 100-Pin TQFP Pinout807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C4DQ C3V SS V DDQ DQ C2DQ C1FT V DD DP V SS DQ D1DQ D2V DDQ V SS DQ D3DQ D4DQ D5V SS V DDQ V DDQ V SS DQ B4DQ B3V SS V DDQ DQ B2DQ B1V SS QE V DD ZZ DQ A1DQ A2V DDQ V SS DQ A3DQ A4V SS V DDQ L B O A 5A 4A 3A 2A 1A 0T M S T D I V S ST D O T C K A 10A 11A 12A 13A 14A 16A 6A 7E 1E 2 B DB CB BB AA 17C K G W B W VD DV S SG A D S C A D S P A D V A 8A 9A 15256K x 36Top ViewDQ B5DQ B9DQ B7DQ B8DQ B6DQ A6DQ A5DQ A8DQ A7DQ A9DQ C7DQ C8DQ C6DQ D6DQ D8DQ D7DQ D9DQ C5DQ C9100999897969594939291908988878685848382813132333435363738394041424344454647484950V D DGS881E18/36T-11/11.5/100/80/66 TQFP Pin DescriptioPin Location Symbol TypeDescription37, 36A0, A1I Address field LSBs and Address Counter preset Inputs 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,46, 47, 48, 49, 50, 92A2–A17I Address Inputs80A18I Address Inputs63, 62, 59, 58, 57, 56, 53, 52 68, 69, 72, 73, 74, 75, 78, 79 13, 12, 9, 8, 7, 6, 3, 2 18, 19, 22, 23, 24, 25, 28, 29DQ A1–DQ A8DQ B1–DQ B8DQ C1–DQ C8DQ D1–DQ D8I/O Data Input and Output pins ( x36 Version)51, 80, 1, 30DQ A9, DQ B9,DQ C9, DQ D9I/O Data Input and Output pins58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24DQ A1–DQ A9DQ B1–DQ B9I/O Data Input and Output pins51, 52, 53, 56, 5775, 78, 79,1, 2, 3, 6, 725, 28, 29, 30NC—No Connect16DP I Parity Input; 1 = Even, 0 = Odd66QE O Parity Error Out; Open Drain Output87BW I Byte Write—Writes all enabled bytes; active low93, 94B A, B B I Byte Write Enable for DQ A, DQ B Data I/Os; active low95, 96B C, B D I Byte Write Enable for DQ C, DQ D Data I/Os; active low ( x36 Version) 95, 96NC—No Connect (x18 Version)89CK I Clock Input Signal; active high88GW I Global Write Enable—Writes all bytes; active low98E1I Chip Enable; active low97E2I Chip Enable; active high86G I Output Enable; active low83ADV I Burst address counter advance enable; active low84, 85ADSP, ADSC I Address Strobe (Processor, Cache Controller); active lowGS881E18/36T-11/11.5/100/80/6664ZZ I Sleep mode control; active high 14FT I Flow Through or Pipeline mode; active low 31LBO I Linear Burst Order mode; active low38TMS I Scan Test Mode Select 39TDI I Scan Test Data In 42TDO O Scan Test Data Out 43TCK I Scan Test Clock 15, 41, 65, 91V DD I Core power supply 5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90V SS I I/O and Core Ground 4, 11, 20, 27, 54, 61, 70, 77V DDQIOutput driver power supplyPin LocationSymbolTyp eDescriptionGS881E18/36T-11/11.5/100/80/66GS881E18/36 Block DiagramA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterD QR e g i s t e rDQ RegisterA0–An LBO ADV CK ADSC ADSP GW BW B AB BB CB DFT GZZPower Down ControlMemory Array36364AQD DQx0–DQx9DPParity QEParity EncodeCompare3643636432Note: Only x36 version shown for simplicity.3636DQR e g i s t e r 4E 1E 2GS881E18/36T-11/11.5/100/80/66ByteSafe ™ Parity FunctionsThis SRAM includes a write data parity check that checks the validity of data coming into the RAM on write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode, write data errors are reported one clock cycle later. (See Write Parity Error Output Timing Diagram .) The Data Parity Mode (DP) pin must be tied high to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data. Validity is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error. Multiple Parity Error Output pins may share a common pull-up resistor.Write Parity Error Output Timing DiagramBPR 1999.05.18CK D In AD In BD In C D In D D In EtKQ tLZDQQEF l o w T h r o u g h M o d eP i p e l i n e d M o d etKQ tLZDQQED In A D In BD In CD In D D In EErr AErr AErr CErr CtHZ tKQX tHZ tKQXGS881E18/36T-11/11.5/100/80/66Note:There are pull-up devices on the LBO, DP and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.Burst Counter SequencesBPR 1999.05.18Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H or NC Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down Control ZZ L or NC Active H Standby, I DD = I SB ByteSafe Data Parity ControlDPL Check for Odd Parity H or NCCheck for Even ParityLinear Burst SequenceNote: The burst counter wraps to initial state on the 5th clock.I nterleaved Burst SequenceNote: The burst counter wraps to initial state on the 5th clock.A[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110A[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100GS881E18/36T-11/11.5/100/80/66Byte Write Truth TableNotes:1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C, and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x36 version.FunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytes H L L L L L 2, 3, 4Write all bytesLXXXXXGS881E18/36T-11/11.5/100/80/66 Synchronous Truth TableOperation AddressUsedStateDiagramKey5E1E22(x36only)ADSP ADSC ADV W3DQ4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend Burst Current H X X H H T D Notes:1.X = Don’t Care, H = High, L = Low.2.For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0.3.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS881E18/36T-11/11.5/100/80/66First WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWX XWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRSimplified State DiagramNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (B A , B B , B C , B D , BW, and GW) controlinputs, and that ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS881E18/36T-11/11.5/100/80/66First WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWSimplified State Diagram with GNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.3.Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS881E18/36T-11/11.5/100/80/66Note:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.Notes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both2.75 V ≤ V DDQ ≤ 2.375 V(i.e., 2.5 V I/O) and 3.6 V ≤ V DDQ ≤ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2.This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers.3.Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number ofIndustrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device.4.Input Under/overshoot voltage must be –2 V > Vi < V DD +2 V with a pulse width not to exceed 20% tKC.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V CK Voltage on Clock Input Pin –0.5 to 6V V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CRecommended Operating ConditionsParameterSymbolMin.Typ.Max.UnitNotesSupply Voltage V DD 3.135 3.3 3.6V I/O Supply Voltage V DDQ 2.375 2.5V DD V 1Input High Voltage V IH 1.7—V DD +0.3V 2Input Low VoltageV IL –0.3—0.8V 2Ambient Temperature (Commercial Range Versions)T A 02570°C 3Ambient Temperature (Industrial Range Versions)T A–402585°C3GS881E18/36T-11/11.5/100/80/66Note: These parameters are sample tested.Notes:1.Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-ature air flow, board density, and PCB thermal resistance.2.SCMI G-38-873.Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1Capacitance(T A = 25o C, f = 1 MH Z , V DD = 3.3 V)ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output CapacitanceC I/OV OUT = 0 V67pFPackage Thermal CharacteristicsRatingLayer BoardSymbolMaxUnitNotesJunction to Ambient (at 200 lfm)single R ΘJA 40°C/W 1,2Junction to Ambient (at 200 lfm)four R ΘJA 24°C/W 1,2Junction to Case (TOP)—R ΘJC9°C/W320% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILGS881E18/36T-11/11.5/100/80/66Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.3.Output Load 2 for t LZ , t HZ , t OLZ and t OHZ4.Device is deselected as defined by the Truth Table.AC Test ConditionsParameterConditionsInput high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level1.25 V Output loadFig. 1& 2DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I INZZ V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH –1 uA –1 uA 1 uA 300 uA Mode Pin Input Current I INM V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –300 uA –1 uA 1 uA 1 uA Output Leakage Current I OL Output Disable,V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH I OH = –8 mA, V DDQ = 3.135 V2.4 V —Output Low VoltageV OLI OL = 8 mA—0.4 VDQVT = 1.25 V50Ω30pF *DQ2.5 VOutput Load 1Output Load 2225Ω225Ω5pF ** Distributed Test Jig CapacitanceGS881E18/36T-11/11.5/100/80/66 Operating CurrentsParameter Test Conditions Symbol-11-11.5-100-80-66Unit 0to70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°Cto70°C–40to85°COperating Current Device Selected;All other inputs≥V IH o r ≤ V ILOutput openI DDPipeline225235225235225235200210185195mAI DDFlow-Thru180 190 180 190 180190175185165175mAStandbyCurrent ZZ≥ V DD- 0.2VI SBPipeline30 40 30 40 304030403040mAI SBFlow-Thru30 40 30 40304030403040mADeselect Current Device Deselected;All other inputs≥ V IH or≤ V ILI DDPipeline80 90 80 90809070806070mAI DDFlow-Thru65 75 65 75657555655060mAGS881E18/36T-11/11.5/100/80/66AC Electrical CharacteristicsNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.Parameter Symbol -11-11.5-100-80-66Unit Min Max MinMax MinMax Min Max Min Max PipelineClock Cycle TimetKC 10—10—10—12.5—15—ns Clock to Output Valid tKQ — 4.0— 4.0— 4.0— 4.5—5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Flow-ThruClock Cycle TimetKC 15.0—15.0—15.0—15.0—20—ns Clock to Output Valid tKQ —11.0—11.5—12.0—14.0—18ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock HIGH Time tKH 1.7— 1.7—2—2— 2.3—ns Clock LOW Time tKL 2—2— 2.2— 2.2— 2.5—ns Clock to Output in High-Z tHZ 1 1.5 4.0 1.5 4.2 1.5 4.5 1.5 4.5 1.5 4.8ns G to Output Valid tOE — 4.0— 4.2— 4.5— 4.5— 4.8ns G to output in Low-Z tOLZ 10—0—0—0—0—ns G to output in High-ZtOHZ 1— 4.0— 4.2— 4.5— 4.5— 4.8ns Setup time tS 1.5— 2.0— 2.0— 2.0— 2.0—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS881E18/36T-11/11.5/100/80/66CKADSPADSCADVGWBWWR2WR3WR1WR1WR2WR3tKCSingle WriteBurst Write t KLt KH tS tHtS tHtS tHtS tHtS tHtStHtS tHWrite specified byte for 2A and all bytes for 2B , 2C & 2DADV must be inactive for ADSP WriteADSC initiated writeADSP is blocked by E inactiveA 0–A nB A –B DDQ A –DQ DWrite DeselectedWR1WR3Write Cycle TimingE 1tS tHE 2 only sampled with ADSP or ADSCE 1 masks ADSPDeselected with E 2GtS tHD2AD2BD2CD2DD3AD1AHi-ZtS tHE 2GS881E18/36T-11/11.5/100/80/66Q1AQ3AQ2DQ2cQ2BQ2AtKQtLZtOEtOHZtOLZtKQXtHZtKQXCKADSP ADSCBW GGWADVBurst ReadRD2RD3tKLtStHtHtS tHtS tHADSC initiated readSuspend Burst Single ReadADSP is blocked by E inactiveA 0–A nB A –B DtKHtKCtS tHtS tStHDQ A –DQ DRD1Hi-ZSuspend BurstFlow Through Read Cycle TimingtHtHE 1 masks ADSPDeselected with E 2E 1tS tS E 2E 2 only sampled with ADSP or ADSCGS881E18/36T-11/11.5/100/80/66Flow Through Read-Write Cycle TimingCKADSPADVGWBWGQ1AD1AQ2AQ2BQ2cQ2DSingle ReadBurst ReadtOEtOHZtS tHtStHtHtS tHtS tHtKH DQ A –DQ DB A –B DtKLtKCtS Single WriteADSP is blocked by E inactivetKQtStHHi-ZQ2ABurst wrap around to it’s initial stateWR1E 1tS tS tHE 1 masks ADSPE 2 only sampled with ADSP and ADSCtHADSCtS tHADSC initiated readRD1WR1RD2tS tHA 0–A nE 2GS881E18/36T-11/11.5/100/80/66Pipelined DCD Read Cycle TimingQ1AQ3AQ2DQ2cQ2BQ2AtKQtLZtOEtOHZtOLZtKQX tHZtKQX CKADSP ADSCBW GGWADVBurst ReadRD2RD3tKLtHtHtStHtHtS tHtS tHADSC initiated readSuspend BurstE 1 masks ADSPE 2 only sampled with ADSP or ADSCSingle ReadADSP is blocked by E 1 inactiveA 0–A nB A –B DE 1tKH tKCtS tHtS tStHDQ A –DQ DtS tS RD1Hi-ZE 2GS881E18/36T-11/11.5/100/80/66Pipelined DCD Read-Write Cycle TimingCKADSPADVGWBW E 1GWR1Q1AD1aQ2A Q2B Q2c Q2DSingle ReadBurst ReadtOEtOHZtS tStHtStH tStHtHtS tHtS tHtKHE 1 masks ADSPE 2 only sampled with ADSP and ADSCDQ A –DQ DtKLtKC tS tHSingle WriteADSP is blocked by E 1 inactivetKQtS tHHi-ZB A –B DADSCtS tHADSC initiated readRD1WR1RD2tS tHA 0–A nE 2GS881E18/36T-11/11.5/100/80/66Application TipsSingle and Dual Cycle DeselectSCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the outputdrivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings) but greater care must be exercised to avoid excessive bus contention.JTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner consistent with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG), but does not implement all of the functions required for 1149.1 compliance. Some functions have been modified or eliminated because they can slow the RAM. Nevertheless, the RAM supports 1149.1-1990 TAP (Test Access Port) Controller architecture, and can be expected to function in a manner that does not conflict with the operation of Standard 1149.1 compliant devices. The JTAG Port interfaces with conventional TTL / CMOS logic level signaling.Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unlessclocked. TCK, TDI, and TMS are designed with internal pull-up circuits. To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.CKADSP ADSCtHtKH tKLtKCtS ZZtZZRtZZHtZZS~~~~~~~~~SnoozeSleep Mode Timing DiagramGS881E18/36T-11/11.5/100/80/66JTAG Port RegistersOverviewThe various JTAG registers, refered to as TAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on the next falling edge of TCK. When a register is selected it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterBoundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. TheBoundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. Two TAP instructions can be used to activate the Boundary Scan Register.JTAG Pin Descriptions PinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data Out OutOutput that is active depending on the state of the TAP state machine. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO.Note:This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.。

6EGG8-2;1EHG1-2;1EGS1-1;1EGS1-2;3EGG8-2;中文规格书,Datasheet资料

166
Available Part Numbers
Filtered modules 1EGG1-1 3EGG1-1 6EGG1-1 10EGG1-1 1EGG1-2 3EGG1-2 6EGG1-2 10EGG1-2 1EGG8-1 3EGG8-1 6EGG8-1 10EGG8-1 1EGG8-2 3EGG8-2 6EGG8-2 10EGG8-2 1EGS1-1 3EGS1-1 6EGS1-1 10EGS1-1 1EGS1-2 3EGS1-2 6EGS1-2 10EGS1-2 Filtered modules with ground circuit inductor 1EGG1C-1 3EGG1C-1 6EGG1C-1 1EGG1C-2 3EGG1C-2 6EGG1C-2 1EGG8C-1 3EGG8C-1 6EGG8C-1 1EGG8C-2 3EGG8C-2 6EGG8C-2 Medical ﬁlter modules 1EHG1-2 3EHG1-2 6EHG1-2 10EHG1-2 1EHG8-2 3EHG8-2 6EHG8-2 10EHG8-2 1EHGS1-2 3EHGS1-2 6EHGS1-2 10EHGS1-2
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Corcom Product Guide
Catalog: 1654001 Issue Date: 06.2011
Smallest Power Entry Module with Metric Fuse Holders (continued)
(not included)
HG Series
• Medical version of our GG Series • Mechanically identical to GG Series • Available only with dual fusing

MAX13085EESA-T中文资料

General DescriptionThe MAX13080E–MAX13089E +5.0V, ±15kV ESD-protect-ed, RS-485/RS-422 transceivers feature one driver and one receiver. These devices include fail-safe circuitry,guaranteeing a logic-high receiver output when receiver inputs are open or shorted. The receiver outputs a logic-high if all transmitters on a terminated bus are disabled (high impedance). The MAX13080E–MAX13089E include a hot-swap capability to eliminate false transitions on the bus during power-up or hot insertion.The MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. The MAX13083E/MAX13084E/MAX13085E also feature slew-rate-limited drivers but allow transmit speeds up to 500kbps. The MAX13086E/MAX13087E/MAX13088E driver slew rates are not limited, making transmit speeds up to 16Mbps possible. The MAX13089E slew rate is pin selectable for 250kbps,500kbps, and 16Mbps.The MAX13082E/MAX13085E/MAX13088E are intended for half-duplex communications, and the MAX13080E/MAX13081E/MAX13083E/MAX13084E/MAX13086E/MAX13087E are intended for full-duplex communica-tions. The MAX13089E is selectable for half-duplex or full-duplex operation. It also features independently programmable receiver and transmitter output phase through separate pins.The MAX13080E–MAX13089E transceivers draw 1.2mA of supply current when unloaded or when fully loaded with the drivers disabled. All devices have a 1/8-unit load receiver input impedance, allowing up to 256transceivers on the bus.The MAX13080E/MAX13083E/MAX13086E/MAX13089E are available in 14-pin PDIP and 14-pin SO packages.The MAX13081E/MAX13082E/MAX13084E/MAX13085E/MAX13087E/MAX13088E are available in 8-pin PDIP and 8-pin SO packages. The devices operate over the com-mercial, extended, and automotive temperature ranges.ApplicationsUtility Meters Lighting Systems Industrial Control Telecom Security Systems Instrumentation ProfibusFeatures♦+5.0V Operation♦Extended ESD Protection for RS-485/RS-422 I/O Pins±15kV Human Body Model ♦True Fail-Safe Receiver While Maintaining EIA/TIA-485 Compatibility ♦Hot-Swap Input Structures on DE and RE ♦Enhanced Slew-Rate Limiting Facilitates Error-Free Data Transmission(MAX13080E–MAX13085E/MAX13089E)♦Low-Current Shutdown Mode (Except MAX13081E/MAX13084E/MAX13087E)♦Pin-Selectable Full-/Half-Duplex Operation (MAX13089E)♦Phase Controls to Correct for Twisted-Pair Reversal (MAX13089E)♦Allow Up to 256 Transceivers on the Bus ♦Available in Industry-Standard 8-Pin SO PackageMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers________________________________________________________________Maxim Integrated Products 1Ordering Information19-3590; Rev 1; 4/05For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Selector Guide, Pin Configurations, and Typical Operating Circuits appear at end of data sheet.Ordering Information continued at end of data sheet.M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.) (Note 1)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.(All Voltages Referenced to GND)Supply Voltage (V CC ).............................................................+6V Control Input Voltage (RE , DE, SLR,H/F , TXP, RXP)......................................................-0.3V to +6V Driver Input Voltage (DI)...........................................-0.3V to +6V Driver Output Voltage (Z, Y, A, B).............................-8V to +13V Receiver Input Voltage (A, B)....................................-8V to +13V Receiver Input VoltageFull Duplex (A, B)..................................................-8V to +13V Receiver Output Voltage (RO)....................-0.3V to (V CC + 0.3V)Driver Output Current.....................................................±250mAContinuous Power Dissipation (T A = +70°C)8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C).....727mW 14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 14-Pin Plastic DIP (derate 10.0mW/°C above +70°C)...800mW Operating Temperature RangesMAX1308_EC_ _.................................................0°C to +75°C MAX1308_EE_ _..............................................-40°C to +85°C MAX1308_EA_ _............................................-40°C to +125°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS (continued)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.) (Note 1)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 4_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICSMAX13080E/MAX13081E/MAX13082E/MAX13089E WITH SRL = UNCONNECTED (250kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13080E/MAX13081E/MAX13082E/MAX13089E WITH SRL = UNCONNECTED (250kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________5DRIVER SWITCHING CHARACTERISTICSMAX13083E/MAX13084E/MAX13085E/MAX13089E WITH SRL = V CC (500kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13083E/MAX13084E/MAX13085E/MAX13089E WITH SRL = V CC (500kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 6_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICSMAX13086E/MAX13087E/MAX13088E/MAX13089E WITH SRL = GND (16Mbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13086E/MAX13087E/MAX13088E/MAX13089E WITH SRL = GND (16Mbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)Note 2:∆V OD and ∆V OC are the changes in V OD and V OC , respectively, when the DI input changes state.Note 3:The short-circuit output current applies to peak current just prior to foldback current limiting. The short-circuit foldback outputcurrent applies during current limiting to allow a recovery from bus contention.MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________70.800.901.501.101.001.201.301.401.60-40-10520-253550958011065125SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )0201040305060021345OUTPUT CURRENTvs. RECEIVER OUTPUT-HIGH VOLTAGEM A X 13080E -89E t o c 02OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )20104030605070021345OUTPUT CURRENTvs. RECEIVER OUTPUT-LOW VOLTAGEM A X 13080E -89E t o c 03OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )4.04.44.24.84.65.25.05.4RECEIVER OUTPUT-HIGH VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T H I G H V O L T A G E (V )-40-10520-2535509580110651250.10.70.30.20.40.50.60.8RECEIVER OUTPUT-LOW VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T L O W V O L T A G E (V )-40-10520-25355095801106512502040608010012014016012345DRIVER DIFFERENTIAL OUTPUT CURRENT vs. DIFFERENTIAL OUTPUT VOLTAGEDIFFERENTIAL OUTPUT VOLTAGE (V)D I F FE R E N T I A L O U T P U T C U R R E N T (m A )2.02.82.43.63.24.44.04.8DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURED I F FE R E N T I A L O U T P U T V O L T A G E (V )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140180160200-7-5-4-6-3-2-1012354OUTPUT CURRENT vs. TRANSMITTEROUTPUT-HIGH VOLTAGEOUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )60402080100120140160180200042681012OUTPUT CURRENT vs. TRANSMITTEROUTPUT-LOW VOLTAGEOUTPUT-LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )Typical Operating Characteristics(V CC = +5.0V, T A = +25°C, unless otherwise noted.)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 8_______________________________________________________________________________________21543679810SHUTDOWN CURRENT vs. TEMPERATUREM A X 13080E -89E t o c 10S H U T D O W N C U R R E N T (µA )-40-10520-253550958011065125TEMPERATURE (°C)600800700100090011001200DRIVER PROPAGATION DELAY vs. TEMPERATURE (250kbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)300400350500450550600DRIVER PROPAGATION DELAY vs. TEMPERATURE (500kbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)1070302040506080DRIVER PROPAGATION DELAY vs. TEMPERATURE (16Mbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140160180RECEIVER PROPAGATION DELAYvs. TEMPERATURE (250kpbs AND 500kbps)R E C E I V E R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140160180RECEIVER PROPAGATION DELAYvs. TEMPERATURE (16Mbps)R EC E I V E R P R O P A G AT I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)2µs/div DRIVER PROPAGATION DELAY (250kbps)DI 2V/divV Y - V Z 5V/divR L = 100Ω200ns/divRECEIVER PROPAGATION DELAY(250kbps AND 500kbps)V A - V B 5V/divRO 2V/divTypical Operating Characteristics (continued)(V CC = +5.0V, T A = +25°C, unless otherwise noted.)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________9Test Circuits and Waveforms400ns/divDRIVER PROPAGATION DELAY (500kbps)DI 2V/divR L = 100ΩV Y - V Z 5V/div10ns/div DRIVER PROPAGATION DELAY (16Mbps)DI 2V/divR L = 100ΩV Y 2V/divV Z 2V/div40ns/divRECEIVER PROPAGATION DELAY (16Mbps)V B 2V/divR L = 100ΩRO 2V/divV A 2V/divTypical Operating Characteristics (continued)(V CC = +5.0V, T A = +25°C, unless otherwise noted.)Figure 2. Driver Timing Test CircuitM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 10______________________________________________________________________________________Test Circuits and Waveforms (continued)Figure 4. Driver Enable and Disable Times (t DHZ , t DZH , t DZH(SHDN))DZL DLZ DLZ(SHDN)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversTest Circuits and Waveforms (continued)Figure 6. Receiver Propagation Delay Test CircuitM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E/MAX13083E/MAX13086EMAX13081E/MAX13084E/MAX13086E/MAX13087EFunction TablesM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers MAX13082E/MAX13085E/MAX13088EFunction Tables (continued)MAX13089EDetailed Description The MAX13080E–MAX13089E high-speed transceivers for RS-485/RS-422 communication contain one driver and one receiver. These devices feature fail-safe circuit-ry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to a terminated transmission line with all dri-vers disabled (see the Fail-Safe section). The MAX13080E/MAX13082E/MAX13083E/MAX13085E/ MAX13086E/MAX13088E/MAX13089E also feature a hot-swap capability allowing line insertion without erroneous data transfer (see the Hot Swap Capability section). The MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflec-tions caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. The MAX13083E/MAX13084E/MAX13085E also offer slew-rate limits allowing transmit speeds up to 500kbps. The MAX13086E/MAX13087E/MAX13088Es’ driver slew rates are not limited, making transmit speeds up to 16Mbps possible. The MAX13089E’s slew rate is selectable between 250kbps, 500kbps, and 16Mbps by driving a selector pin with a three-state driver.The MAX13082E/MAX13085E/MAX13088E are half-duplex transceivers, while the MAX13080E/MAX13081E/ MAX13083E/MAX13084E/MAX13086E/MAX13087E are full-duplex transceivers. The MAX13089E is selectable between half- and full-duplex communication by driving a selector pin (H/F) high or low, respectively.All devices operate from a single +5.0V supply. Drivers are output short-circuit current limited. Thermal-shutdown circuitry protects drivers against excessive power dissi-pation. When activated, the thermal-shutdown circuitry places the driver outputs into a high-impedance state.Receiver Input Filtering The receivers of the MAX13080E–MAX13085E, and the MAX13089E when operating in 250kbps or 500kbps mode, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 25% due to this filtering.Fail-Safe The MAX13080E family guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver input threshold between -50mV and -200mV. If the differential receiver input voltage (A - B) is greater than or equal to -50mV, RO is logic-high. If (A - B) is less than or equal to -200mV, RO is logic-low. In the case of a terminated bus with all transmitters disabled, the receiv-er’s differential input voltage is pulled to 0V by the termi-nation. With the receiver thresholds of the MAX13080E family, this results in a logic-high with a 50mV minimumnoise margin. Unlike previous fail-safe devices, the-50mV to -200mV threshold complies with the ±200mVEIA/TIA-485 standard.Hot-Swap Capability (Except MAX13081E/MAX13084E/MAX13087E)Hot-Swap InputsWhen circuit boards are inserted into a hot or powered backplane, differential disturbances to the data buscan lead to data errors. Upon initial circuit board inser-tion, the data communication processor undergoes itsown power-up sequence. During this period, the processor’s logic-output drivers are high impedanceand are unable to drive the DE and RE inputs of these devices to a defined logic level. Leakage currents up to±10µA from the high-impedance state of the proces-sor’s logic drivers could cause standard CMOS enableinputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance couldcause coupling of V CC or GND to the enable inputs. Without the hot-swap capability, these factors could improperly enable the transceiver’s driver or receiver.When V CC rises, an internal pulldown circuit holds DElow and RE high. After the initial power-up sequence,the pulldown circuit becomes transparent, resetting thehot-swap tolerable input.Hot-Swap Input CircuitryThe enable inputs feature hot-swap capability. At theinput there are two NMOS devices, M1 and M2 (Figure 9). When V CC ramps from zero, an internal 7µstimer turns on M2 and sets the SR latch, which alsoturns on M1. Transistors M2, a 1.5mA current sink, andM1, a 500µA current sink, pull DE to GND through a5kΩresistor. M2 is designed to pull DE to the disabledstate against an external parasitic capacitance up to100pF that can drive DE high. After 7µs, the timer deactivates M2 while M1 remains on, holding DE low against three-state leakages that can drive DE high. M1 remains on until an external source overcomes the required input current. At this time, the SR latch resetsand M1 turns off. When M1 turns off, DE reverts to a standard, high-impedance CMOS input. Whenever V CCdrops below 1V, the hot-swap input is reset.For RE there is a complementary circuit employing two PMOS devices pulling RE to V CC. MAX13080E–MAX13089E+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversM A X 13080E –M A X 13089EMAX13089E ProgrammingThe MAX13089E has several programmable operating modes. Transmitter rise and fall times are programma-ble, resulting in maximum data rates of 250kbps,500kbps, and 16Mbps. To select the desired data rate,drive SRL to one of three possible states by using a three-state driver: V CC , GND, or unconnected. F or 250kbps operation, set the three-state device in high-impedance mode or leave SRL unconnected. F or 500kbps operation, drive SRL high or connect it to V CC .F or 16Mbps operation, drive SRL low or connect it to GND. SRL can be changed during operation without interrupting data communications.Occasionally, twisted-pair lines are connected backward from normal orientation. The MAX13089E has two pins that invert the phase of the driver and the receiver to cor-rect this problem. F or normal operation, drive TXP and RXP low, connect them to ground, or leave them uncon-nected (internal pulldown). To invert the driver phase,drive TXP high or connect it to V CC . To invert the receiver phase, drive RXP high or connect it to V CC . Note that the receiver threshold is positive when RXP is high.The MAX13089E can operate in full- or half-duplex mode. Drive H/F low, leave it unconnected (internal pulldown), or connect it to GND for full-duplex opera-tion. Drive H/F high for half-duplex operation. In full-duplex mode, the pin configuration of the driver and receiver is the same as that of a MAX13080E. In half-duplex mode, the receiver inputs are internally connect-ed to the driver outputs through a resistor-divider. This effectively changes the function of the device’s outputs.Y becomes the noninverting driver output and receiver input, Z becomes the inverting driver output and receiver input. In half-duplex mode, A and B are still connected to ground through an internal resistor-divider but they are not internally connected to the receiver.±15kV ESD ProtectionAs with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electro-static discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX13080E family of devices have extra protection against static electricity. Maxim’s engineers have devel-oped state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD struc-tures withstand high ESD in all states: normal operation,shutdown, and powered down. After an ESD event, the MAX13080E–MAX13089E keep working without latchup or damage.ESD protection can be tested in various ways. The transmitter outputs and receiver inputs of the MAX13080E–MAX13089E are characterized for protec-tion to the following limits:•±15kV using the Human Body Model•±6kV using the Contact Discharge method specified in IEC 61000-4-2ESD Test ConditionsESD performance depends on a variety of conditions.Contact Maxim for a reliability report that documents test setup, test methodology, and test results.Human Body ModelFigure 10a shows the Human Body Model, and Figure 10b shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest,which is then discharged into the test device through a 1.5k Ωresistor.IEC 61000-4-2The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX13080E family of devices helps you design equip-ment to meet IEC 61000-4-2, without the need for addi-tional ESD-protection components.+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversThe major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD with-stand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 10c shows the IEC 61000-4-2 model, and Figure 10d shows the current waveform for IEC 61000-4-2 ESD Contact Discharge test.Machine Model The machine model for ESD tests all pins using a 200pF storage capacitor and zero discharge resis-tance. The objective is to emulate the stress caused when I/O pins are contacted by handling equipment during test and assembly. Of course, all pins require this protection, not just RS-485 inputs and outputs.Applications Information256 Transceivers on the BusThe standard RS-485 receiver input impedance is 12kΩ(1-unit load), and the standard driver can drive up to 32-unit loads. The MAX13080E family of transceivers has a1/8-unit load receiver input impedance (96kΩ), allowingup to 256 transceivers to be connected in parallel on one communication line. Any combination of these devices,as well as other RS-485 transceivers with a total of 32-unit loads or fewer, can be connected to the line.Reduced EMI and ReflectionsThe MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to250kbps. The MAX13083E/MAX13084E/MAX13085Eoffer higher driver output slew-rate limits, allowing transmit speeds up to 500kbps. The MAX13089E withSRL = V CC or unconnected are slew-rate limited. WithSRL unconnected, the MAX13089E error-free data transmission is up to 250kbps. With SRL connected toV CC,the data transmit speeds up to 500kbps. MAX13080E–MAX13089E+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversM A X 13080E –M A X 13089ELow-Power Shutdown Mode (Except MAX13081E/MAX13084E/MAX13087E)Low-power shutdown mode is initiated by bringing both RE high and DE low. In shutdown, the devices typically draw only 2.8µA of supply current.RE and DE can be driven simultaneously; the devices are guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 700ns, the devices are guaranteed to enter shutdown.Enable times t ZH and t ZL (see the Switching Characteristics section) assume the devices were not in a low-power shutdown state. Enable times t ZH(SHDN)and t ZL(SHDN)assume the devices were in shutdown state. It takes drivers and receivers longer to become enabled from low-power shutdown mode (t ZH(SHDN), t ZL(SHDN))than from driver/receiver-disable mode (t ZH , t ZL ).Driver Output ProtectionTwo mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention.The first, a foldback current limit on the output stage,provides immediate protection against short circuits over the whole common-mode voltage range (see the Typical Operating Characteristics ). The second, a thermal-shut-down circuit, forces the driver outputs into a high-imped-ance state if the die temperature exceeds +175°C (typ).Line LengthThe RS-485/RS-422 standard covers line lengths up to 4000ft. F or line lengths greater than 4000ft, use the repeater application shown in Figure 11.Typical ApplicationsThe MAX13082E/MAX13085E/MAX13088E/MAX13089E transceivers are designed for bidirectional data commu-nications on multipoint bus transmission lines. F igures 12 and 13 show typical network applications circuits. To minimize reflections, terminate the line at both ends in its characteristic impedance, and keep stub lengths off the main line as short as possible. The slew-rate-lim-ited MAX13082E/MAX13085E and the two modes of the MAX13089E are more tolerant of imperfect termination.Chip InformationTRANSISTOR COUNT: 1228PROCESS: BiCMOS+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversFigure 11. Line Repeater for MAX13080E/MAX13081E/MAX13083E/MAX13084E/MAX13086E/MAX13087E/MAX13089E in Full-Duplex Mode+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E–MAX13089EM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversPin Configurations and Typical Operating CircuitsMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers______________________________________________________________________________________21Pin Configurations and Typical Operating Circuits (continued)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 22______________________________________________________________________________________Ordering Information (continued)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers______________________________________________________________________________________23Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)。

GS841E18AGT-180中文资料

GS841E18AT/B-180/166/150/130/100256K x 18 Sync Cache Tag 180 MHz–100 MHz3.3 V V DD3.3 V and 2.5 V I/OTQFP, BGACommercial Temp Industrial Temp Features• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O supply• Dual Cycle Deselect (DCD)• Intergrated data comparator for Tag RAM application • FT mode pin for flow through or pipeline operation• LBO pin for Linear or Interleave (Pentium TM and X86) Burst mode• Synchronous address, data I/O, and control inputs • Synchronous Data Enable (DE)• Asynchronous Output Enable (OE)• Asynchronous Match Output Enable (MOE)• Byte Write (BWE) and Global Write (GW) operation • Three chip enable signals for easy depth expansion • Internal self-timed write cycle• JTAG Test mode conforms to IEEE standard 1149.1• JEDEC-standard 100-lead TQFP package and 119-BGA • Pb-Free 100-lead TQFP package availableFunctional DescriptionThe GS841E18A is a 256K x 18 high performance synchronous DCD SRAM with integrated Tag RAM comparator. A 2-bit burst counter is included to provide burst interface with Pentium TM and other high performance CPUs. It is designed to be used as a Cache Tag SRAM, as well as data SRAM. Addresses, data IOs, match output, chip enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC, ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are synchronous and are controlled by a positive-edge-triggered clock (CLK).Output Enable (OE), Match Output Enable, and power down control (ZZ) are asynchronous. Burst can be initiated with either ADSP or ADSC inputs. Subsequent burst addresses are generated internally and are controlled by ADV. The burst sequence is either interleave order (Pentium TM or x86) or linear order, and is controlled by LBO.Output registers and the Match output register are provided andcontrolled by the FT mode pin (Pin 14). Through use of the FT mode pin, I/O registers can be programmed to perform pipeline or flow through operation. Flow Through mode reduces latency.Byte write operation is performed by using Byte Write Enable (BWE) input combined with two individual byte write signals BW1-2. In addition, Global Write (GW) is available for writing all bytes at one time.Compare cycles begin as a read cycle with output disabled so that compare data can be loaded into the data input register. Thecomparator compares the read data with the registered input data and a match signal is generated. The match output can be either in Pipeline or Flow Through modes controlled by the FT signal.Low power (Standby mode) is attained through the assertion of the ZZ signal, or by stopping the clock (CLK). Memory data is retained during Standby mode.JTAG boundary scan interface is provided using IEEE standard 1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to perform JTAG function.The GS841E18A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output (V DDQ ) pins are used to allow both 3.3 V or 2.5 V IO interface.Dual Cycle Deselect (DCD)The GS841E18A is a DCD pipelines synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD SRAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of the clock.Parameter Synopsis–180-166-150-133-100Pipeline 3-1-1-1t cycle t KQ I DD 5.5 ns 3.2 ns 335 mA 6.0 ns 3.5 ns 310 mA 6.6 ns 3.8 ns 275 mA 7.5 ns 4.0 ns 250 mA 10 ns 4.5 ns 190 mA Flow Through 2-1-1-1t KQ t cycle I DD8 ns 9.1 ns 210 mA8.5 ns 10 ns 190 mA10 ns 10 ns 190 mA11 ns 15 ns 140 mA12 ns 15 ns 140 mAGS841E18AT/B-180/166/150/130/100Pin Configuration (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS D DQ V SS V DDQ DQ DQ V DD NC V SS DQ DQ V DDQ V SS DQ DQ DQ P V SS V DDQ V DDQ V SS DQ DQ V SS VDDQ DQ DQ V SS NC V DD ZZ DQ DQ V DDQ V SS DQ DQ V SS V DDQL B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A C E 1C E 2 N C N C B W 2B W 1C E 3C L K G W B W E VD DV S SO E A D S C A D S P A D V A AA 256K x 18Top View DQ P A NC NC NC NC NC DE MATCHMOENC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FTGS841E18AT/B-180/166/150/130/100 GS841E18A PadOut—119-Bump BGA—Top View (Package B)1234567A V DDQ A A ADSP A A V DDQB NC E2A ADSC A E3NCC NC A A V DD A A NCD DQ B NC V SS NC V SS DQ P NCE NC DQ B V SS E1V SS NC DQ AF V DDQ NC V SSG V SS DQ A V DDQG NC D Q B B B ADV NC NC DQ AH DQ B N C V SS GW V SS DQ A NCJ V DDQ V DD NC V DD NC V DD V DDQK NC DQ B V SS CK V SS NC DQ AL DQ B NC NC NC B A DQ A NCM V DDQ DQ B V SS BW V SS MATCH V DDQN DQ B NC V SS A1V SS DQ A DEP NC DQ P V SS A0V SS MOE DQ AR NC A LBO V DD FT A NCT NC A A NC A A ZZU V DDQ TMS TDI TCK TDO NC V DDQGS841E18AT/B-180/166/150/130/100TQFP Pin DescriptionSymbol DescriptionAn Address Input Signals—Inputs are registered and must meet setup and hold times, as specified onpage 11.CLK Clock Input SignalBWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the fourbyte write signals for a write operation to occur.BW1Byte Write signal for data outputs 1 thru 8BW2Byte Write signal for data outputs 9 thru 16GW Global Write EnableCE1,CE2, CE3Chip EnablesOE Output EnableADV Burst address advanceADSP, ADSC Address status signalsDQ Data Input and Output pinsDQP Parity Input and Output pinsMATCH Match OutputMOE Match Output EnableDE Data Enable—Data input registers are updated only when DE is active.ZZ Power down control—Application of ZZ will result in a low standby power consumption.FT Flow Through or Pipeline modeLBO Linear Order Burst modeTMS Test Mode SelectTDI Test Data InTDO Test Data OutTCK Test ClockV DD 3.3 V power supplyV SS GroundV DDQ 2.5 V/3.3 V output power supplyNC No ConnectGS841E18AT/B-180/166/150/130/100PBGA Pin DescriptionSymbol DescriptionAn Address Input Signals—Inputs are registered and must meet setup and hold times, as specified onpage 11.CLK Clock Input SignalBWE Byte Write Enable Signal—The byte write enable signal needs to be combined with one of the fourbyte write signals for a write operation to occur.BW1Byte Write signal for data outputs 1 thru 8BW2Byte Write signal for data outputs 9 thru 16GW Global Write EnableCE1,CE2, CE3Chip EnablesOE Output EnableADV Burst address advanceADSP, ADSC Address status signalsDQ Data Input and Output pinsDQP Parity Input and Output pinsMATCH Match OutputMOE Match Output EnableDE Data Enable—Data input registers are updated only when DE is active.ZZ Power down control—Application of ZZ will result in a low standby power consumption.FT Flow Through or Pipeline modeLBO Linear Order Burst modeTMS Test Mode SelectTDI Test Data InTDO Test Data OutTCK Test ClockV DD 3.3 V power supplyV SS GroundV DDQ 2.5 V/3.3 V output power supplyNC No ConnectGS841E18AT/B-180/166/150/130/100Functional Block DiagramA1A0A0A1D0D1Q1Q0B INARY C OUNTERLoadD QR EGISTE RD QRegister D QRegister D QRegister D QRegister D QRegister DQRegisterDQRegisterA0-17LBO ADV CLK ADSC ADSPGW BWE BW1BW2CE1CE2CE3FTDQ1-16OE ZZPowerdown Control256K X 18Memory Array18181818218AQDDQP1-2DEDQRegisterMatchTAP ControllerInstruction Reg.ID Reg.Bypass Reg Boundary Scan Registers 54TCKTMS TDIA, DQ, ControlTDOMOE always (Ø)GS841E18AT/B-180/166/150/130/100Mode Pin FunctionLBOFunctionL Linear Burst H or NCInterleaved BurstFTFunctionL Flow Through H or NCPipelinePower Down ControlNote:There are pull up devices on LBO and FT pins and pull down device on ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables.ZZFunctionL or NC Active HStandby, IDD = ISBLinear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Note: H = logic high, L = logic low, NC = no connectByte Write FunctionFunctionGWBWEBW1BW2Read H H X X Read H L H H Write all bytes L X X X Write all bytes H L L L Write byte 1H L L H Write byte 2HLHLGS841E18AT/B-180/166/150/130/100Notes:1.X means “don’t care,” H means “logic high,” L means “logic low.”2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.3.All inputs, except OE, must meet setup and hold on rising edge of CLK.4.Suspending busrt generates a wait cycle.5.ADSP LOW along with SRAM being selected always initiates a Read cycle at the L-H edge of the clock (CLK).6.A Write cycle can only be performed by setting Write low for the clock L-H edge of the subsequent wait cycle. Refer to page 12 for the Write timing diagram.Synchronous Truth TableOperationAddress UsedCE1CE2CE3ADSP ADSC ADV Write OE CLK DQ Deselect Cycle, Power Down none H X X X L X X X L-H High-Z Deselect Cycle, Power Down none L L X L X X X X L-H High-Z Deselect Cycle, Power Down none L X H L X X X X L-H High-Z Deselect Cycle, Power Down none L L X H L X X X L-H High-Z Deselect Cycle, Power Down none L X H H L X X X L-H High-Z Read Cycle, Begin Burst external L H L L X X X L L-H Q Read Cycle, Begin Burst external L H L L X X X H L-H High-Z Read Cycle, Begin Burst external L H L H L X H L L-H Q Read Cycle, Begin Burst external L H L H L X H H L-H High-Z Write Cycle, Begin Burst external L H L H L X L X L-H D Read Cycle, Continue Burst next X X X H H L H L L-H Q Read Cycle, Continue Burst next X X X H H L H H L-H High-Z Read Cycle, Continue Burst next H X X X H L H L L-H Q Read Cycle, Continue Burst next H X X X H L H H L-H High-Z Write Cycle, Continue Burst next X X X H H L L X L-H D Write Cycle, Continue Burst next H X X X H L L X L-H D Read Cycle, Suspend Burst current X X X H H H H L L-H Q Read Cycle, Suspend Burst current X X X H H H H H L-H High-Z Read Cycle, Suspend Burst current H X X X H H H L L-H Q Read Cycle, Suspend Burst current H X X X H H H H L-H High-Z Write Cycle, Suspend Burst current X X X H H H L X L-H D Write Cycle, Suspend BurstcurrentHXXXHHLXL-HDGS841E18AT/B-180/166/150/130/100Notes:1.X means “don’t care,” H means “logic high,” L means “logic low.”2.Write is the logic function of GW, BWE, BW1, BW2. See Byte Write Function table for detail.3.CE is defined as CE1=L, CE2=H and CE3=L4.All signals are synchronous and are sampled by CLK except OE and MOE. OE and MOE are asynchronous and drive the bus immediately.)Note:Permanent damage to the device may occur if the Absolute Maximun Ratings are exceeded. Functional operation should be restricted to the recommended operation conditions. Exposure to higher than recommended voltages, for an extended period of time, could effect the performance and reliability of this component.Truth Table For Read/Write/Compare/Fill Write OperationCEWriteDEMOEOEMatchDQRead L H X X L —Q Write L L L X H —D Compare L H L L H Data Out D Fill Write L L H X X —X Match Deselect H X X L X High High Z DeselectHXXHXHigh ZHigh ZAbsolute Maximum Ratings (Voltage reference to V SS = 0 V)SymbolDescriptionCommericalUnitV DD Supply Voltage –0.5 to 4.6V V DDQ Output Supply Voltage –0.5 to V DD V V CLK CLK Input Voltage –0.5 to 6V V in Input Voltage –0.5 to V DD + 0.5 (≤ 4.6 V max. )V V out Output Voltage –0.5 to V DD + 0.5 (≤ 4.6 V max. )V I out Output Current per I/O +/–20mA P D Power Dissipation 1.5WT OPR Operating Temperature 0 to 70o C T STGStorage Temperature–55 to 125oCGS841E18AT/B-180/166/150/130/100Notes:1.Junction temperature is a function of SRAM power dissapation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance.2.SCMI G-38-87.3.Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1.Package Thermal CharacteristicsRatingLayer BoardSymbolTQFP maxPBGA maxUnitNotesJunction to Ambient (at 200 lfm)single R ΘJA 3228°C/W 1,2Junction to Ambient (at 200 lfm)four R ΘJA 2018°C/W 1,2Junction to Case (TOP)—R ΘJC74°C/W3Notes: 1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.3.Output load 2 for t LZ , t HZ , t OLZ and t OHZ .4.Device is deselected as defined by the Truth Table.AC Test Conditions(VDD = 3.135 V–3.6 V, Ta = 0–70°C)ParameterConditionsInput high level V IH = 2.3 V Input low level V IL = 0.2 V Input slew rate TR = 1 V/ns Input reference level 1.25 V Output reference level1.25 V Output loadFig. 1& 2DQVT = 1.25 V50W 30pF 1DQ2.5 V F IG . 1Output load 1Output load 2F IG . 2225W 225W5pF 1GS841E18AT/B-180/166/150/130/100DC Characteristics and Supply Currents(Voltage reference to V SS = 0 V)(VDD = 3.135 V–3.6 V, Ta = 0–70°C for Commercial Temperature Offering)Parameter Symbol Test Conditions Min MaxInput Leakage Current(except ZZ, FT, LBO pins)I IL V IN = 0 to V DD–1 uA 1 uAZZ Input Current Iin ZZ V DD ≥V IN ≥V IH0 V≤ V IN ≤ V IH–1 uA–1 uA1 uA300 uAMode Input Current (FT & LBO pins)Iin MV DD ≥V IN ≥V IL0 V≤ V IN ≤ V IL–30 0uA–1 uA1 uA1 uAOutput Leakage Current I ol Output Disable,V OUT = 0 to V DD–1 uA 1 uAOutput High Voltage V OH I OH = –4 mA, V DDQ = 2.375 V 1.7 VOutput High Voltage V OH I OH = –4 mA, V DDQ = 3.135 V 2.4 VOutput Low Voltage V OL I OL = +4 mA0.4 VGS841E18AT/B-180/166/150/130/100Operating CurrentsParameter Test Conditions Symbol-180-166-150-133-100Unit 0to70°C–40to85°Cto70°C–40to+85°Cto70°C–40to+85°Cto70°C–40to+85°Cto70°C–40to+85°CO perating Current Device Selected;All other inputs≥ V IH O r ≤ V ILOutput openI DDPipeline335345310320275285250260190200mAI DDFlowThrough210220190200190200140150140150mAStandby Current ZZ≥ V DD – 0.2 VI SBPipeline20303040304030403040mAI SBFlowThrough20303040304030403040mADeselect Supply Current Device Deselected;All other inputs≥ V IH OR≤ V ILI DDPipeline55651101201051151001108090mAI DDFlowThrough40508090809065756575mAGS841E18AT/B-180/166/150/130/100Notes:1.These parameters are sampled and are not 100% tested2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.AC Electrical CharacteristicsParameterSymbol-180-166-150-133-100UnitMinMaxMinMaxMinMaxMinMaxMinMaxPipelineClock Cycle Time tKC 5.5— 6.0— 6.7—7.5—10—ns Clock to Output Valid tKQ — 3.2— 3.5— 3.8—4— 4.5ns Clock to Output InvalidtKQX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Output in Low-Z tLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Match Valid tKM — 3.2— 3.5— 3.8—4— 4.5ns Clock to Match Invalid tKMX 1.5— 1.5— 1.5— 1.5— 1.5—ns Clock to Match in Low-Z tMLZ 1 1.5— 1.5— 1.5— 1.5— 1.5—ns Flow ThroughClock Cycle Time tKC 9.1—10.0—10.0—15.0—15.0—ns Clock to Output Valid tKQ —8.0—8.5—10.0—11.0—12.0ns Clock to Output InvalidtKQX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Output in Low-Z tLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Match Valid tKM —8.5—8.5—10.0—11.0—12.0ns Clock to Match Invalid tKMX 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock to Match in Low-Z tMLZ 1 3.0— 3.0— 3.0— 3.0— 3.0—ns Clock HIGH Time tKH 1.3— 1.3— 1.5— 1.7—2—ns Clock LOW Time tKL 1.5— 1.5— 1.7—1.9—2.2—ns Clock to Output in High-Z tHZ 1 1.53.2 1.5 3.5 1.5 3.8 1.54 1.55ns OE to Output Valid tOE — 3.2— 3.5— 3.8—4—5ns OE to output in Low-Z tOLZ 10—0—0—0—0—ns OE to output in High-Z tOHZ 1— 3.2— 3.5— 3.8—4—5ns MOE to Match Valid tMOE — 3.2— 3.5— 3.8—4—5ns MOE to Match in Low-Z tMOLZ 10—0—0—0—0—ns MOE to Match in High-ZtMOHZ 1— 3.2— 3.5— 3.8—4—5ns Setup time tS 1.5— 1.5— 1.5— 2.0— 2.0—ns Hold time tH 0.5—0.5—0.5—0.5—0.5—ns ZZ setup time tZZS 25—5—5—5—5—ns ZZ hold time tZZH 21—1—1—1—1—ns ZZ recoverytZZR20—20—20—20—20—nsGS841E18AT/B-180/166/150/130/100Pipeline Mode TimingBegin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS841E18AT/B-180/166/150/130/100Flow Through Mode TimingBegin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS841E18AT/B-180/166/150/130/100Pipeline Compare Fill Write CycleHit Miss Fill WriteA BBA A tKMtKMtKMXtKM tMOE tMLZtH tStH tStH tStH tStH tSKAddressDQCEW GDE MOEMatchGS841E18AT/B-180/166/150/130/100Flow Through Compare Fill Write CycleHit Miss Fill WriteA BBA A tKMtKM tKMXtKM tMOE tMLZtH tStH tStH tStH tStH tSKAddressDQCEW GDE MOEMatchGS841E18AT/B-180/166/150/130/100TQFP Package Drawing (Package T)D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°GS841E18AT/B-180/166/150/130/100Package Dimensions—119-Bump FPBGA (Package B, Variation 2)A B C D E F G H J K L M N P R T U1 2 3 4 5 6 77 6 5 4 3 2 1A1 TOP VIEWA1 BOTTOM VIEW 1.277.621.2720.3214±0.1022±0.10BA 0.20(4x)Ø0.10Ø0.30CC A B S S Ø0.60~0.90 (119x)CSEATING PLANE0.15C0.50~0.701.86.±0.130.70±0.050.15CA B C D E F G H J K L M N P R T U0.56±0.05S SGS841E18AT/B-180/166/150/130/100 Ordering InformationOrg Part Number1Type Package Speed 2(MHz/ns)T A3Status256K x 18GS841E18AT-180DCD Pipeline/Flow Through TQFP180/8C256K x 18GS841E18AT-166DCD Pipeline/Flow Through TQFP166/8.5C256K x 18GS841E18AT-150DCD Pipeline/Flow Through TQFP150/10C256K x 18GS841E18AT-133DCD Pipeline/Flow Through TQFP133/11C256K x 18GS841E18AT-100DCD Pipeline/Flow Through TQFP100/12C256K x 18GS841E18AT-180I DCD Pipeline/Flow Through TQFP180/8I256K x 18GS841E18AT-166I DCD Pipeline/Flow Through TQFP166/8.5I256K x 18GS841E18AT-150I DCD Pipeline/Flow Through TQFP150/10I256K x 18GS841E18AT-133I DCD Pipeline/Flow Through TQFP133/11I256K x 18GS841E18AT-100I DCD Pipeline/Flow Through TQFP100/12I256K x 18GS841E18AGT-180DCD Pipeline/Flow Through Pb-Free TQFP180/8C256K x 18GS841E18AGT-166DCD Pipeline/Flow Through Pb-Free TQFP166/8.5C256K x 18GS841E18AGT-150DCD Pipeline/Flow Through Pb-Free TQFP150/10C256K x 18GS841E18AGT-133DCD Pipeline/Flow Through Pb-Free TQFP133/11C256K x 18GS841E18AGT-100DCD Pipeline/Flow Through Pb-Free TQFP100/12C256K x 18GS841E18AGT-180I DCD Pipeline/Flow Through Pb-Free TQFP180/8I256K x 18GS841E18AGT-166I DCD Pipeline/Flow Through Pb-Free TQFP166/8.5I256K x 18GS841E18AGT-150I DCD Pipeline/Flow Through Pb-Free TQFP150/10I256K x 18GS841E18AGT-133I DCD Pipeline/Flow Through Pb-Free TQFP133/11I256K x 18GS841E18AGT-100I DCD Pipeline/Flow Through Pb-Free TQFP100/12I256K x 18GS841E18AB-180DCD Pipeline/Flow Through119 BGA (var. 2)180/8C256K x 18GS841E18AB-166DCD Pipeline/Flow Through119 BGA (var. 2)166/8.5C256K x 18GS841E18AB-150DCD Pipeline/Flow Through119 BGA (var. 2)150/10C256K x 18GS841E18AB-133DCD Pipeline/Flow Through119 BGA (var. 2)133/11C256K x 18GS841E18AB-100DCD Pipeline/Flow Through119 BGA (var. 2)100/12C256K x 18GS841E18AB-180I DCD Pipeline/Flow Through119 BGA (var. 2)180/8I256K x 18GS841E18AB-166I DCD Pipeline/Flow Through119 BGA (var. 2)166/8.5I256K x 18GS841E18AB-150I DCD Pipeline/Flow Through119 BGA (var. 2)150/10I256K x 18GS841E18AI-133I DCD Pipeline/Flow Through119 BGA (var. 2)133/11I256K x 18GS841E18AB-100I DCD Pipeline/Flow Through119 BGA (var. 2)100/12INotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS841E18AT-166T.2.The speed column indicates the cycle frequency (Mhz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline / Flow through mode selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of whichare covered in this data sheet. See the GSI Technology web site for a complete listing of current offerings.GS841E18AT/B-180/166/150/130/100Specifications cited are subject to change without notice. For latest documentation see .Rev: 1.03 4/200521/21© 2001, GSI Technology 4Mb Synchronous Tag RAM Datasheet Revision History Rev. Code: Old;NewTypes of Changes Format or Content Page /Revisions;Reason GS841E18A_r1• Creation of new datasheet GS841E18A_r1;GS841E18A_r1_01Content • Moved TCK from U6 (incorrect placement) to U4 (correct placement) on BGA• Changed U6 to NCGS841E18A_r1_01; GS841E18A_r1_02Format/Content • Updated format• Added 180 MHz speed bin• Updated timing diagrams• Updated mechanical drawings• Added Pb-Free info for TQFPGS841E18A_r1_02;GS841E18A_r1_03Content• Added Pipeline Compare Fill Write Cycle and Flow ThroughCompare Fill Write Cycle timing diagrams 元器件交易网。

GS8662R18E-200资料

GS8662R08/09/18/36E-333/300/250/200/16772Mb SigmaCIO DDR-II Burst of 4 SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaCIO™ Interface • Common I/O bus• JEDEC-standard pinout and package • Double Data Rate interface• Byte Write (x36 and x18) and Nybble Write (x8) function • Burst of 4 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface• Pipelined read operation with self-timed Late Write • Fully coherent read and write pipelines• ZQ pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan• Pin-compatible with present 9Mb, 18Mb, 36Mb and future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaCIO ™ Family OverviewThe GS8662R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 75,497,472-bit (72Mb)SRAMs. The GS8662R08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed toimplement economical high performance networking systems.Clocking and Addressing SchemesThe GS8662R08/09/18/36E SigmaCIO DDR-II SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate theoutput register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-endedclock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead.Common I/O x36 and x18 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, A0 and A1 preset an internal 2 bit linear addresscounter. The counter increments by 1 for each beat of a burst of four data transfer. The counter always wraps to 00 after reaching 11, no matter where it starts.Common I/O x8 SigmaCIO DDR-II B4 RAMs always transfer data in four packets. When a new address is loaded, the LSBs are internally set to 0 for the first read or write transfer, and incremented by 1 for the next 3 transfers. Because the LSBs are tied off internally, the address field of a x8 SigmaCIO DDR-II B4 RAM is always two address pins less than the advertised index depth (e.g., the 4M x 18 has a 1024K addressable index).Parameter Synopsis-333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.5 ns165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump ArrayBottom View2M x 36 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ MCL/SA (144Mb)SA R/W BW2K BW1LD SA SA CQ B NC DQ27DQ18SA BW3K BW0SA NC NC DQ8C NC NC DQ28V SS SA SA0SA1V SS NC DQ17DQ7D NC DQ29DQ19V SS V SS V SS V SS V SS NC NC DQ16E NC NC DQ20 V DDQ V SS V SS V SS V DDQ NC DQ15DQ6F NC DQ30DQ21 V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC DQ31DQ22 V DDQ V DD V SS V DD V DDQ NC NC DQ14H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC DQ32 V DDQ V DD V SS V DD V DDQ NC DQ13DQ4K NC NC DQ23V DDQ V DD V SS V DD V DDQ NC DQ12DQ3L NC DQ33DQ24 V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC DQ34 V SS V SS V SS V SS V SS NC DQ11DQ1N NC DQ35DQ25 V SS SA SA SA V SS NC NC DQ10P NC NC DQ26SA SA C SA SA NC DQ9DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17; BW2 controls writes to DQ18:DQ26; BW3 controls writes toDQ27:DQ352.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1674M x 18 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W BW1K NC LD SA SA CQ B NC DQ9NC SA NC K BW0SA NC NC DQ8C NC NC NC V SS SA SA0SA1V SS NC DQ7NC D NC NC DQ10V SS V SS V SS V SS V SS NC NC NC E NC NC DQ11 V DDQ V SS V SS V SS V DDQ NC NC DQ6F NC DQ12NC V DDQ V DD V SS V DD V DDQ NC NC DQ5G NC NC DQ13 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ4NC K NC NC DQ14V DDQ V DD V SS V DD V DDQ NC NC DQ3L NC DQ15NC V DDQ V SS V SS V SS V DDQ NC NC DQ2M NC NC NC V SS V SS V SS V SS V SS NC DQ1NC N NC NC DQ16 V SS SA SA SA V SS NC NC NC P NC NC DQ17SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ172.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 9 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC DQ4C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ5 V DDQ V SS V SS V SS V DDQ NC NC DQ3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ2NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ7NC V DDQ V SS V SS V SS V DDQ NC NC DQ1M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ8SA SA C SA SA NC NC DQ0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/1678M x 8 SigmaCIO DDR-II SRAM—Top View1234567891011ACQ SA SA R/W NW1K NC LD SA SA CQ B NC NC NC SA NC K NW0SA NC NC DQ3C NC NC NC V SS SA NC SA V SS NC NC NC D NC NC NC V SS V SS V SS V SS V SS NC NC NC E NC NC DQ4 V DDQ V SS V SS V SS V DDQ NC NC DQ2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC NC DQ5 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC DQ1NC K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC DQ6NC V DDQ V SS V SS V SS V DDQ NC NC DQ0M NC NC NC V SS V SS V SS V SS V SS NC NC NC N NC NC NC V SS SA SA SA V SS NC NC NC P NC NC DQ7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—13 x 15 mm 2 Body—1 mm Bump PitchNotes:1.Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0 and A1. SA0 and SA1 are set to0 at the beginning of each access.2.NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ73.MCL = Must Connect LowGS8662R08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R Synchronous Read Input Active High W Synchronous Write Input Active Low BW0–BW3Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load PinInput Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active LowTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching InputInput —MCL Must Connect Low——DQ Data I/O Input/Output Three State Doff Disable DLL when low Input Active LowCQ Output Echo Clock Output —CQ Output Echo Clock Output —V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.5 V NominalV SSPower Supply: GroundSupply—GS8662R08/09/18/36E-333/300/250/200/167Note:NC = Not Connected to die or any other pinGS8662R08/09/18/36E-333/300/250/200/167BackgroundCommon I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications. Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half.Burst OperationsRead and write operations are “burst” operations. In every case where a read or write command is accepted by the SRAM, it will respond by issuing or accepting four beats of data, executing a data transfer on subsequent rising edges of K and K#, as illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Four beats of data are always transferred. This means that it is possible to load new addresses every other K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.Deselect CyclesChip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the four beat read data transfer and then execute the deselect command, returning the output drivers to high-Z.A high on the LD# pin prevents the RAM from loading read or write commandinputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer operations.SigmaCIO DDR-II B4 SRAM Read CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer inresponse to a read command, if the previous command captured was a read or write command, the Address, LD# and R/W# pins are ignored. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes pipelined reads. The read command is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM produces data out in response to the next rising edge of C# (or the next rising edge of K#, if C and C# are tied high). The second beat of data is transferred on the next rising edge of C, then on the next rising edge of C# and finally on the next rising edge of C, for a total of four transfers per address load.SigmaCIO DDR-II B4 SRAM Write CyclesThe status of the Address, LD# and R/W# pins are evaluated on the rising edge of K. Because the device executes a four beat burst transfer in response to a write command, if the previous command captured was a read or write command, the Address, LD# and R/ W# pins are ignored at the next rising edge of K. If the previous command captured was a deselect, the control pin status is checked.The SRAM executes “late write” data transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command and the write address. To complete the remaining three beats of the burst of four write transfer the SRAM captures data in on the next rising edge of K#, the following rising edge of K and finally on the next rising edge of K#, for a total of four transfers per address load.GS8662R08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 20).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662R08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 4 beat data transfer. The x18 version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) write control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NBx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleTimeBW0BW1D0–D8D9–D17Beat 101Data In Don’t CareBeat 210Don’t Care Data InBeat 300Data In Data InBeat 410Don’t Care Data InResulting Write OperationByte 1 D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Byte 1D0–D8Byte 2D9–D17Written Unchanged Unchanged Written Written Written Unchanged Written Beat 1Beat 2Beat 3Beat 4Output Register ControlSigmaCIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs isare tied high, the RAM reverts to K and K control of the outputs, allowing the RAM to function as a conventional pipelined read SRAM.A K R/W LDA 0–A nKBank 0Bank 1Bank 2Bank 3A KLD A K LD A K LD R/W R/W R/W DQDQDQ DQCC CCDQ 1–C R/WLD 0LD 1LD 2LD 3Note:For simplicity BWn (or NWn), K, and C are not shown.CQ CQ CQ CQ CQGS8662R08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicGS8662R08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaCIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver isimplemented with discrete binary weighted impedance steps. Updates of pull-down drive impedance occur whenever a driver is producing a “1” or is High-Z. Pull-up drive impedance is updated when a driver is producing a “0” or is High-Z.Common I/O SigmaCIO DDR-II B4 SRAM Truth TableK nLDR/WDQOperationA + 0A + 1A + 2A + 3↑1X Hi-Z Hi-Z Hi-Z Hi-Z Deselect ↑00D@K n+1D@K n+1D@K n+2D@K n+2Write ↑1Q@K n+1or C n+1Q@K n+2or C n+2Q@K n+2or C n+2Q@K n+3or C n+3ReadNote:Q is controlled by K clocks if C clocks are not used.B4 Byte Write Clock Truth TableBW BW BW BW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if BWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if BWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if BWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if BWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if BWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662R08/09/18/36E-333/300/250/200/167*Assuming stable conditions, the RAM can achieve optimum impedance within 1024 cycles.B4 Nybble Write Clock Truth TableNW NW NW NW Current OperationD D D D K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)K ↑(t n )K ↑(t n+1)K ↑(t n+1½)K ↑(t n+2)K ↑(t n+2½)TTTTWriteDx stored if NWn = 0 in all four data transfers D0D2D3D4T F F F WriteDx stored if NWn = 0 in 1st data transfer only D0X X XF T F F WriteDx stored if NWn = 0 in 2nd data transfer only X D1X XF F T F WriteDx stored if NWn = 0 in 3rd data transfer only X X D2XF F F T WriteDx stored if NWn = 0 in 4th data transfer only X X X D3F F F F Write AbortNo Dx stored in any of the four data transfersX X X XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more NWn = 0, then NW = “T”, else NW = “F”.GS8662R08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW0BW1BW2BW3D0–D8D9–D17D18–D26D27–D351111Don’t Care Don’t Care Don’t Care Don’t Care 0111Data In Don’t Care Don’t Care Don’t Care 1011Don’t Care Data In Don’t Care Don’t Care 0011Data In Data In Don’t Care Don’t Care 1101Don’t Care Don’t Care Data In Don’t Care 0101Data In Don’t Care Data In Don’t Care 1001Don’t Care Data In Data In Don’t Care 0001Data In Data In Data In Don’t Care 1110Don’t Care Don’t Care Don’t Care Data In 0110Data In Don’t Care Don’t Care Data In 1010Don’t Care Data In Don’t Care Data In 0010Data In Data In Don’t Care Data In 1100Don’t Care Don’t Care Data In Data In 0100Data In Don’t Care Data In Data In 1000Don’t Care Data In Data In Data In 0Data InData InData InData Inx18 Byte Write Enable (BWn) Truth Table BW0BW1D0–D8D9–D1711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData Inx8 Nybble Write Enable (NWn) Truth Table NW0NW1D0–D3D4–D711Don’t Care Don’t Care 01Data In Don’t Care 10Don’t Care Data In 0Data InData InGS8662R08/09/18/36E-333/300/250/200/167GS8662R08/09/18/36E-333/300/250/200/167B4 State DiagramPower-UpNOPLoad New AddressDDR Read DDR WriteLOADREAD WRITE LOADLOADLOADLOADNotes:1.The internal burst address counter is a 4-bit linear counter (i.e., when first address is A0, next internal burst address is A0+1).2.“READ” refers to read active status with R/W = High, “WRITE” refers to write inactive status with R/W = Low.3.“LOAD” refers to read new address active status with LD = Low, “LOAD” refers to read new address inactive status with LD = High.LOAD Increment Read Address Increment Write AddressAlwaysAlwaysREADWRITEAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.5 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662R08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.7 1.8 1.9V Reference VoltageV REF0.68—0.95VNotes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V DDQ ≤ 1.6 V (i.e., 1.5 V I/O)and 1.7 V ≤ V DDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.2.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signal inputs. Thepower down sequence must be the reverse. V DDQ must not exceed V DD ..Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662R08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.10V DD + 0.3 V V 1DC Input Logic LowV IL (dc)–0.3 VV REF – 0.10V1Notes:patible with both 1.8 V and 1.5 V I/O drivers2.These are DC test criteria. DC design criteria is V REF ± 50 mV. The AC V IH /V IL levels are defined separately for measuring timing parame-ters.3.V IL (Min) DC = –0.3 V, V IL (Min) AC = –1.5 V (pulse width ≤ 3 ns).4.V IH (Max) DC = V DDQ + 0.3 V, V IH (Max) AC = V DDQ + 0.85 V (pulse width ≤ 3 ns).HSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 0.20—V 3,4AC Input Logic LowV IL (ac)—V REF – 0.20V 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)V1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output Capacitance C OUT V OUT = 0 V67pF Clock CapacitanceC CLK—56pFNote:This parameter is sample tested.GS8662R08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –100 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 3.3 V)GS8662R08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2V DDQ V 1, 3Output Low Voltage V OL1 Vss V DDQ /2V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9):DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8):DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP):DDRI SB1Device deselected,I OUT = 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662R08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKH t CHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.07.88 6.08.4ns tTKC Variablet KCVar —0.2—0.2—0.2—0.2—0.2ns 5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKL t CHCL 1.2— 1.32— 1.6— 2.0— 2.4—ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKH t CLCH 1.2— 1.32— 1.6— 2.0— 2.4—ns K to K High C to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—ns K, K Clock High to C, C Clock High t KHCH 0 1.30 1.450 1.80 2.30 2.8ns DLL Lock Time t KCLock 1024—1024—1024—1024—1024—cycle 6K Static to DLL resett KCReset 30—30—30—30—30—nsOutput TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQV t CHQV —0.45—0.45—0.45—0.45—0.5ns 3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQX t CHQX –0.45—–0.45—–0.45—–0.45—–0.5—ns 3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQV t CHCQV —0.45—0.45—0.45—0.45—0.5ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQX t CHCQX –0.45—–0.45—–0.45—–0.45—–0.5—ns CQ, CQ High Output Valid t CQHQV —0.25—0.27—0.30—0.35—0.40ns 7CQ, CQ High Output Hold t CQHQX –0.25—–0.27—–0.30—–0.35—–0.40—ns 7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZ t CHQZ —0.45—0.45—0.45—0.45—0.5ns 3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Zt KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH 0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH 0.4—0.4—0.5—0.6—0.7—ns 2Data Input Setup Timet DVKH0.28—0.3—0.35—0.4—0.5—ns。

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