实时时钟设计 - 副本

基于单片机电子时钟的设计与实现一、设计目标设计一个基于单片机的电子时钟，能够准确显示时间并能够进行设置和调整。

二、硬件设计1.时钟部分：采用晶振芯片提供准确的时钟信号2.数码管显示部分：使用共阴数码管进行数字显示3.按键部分：设计几个按键用于设置和调整时间4.电源部分：采用直流电源供电三、软件设计1.功能设计a.时间设置功能：通过按键可以设置当前的时间，包括小时、分钟和秒钟。

b.时间调整功能：通过按键可以调整当前的时间，包括小时、分钟和秒钟。

c.时间显示功能：通过数码管可以实时显示当前的时间。

2.代码实现以C语言为例，以下是一个基于单片机的电子时钟的代码实现示例：```c#include <reg51.h>sbit DS18B20=P1^3; // 定义18B20数据线接口sbit beep=P2^3; // 定义蜂鸣器接口unsigned char hour,min,sec; // 定义小时、分钟、秒钟变量//函数声明void Delay_1ms(unsigned int count);bit Ds18b20Init(;unsigned char Ds18b20ReadByte(;void ReadTime(;void WriteTime(;void DisplayTime(;//主函数void mainP2=0x00;WriteTime(; // 写入时间while(1)ReadTime(; // 读取时间DisplayTime(; // 显示时间Delay_1ms(1000); // 延时1秒}//毫秒延时函数void Delay_1ms(unsigned int count) unsigned int i, j;for(i=0; i<count; i++)for(j=0; j<1275; j++);//18B20初始化函数bit Ds18b20Initbit presence;DS18B20=0;Delay_1ms(100); // 延时450us~1000us DS18B20=1;Delay_1ms(10); // 延时15us~60us presence=DS18B20;Delay_1ms(30); // 延时60us~240us return presence;//18B20读取字节函数unsigned char Ds18b20ReadByte unsigned char i, dat;for(i=0; i<8; i++)DS18B20=0;//主机发起读时序_nop_(; // 延时1us_nop_(; // 延时1us_nop_(; // 延时1usDS18B20=1;//主机释放总线_nop_(; // 延时1us_nop_(; // 延时1us_nop_(; // 延时1usdat，=(DS18B20<<i); // 读取数据位，存放在dat变量中Delay_1ms(3); // 读时序完成后等待48us再接收下一位}return dat;//读取时间函数void ReadTimeunsigned char temp;temp=0x00;while(temp!=0xaa)Ds18b20Init(; // 初始化温度传感器Delay_1ms(1);DS18B20=0xcc;Delay_1ms(1);DS18B20=0xbe;Delay_1ms(1);temp=Ds18b20ReadByte(; // 读取时间数组的标志位}for(temp=0; temp<7; temp++)//写入时间函数void WriteTimeunsigned char i,j;while(1)Ds18b20Init(;Delay_1ms(1);DS18B20=0xcc;Delay_1ms(1);DS18B20=0x4e;Delay_1ms(1);for(i=0; i<7; i++)DS18B20=0x55;Delay_1ms(1);DS18B20=0xaa;Delay_1ms(1);Ds18b20Init(;Delay_1ms(1);DS18B20=0xcc;Delay_1ms(1);DS18B20=0x48;Delay_1ms(1);j=Ds18b20ReadByte(; // 判断是否写入成功if(j==0x0a)break;}//显示时间函数void DisplayTimeP1=seg[hour/10]; // 显示十位小时P2=(P2&0xf0)，0x08; // 点亮第一个数码管Delay_1ms(5); // 延时一段时间P2=0x0f;//熄灭数码管P1=seg[hour%10]; // 显示个位小时P2=(P2&0xf0)，0x04; // 点亮第二个数码管Delay_1ms(5); // 延时一段时间P2=0x0f;//熄灭数码管P1=seg[min/10]; // 显示十位分钟P2=(P2&0xf0)，0x02; // 点亮第三个数码管Delay_1ms(5); // 延时一段时间P2=0x0f;//熄灭数码管P1=seg[min%10]; // 显示个位分钟P2=(P2&0xf0)，0x01; // 点亮第四个数码管Delay_1ms(5); // 延时一段时间P2=0x0f;//熄灭数码管P1=0x00;//空显示P2=0x00;//熄灭数码管```四、总结通过以上的硬件设计和软件实现，可以实现一个基于单片机的电子时钟。

linux实时时间显示课程设计一、教学目标本课程的教学目标是让学生掌握Linux系统中实时时间显示的原理和方法。

具体包括：1.知识目标：–了解Linux操作系统的基本结构；–掌握Linux系统中的时间管理机制；–理解实时时间显示的原理和方法。

2.技能目标：–能够配置Linux系统的时钟；–能够使用命令行工具获取实时时间；–能够编写简单的脚本实现实时时间显示。

3.情感态度价值观目标：–培养学生的动手实践能力，提高他们对计算机科学的兴趣；–培养学生团队合作精神，提高他们的问题解决能力。

二、教学内容本课程的教学内容主要包括以下几个部分：1.Linux操作系统基本结构：介绍Linux操作系统的内核、文件系统、进程管理等基本组成部分；2.时间管理机制：讲解Linux系统中的时间管理机制，包括时钟、时间源、时间同步等；3.实时时间显示原理：介绍实时时间显示的原理，包括硬件时钟、软件时钟、NTP协议等；4.实时时间显示方法：讲解如何在Linux系统中实现实时时间显示，包括命令行工具的使用、脚本的编写等。

三、教学方法本课程采用多种教学方法，以激发学生的学习兴趣和主动性：1.讲授法：用于讲解Linux操作系统基本结构、时间管理机制等理论知识；2.讨论法：通过小组讨论，让学生深入理解实时时间显示的原理和方法；3.案例分析法：分析实际案例，让学生掌握命令行工具和脚本的使用；4.实验法：让学生动手实践，配置Linux系统的时钟，编写实时时间显示的脚本。

四、教学资源本课程所需的教学资源包括：1.教材：《Linux操作系统原理与应用》；2.参考书：《Linux系统编程》；3.多媒体资料：PPT课件、实验指导视频等；4.实验设备：计算机、网络设备等。

以上教学资源将有助于实现本课程的教学目标，提高学生的学习效果。

五、教学评估本课程的评估方式包括以下几个方面：1.平时表现：通过课堂参与、提问、讨论等环节，评估学生的学习态度和理解程度；2.作业：布置相关的编程练习和理论作业，评估学生对知识的掌握和应用能力；3.实验报告：评估学生在实验过程中的操作技能和对实时时间显示原理的理解；4.期末考试：采用闭卷考试的方式，全面测试学生的理论知识和实践能力。

ppt中可以插入实时时钟吗方法教程ppt中可以插入实时时钟吗方法教程有时在考试或者作演示时候为了展示时间，我们需要在ppt中插入一个实时时钟，方便我们知道时间，具体怎么设置呢?为此店铺整理了ppt中插入时钟的方法教程，希望对你有所帮助。

在ppt中插入时钟的方法1、将需要插入幻灯片的Flash文件与PPT文件放在一个文件内。

(也可以不放在一个文件夹内，但为了后面的设置简单，所以建议大家放在一个文件夹内)。

2、打开需要插入Flash的PPT文件。

3、Flash文件是不能直接插入PPT中的，需要使用Flash控件。

首先进入工具栏的“文件”选项卡，然后点击“选项”。

4、在打开的PowerPoint选项窗口中，点击左侧的“快速访问工具栏”。

5、在快速访问工具栏选项卡里，点击下拉箭头，从列表中选择“开发工具选项卡”。

6、然后在开发工具列表里找到“其他控件”并选中。

7、选中其他控件后点击添加按钮，此次右侧的列表里就新增了“其他控件”命令。

8、添加完成后点击PowerPoint选项窗口下方的“确定”即可。

9、回到PowerPoint编辑主界面，此时你会发现在PowerPoint 顶部的快速访问工具栏新增了“其他控件”工具。

10、点击顶部的“其他控件”命令，弹出一个控件窗口。

11、在控件列表里找到“Shockwave Flash Object”并选中。

12、选中后点击确定。

13、点击确定后鼠标指针会变成“+”字形，此时按住鼠标左键绘制一个矩形Flah控件即可(随意大小就行，大小都是可以随时更改的)。

14、在绘制好的控件上点击鼠标右键，从下拉菜单中选择“属性”。

此时弹出一个属性窗口。

15、这时回到存放Flash文件的文件夹，在Flash文件上点击鼠标右键，点击下拉菜单中的“属性”。

16、在打开的文件属性窗口中复制该文件的文件名(包括扩展名.swf)。

17、回到PowerPoint中，在控件属性窗口中找到Movie一项，将Flash文件的完整文件名(包括扩展名.swf)设置为Movie的值。

EDA课程设计-电子钟一、设计要求1、基本功能要求：设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。

扩展功能要求：2、跑表功能，闹钟功能，调整数码管的亮度。

二、系统结构控制键—jian5、jian4、jian7、jian8：数码管显示段选信号输出sg：——选择6位数码管中的某一个显示数据；发光二极管控制信号输出—led（7~0）闹钟声音输出—speaker通过一个10M信号分出各种所需频率功能介绍运行后，选择模式7，8位数码管分显示时间的时、分、秒，当前为模式0：时间显示模式，按键7为模式选择键，按下按键7，系统进入模式1，第二次按下为模式2，设置时间模式，第三次按下为跑表模式，第四次为闹钟设置模式，第五次为亮度调节模式：设置时间模式，按键4控制更改数码管的位，按键5控制选中数码管的数值，时间设置完成后，按键按键8，设置时间会保存住，并在模式0中显示；系统进入模式2：秒表模式，按键4为开始/结束键，按键5为清零键；系统进入模式3：闹钟设置模式，相关设置与模式1相同，当当前时间与闹钟设置时间相同时，喇叭就会响；系统进入模式4:亮度调节模式，通过按键4设置亮度，共三种亮度；再按下按键7，系统又会进入模式0。

4、RTL图三、VHDL源程序1、library ieee; --通过10M分出所需频率use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport (clk_10M : in std_logic;clk_10000 : out std_logic;clk_100 : out std_logic;clk_1 : out std_logic);end entity;architecture sub1 of fenpin issignal Q_1 : std_logic_vector(8 downto 0);signal Q_2 : std_logic_vector(6 downto 0);signal Q_3 : std_logic_vector(6 downto 0);signal clk10000 : std_logic;signal clk100 : std_logic;signal clk1 : std_logic;beginprocess(clk_10M)beginif clk_10M'event and clk_10M='1' thenif Q_1=500 thenQ_1 <= "000000000";clk10000 <= not clk10000;if Q_2=100 thenQ_2 <= "0000000";clk100<= not clk100;if Q_3=100 thenQ_3 <= "0000000";clk1<=not clk1;else Q_3<=Q_3+1;end if;else Q_2<=Q_2+1;end if;else Q_1<=Q_1+1;end if;end if;end process;clk_10000 <= clk10000;clk_100 <= clk100;clk_1 <= clk1;end sub1;2、library ieee; --扫描数码管use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity xianshi isport(clk_10000:in std_logic;jian4:in std_logic;moshi:in integer range 0 to 4;a0,a1,a3,a4,a6,a7:in integer range 0 to 9;sg11:out std_logic_vector(6 downto 0);bt11:out std_logic_vector(7 downto 0));end;architecture one of xianshi issignal cnt8 :std_logic_vector(2 downto 0);signal a :integer range 0 to 15;signal light: std_logic;signal flash:integer range 0 to 2;signal count1,count2:integer range 0 to 10;beginp1: process(cnt8,light,a0,a1,a3,a4,a6,a7)begincase cnt8 iswhen "000" => bt11<= "0000000"&(light);a<=a0;when "001" => bt11<= "000000"&(light)&'0';a<=a1; when "010" => bt11<= "00000"&(light)&"00";a<=15; when "011" => bt11<= "0000"&(light)&"000";a<=a3; when "100" => bt11<= "000"&(light)&"0000";a<=a4; when "101" => bt11<= "00"&(light)&"00000";a<=15; when "110" => bt11<= '0'&(light)&"000000";a<=a6; when "111" => bt11<= (light)&"0000000";a<=a7;when others => null;end case;end process p1;p2:process(clk_10000)beginif clk_10000'event and clk_10000 ='1' then cnt8 <= cnt8+1; end if;end process p2;p3:process(a)begincase a iswhen 0 => sg11<= "0111111";when 1 => sg11<= "0000110";when 2 => sg11<= "1011011";when 3 => sg11<= "1001111";when 4 => sg11<= "1100110";when 5 => sg11<= "1101101";when 6 => sg11<= "1111101";when 7 => sg11<= "0000111";when 8 => sg11<= "1111111";when 9 => sg11<= "1101111";when 10 => sg11<= "1110111";when 11 => sg11<= "1111100";when 12 => sg11<= "0111001";when 13 => sg11<= "1011110";when 14 => sg11<= "1111001";when 15 => sg11<= "1000000";when others => null;end case;end process p3;process(jian4,moshi)beginif moshi=4 thenif jian4'event and jian4='1' thenif flash =2 thenflash<=0;else flash<=flash+1;end if;end if;end if;end process;process(clk_10000,flash)beginif clk_10000'event and clk_10000 ='1' thencase flash iswhen 0 => light<='1';when 1 => if count1=2 thencount1<=0; light<='1';else count1<=count1+1;light<='0';end if;when 2 => if count2=4 thencount2<=0; light<='1';else count2<=count2+1;light<='0';end if;end case;end if;end process;end;3、library ieee; --跑表开始暂停use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity paobiao isport(clk_1:in std_logic;jian8:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9); end entity;architecture bhv of paobiao issignal shi:integer range 0 to 100;signal fen:integer range 0 to 100;signal miao:integer range 0 to 100;beginprocess(clk_1,jian8,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1)beginif jian8='1' thenshi<=shishi1*10+shige1;fen<=fenshi1*10+fenge1;miao<=miaoshi1*10+miaoge1;elsif clk_1'event and clk_1='1' thenif miao=59 thenmiao<=0;fen<=fen+1;elsif fen>59 thenfen<=0;shi<=shi+1;elsif shi>23 thenshi<=0;else miao<=miao+1;end if;end if;end process;miaoge2<=miao rem 10;miaoshi2<=miao/10;fenge2<=fen rem 10;fenshi2<=fen/10;shige2<=shi rem 10;shishi2<=shi/10;end;4、library ieee; --设置当前时间use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity settime isport(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end entity;architecture bav of settime issignal a:integer range 0 to 5;signal shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1: integer range 0 to 9; beginprocess(moshi,jian4)beginif moshi=1 thenif jian4'event and jian4='1' thenif a < 5 thena<=a+1;else a<=0;end if;end if;end if;end process;process(moshi,a,jian5)beginif moshi=1 thenif a=0 thenif jian5'event and jian5='1' thenif miaoge1 =9 thenmiaoge1<=0;else miaoge1<=miaoge1+1;end if;end if;end if;if a=1 thenif jian5'event and jian5='1' thenif miaoshi1 =5 thenmiaoshi1<=0;else miaoshi1<=miaoshi1+1;end if;end if;end if;if a=2 thenif jian5'event and jian5='1' thenif fenge1 =9 thenfenge1<=0;else fenge1<=fenge1+1;end if;end if;end if;if a=3 thenif jian5'event and jian5='1' thenif fenshi1 =5 thenfenshi1<=0;else fenshi1<=fenshi1+1;end if;end if;end if;if a=4 thenif jian5'event and jian5='1' thenif shige1 =9 thenshige1<=0;else shige1<=shige1+1;end if;end if;end if;if a=5 thenif jian5'event and jian5='1' thenif shishi1 =2 thenshishi1<=0;else shishi1<=shishi1+1;end if;end if;end if;end if;end process;miaoge<=miaoge1;miaoshi<=miaoshi1;fenge<=fenge1;fenshi<=fenshi1;shige<=shige1;shishi<=shishi1;end;5、library ieee; --秒表功能use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity miaobiao isport(clk_100:in std_logic;moshi:in integer range 0 to 4;jian5,jian4:in std_logic;fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:out integer range 0 to 9); end entity;architecture bhv of miaobiao issignal fen,miao,xmiao:integer range 0 to 99;signal start:std_logic:='0';signal reset:std_logic:='0';beginprocess(clk_100,jian5,jian4,moshi,reset,start)beginif moshi=2 thenif reset='1' thenfen<=0;miao<=0;xmiao<=0;elsif start='1' thenelsif clk_100'event and clk_100='1' thenif xmiao=99 thenxmiao<=0;miao<=miao+1;elsif miao>59 thenmiao<=0;fen<=fen+1;elsif fen>23 thenfen<=0;else xmiao<=xmiao+1;end if;end if;end if;end process;process(jian4,start)beginif jian4'event and jian4='1' thenstart<=not start;else start<=start;end if;end process;process(jian5,reset)beginif jian5'event and jian5='1' thenreset<=not reset;else reset<= reset;end if;end process;xmiaoge<=xmiao rem 10;xmiaoshi<=xmiao/10;miaoge<=miao rem 10;miaoshi<=miao/10;fenge<=fen rem 10;fenshi<=fen/10;end;6、library ieee; --设置闹钟时间use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity naozhongset isport(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9); end entity;architecture bav of naozhongset issignal a:integer range 0 to 5;signal fenshi1,fenge1,miaoge1: integer range 0 to 9;signal shishi1: integer range 0 to 9:=1;signal shige1: integer range 0 to 9:=2;signal miaoshi1: integer range 0 to 9:=0;beginprocess(moshi,jian4)beginif moshi=3 thenif jian4'event and jian4='1' thenif a < 5 thena<=a+1;else a<=0;end if;end if;end if;end process;process(moshi,a,jian5)beginif moshi=3 thenif a=0 thenif jian5'event and jian5='1' thenif miaoge1 =9 thenmiaoge1<=0;else miaoge1<=miaoge1+1;end if;end if;end if;if a=1 thenif jian5'event and jian5='1' thenif miaoshi1 =5 thenmiaoshi1<=0;else miaoshi1<=miaoshi1+1;end if;end if;end if;if a=2 thenif jian5'event and jian5='1' thenif fenge1 =9 thenfenge1<=0;else fenge1<=fenge1+1;end if;end if;end if;if a=3 thenif jian5'event and jian5='1' thenif fenshi1 =5 thenfenshi1<=0;else fenshi1<=fenshi1+1;end if;end if;end if;if a=4 thenif jian5'event and jian5='1' thenif shige1 =9 thenshige1<=0;else shige1<=shige1+1;end if;end if;end if;if a=5 thenif jian5'event and jian5='1' thenif shishi1 =2 thenshishi1<=0;else shishi1<=shishi1+1;end if;end if;end if;end if;end process;miaoge<=miaoge1;miaoshi<=miaoshi1;fenge<=fenge1;fenshi<=fenshi1;shige<=shige1;shishi<=shishi1;end;7、library ieee; --闹钟喇叭输出use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity naozhongspeaker isport(clk_100:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9; speaker:out std_logic);end entity;architecture bav of naozhongspeaker isbeginprocess(clk_100,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2)beginif shishi2=shishi1 and shige2=shige1 and fenshi2=fenshi1 andfenge2=fenge1 and miaoshi2=miaoshi1 thenspeaker<=clk_100;else speaker<='1';end if;end process;end;8、library ieee; --转换模式use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity moshi isport(jian7:in std_logic;moshi:out integer range 0 to 4);end;architecture one of moshi issignal moshis:integer range 0 to 4;beginprocess(jian7)beginif jian7'event and jian7='1' thenif moshis=4 thenmoshis<=0;else moshis<=moshis+1;end if;end if;end process;moshi<=moshis;end;9、library ieee; --五选一选择器use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mux5_1 isport(moshi:in integer range 0 to 4 ;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9; fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;a0,a1,a3,a4,a6,a7:out integer range 0 to 9);end entity mux5_1;architecture bhv of mux5_1 isbeginprocess(shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1,shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2,shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3,fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge,moshi)begincase moshi iswhen 0 =>a0<=shishi1;a1<=shige1;a3<=fenshi1;a4<=fenge1;a6<=miaoshi1;a7<=miaoge1;when 1 =>a0<=shishi2;a1<=shige2;a3<=fenshi2;a4<=fenge2;a6<=miaoshi2;a7<=miaoge2;when 2 =>a0<=fenshi;a1<=fenge;a3<=miaoshi;a4<=miaoge;a6<=xmiaoshi;a7<=xmiaoge;when 3 =>a0<=shishi3;a1<=shige3;a3<=fenshi3;a4<=fenge3;a6<=miaoshi3;a7<=miaoge3;when 4 => a0<=8;a1<=8;a3<=8;a4<=8;a6<=8;a7<=8;end case;end process;end;10、library ieee; --主程序置顶use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity clock isport(clk_10M:in std_logic;jian5,jian4,jian7,jian8:in std_logic;sg:out std_logic_vector(6 downto 0);bt:out std_logic_vector(7 downto 0);speaker:out std_logic);end entity;调用声明语句architecture bav of clock iscomponent fenpin --分频port (clk_10M : in std_logic;clk_10000 : out std_logic;clk_100 : out std_logic;clk_1 : out std_logic);end component;component paobiao --跑表port(clk_1:in std_logic;jian8:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9; shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:out integer range 0 to 9);end component;component xianshi --扫描显示port(clk_10000:in std_logic;jian4:in std_logic;moshi:in integer range 0 to 4;a0,a1,a3,a4,a6,a7:in integer range 0 to 9;sg11:out std_logic_vector(6 downto 0);bt11:out std_logic_vector(7 downto 0));end component;component moshi --模式转换port(jian7:in std_logic;moshi:out integer range 0 to 4);end component;component mux5_1 --五选一选择器port(moshi:in integer range 0 to 4 ;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;shishi3,shige3,fenshi3,fenge3,miaoshi3,miaoge3:in integer range 0 to 9;fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:in integer range 0 to 9;a0,a1,a3,a4,a6,a7:out integer range 0 to 9);end component;component settime --设置当前时间port(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end component;component miaobiao is --秒表port(clk_100:in std_logic;moshi:in integer range 0 to 4;jian5,jian4:in std_logic;fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:out integer range 0 to 9);end component;component naozhongset is --闹钟时间设置port(moshi:in integer range 0 to 4;jian4,jian5:in std_logic;shishi,shige,fenshi,fenge,miaoshi,miaoge:out integer range 0 to 9);end component;component naozhongspeaker is --闹钟喇叭输出port(clk_100:in std_logic;shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:in integer range 0 to 9;shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:in integer range 0 to 9;speaker:out std_logic);end component;signal moshis:integer range 0 to 4; --信号声明signal shishi1s,shige1s,fenshi1s,fenge1s,miaoshi1s,miaoge1s:integer range 0 to 9;signal shishi2s,shige2s,fenshi2s,fenge2s,miaoshi2s,miaoge2s:integer range 0 to 9;signal shishi3s,shige3s,fenshi3s,fenge3s,miaoshi3s,miaoge3s:integer range 0 to 9;signal fenshis,fenges,miaoshis,miaoges,xmiaoshis,xmiaoges: integer range 0 to 9;signal a0s,a1s,a3s,a4s,a6s,a7s: integer range 0 to 9;signal clk_10000s,clk_100s, clk_1s: std_logic;begin --元件例化u1:paobiao port map(clk_1=>clk_1s,jian8=>jian8,shishi1=>shishi2s,shige1=>shige2s,fenshi1=>fenshi2s,fenge1=>fenge2s,miaoshi 1=>miaoshi2s,miaoge1=>miaoge2s,shishi2=>shishi1s,shige2=>shige1s,fenshi2=>fenshi1s,fenge2=>fenge1s,miaoshi2=>m iaoshi1s,miaoge2=>miaoge1s);u2:xianshi port map(clk_10000=>clk_10000s,jian4=>jian4,moshi=>moshis,a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s,sg11=>sg,bt11=>bt);u3:settime port map(moshi=>moshis,jian5=>jian5,jian4=>jian4,shishi=>shishi2s,shige=>shige2s,fenshi=>fenshi2s,fenge=>fenge2s,miaoshi=>miaosh i2s,miaoge=>miaoge2s);u4:moshi port map(jian7=>jian7,moshi=>moshis);u5:mux5_1 port map(moshi=>moshis,shishi1=>shishi1s,shige1=>shige1s,fenshi1=>fenshi1s,fenge1=>fenge1s,miaoshi1=>m iaoshi1s,miaoge1=>miaoge1s,shishi2=>shishi2s,shige2=>shige2s,fenshi2=>fenshi2s,fenge2=>fenge2s,miaoshi2=>m iaoshi2s,miaoge2=>miaoge2s,shishi3=>shishi3s,shige3=>shige3s,fenshi3=>fenshi3s,fenge3=>fenge3s,miaoshi3=>m iaoshi3s,miaoge3=>miaoge3s,fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>x miaoshis,xmiaoge=>xmiaoges,a0=>a0s,a1=>a1s,a3=>a3s,a4=>a4s,a6=>a6s,a7=>a7s);u6:miaobiao port map(clk_100=>clk_100s,moshi=>moshis,jian5=>jian5,jian4=>jian4,fenshi=>fenshis,fenge=>fenges,miaoshi=>miaoshis,miaoge=>miaoges,xmiaoshi=>xmiao shis,xmiaoge=>xmiaoges);u7:fenpin port map(clk_10M=>clk_10m,clk_10000=>clk_10000s,clk_100=>clk_100s,clk_1 =>clk_1s);u8:naozhongset port map(moshi=>moshis,jian5=>jian5,jian4=>jian4,shishi=>shishi3s,shige=>shige3s,fenshi=>fenshi3s,fenge=>fenge3s,miaoshi=>mi aoshi3s,miaoge=>miaoge3s);u9:naozhongspeaker port map(clk_100=>clk_100s,speaker=>speaker,shishi1=>shishi3s,shige1=>shige3s,fenshi1=>fenshi3s,fenge1=>fenge3s,miaoshi1=>m iaoshi3s,miaoge1=>miaoge3s,shishi2=>shishi1s,shige2=>shige1s,fenshi2=>fenshi1s,fenge2=>fenge1s,miaoshi2=>m iaoshi1s,miaoge2=>miaoge1s);end;。